llvm.org GIT mirror llvm / d8ff05e
Backport r293433, ARM: support `-mlong-calls` with AEABI TLS on ELF Support lowering AEABI TLS access (__aeabi_read_tp) with long calls. This requires adjusting the call sequence to use an indirect call to get full addressability. Resolves PR31769! By Saleem Abdulrasool! git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@295910 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 2 years ago
2 changed file(s) with 53 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
12241224 }
12251225 case ARM::tTPsoft:
12261226 case ARM::TPsoft: {
1227 const bool Thumb = Opcode == ARM::tTPsoft;
1228
12271229 MachineInstrBuilder MIB;
1228 if (Opcode == ARM::tTPsoft)
1230 if (STI->genLongCalls()) {
1231 MachineFunction *MF = MBB.getParent();
1232 MachineConstantPool *MCP = MF->getConstantPool();
1233 unsigned PCLabelID = AFI->createPICLabelUId();
1234 MachineConstantPoolValue *CPV =
1235 ARMConstantPoolSymbol::Create(MF->getFunction()->getContext(),
1236 "__aeabi_read_tp", PCLabelID, 0);
1237 unsigned Reg = MI.getOperand(0).getReg();
12291238 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1230 TII->get( ARM::tBL))
1231 .addImm((unsigned)ARMCC::AL).addReg(0)
1232 .addExternalSymbol("__aeabi_read_tp", 0);
1233 else
1239 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1240 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1241 if (!Thumb)
1242 MIB.addImm(0);
1243 MIB.addImm(static_cast(ARMCC::AL)).addReg(0);
1244
12341245 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1235 TII->get( ARM::BL))
1236 .addExternalSymbol("__aeabi_read_tp", 0);
1246 TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1247 if (Thumb)
1248 MIB.addImm(static_cast(ARMCC::AL)).addReg(0);
1249 MIB.addReg(Reg, RegState::Kill);
1250 } else {
1251 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1252 TII->get(Thumb ? ARM::tBL : ARM::BL));
1253 if (Thumb)
1254 MIB.addImm(static_cast(ARMCC::AL)).addReg(0);
1255 MIB.addExternalSymbol("__aeabi_read_tp", 0);
1256 }
12371257
12381258 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
12391259 TransferImpOps(MI, MIB, MIB);
0 ; RUN: llc -mtriple armv7---eabi -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-SHORT
1 ; RUN: llc -mtriple thumbv7---eabi -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-SHORT
2 ; RUN: llc -mtriple armv7---eabi -mattr=+long-calls -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-LONG
3 ; RUN: llc -mtriple thumbv7---eabi -mattr=+long-calls -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-LONG
4
5 @i = thread_local local_unnamed_addr global i32 0, align 4
6
7 define i32 @f() local_unnamed_addr {
8 entry:
9 %0 = load i32, i32* @i, align 4
10 ret i32 %0
11 }
12
13 ; CHECK-LABEL: f:
14 ; CHECK-SHORT: ldr r1, [[VAR:.LCPI[0-9]+_[0-9]+]]
15 ; CHECK-SHORT-NEXT: bl __aeabi_read_tp
16 ; CHECK-SHORT: [[VAR]]:
17 ; CHECK-SHORT-NEXT: .long i(TPOFF)
18
19 ; CHECK-LONG: ldr [[REG:r[0-9]+]], [[FUN:.LCPI[0-9]+_[0-9]+]]
20 ; CHECK-LONG-NEXT: ldr r1, [[VAR:.LCPI[0-9]+_[0-9]+]]
21 ; CHECK-LONG-NEXT: blx [[REG]]
22 ; CHECK-LONG: [[VAR]]:
23 ; CHECK-LONG-NEXT: .long i(TPOFF)
24 ; CHECK-LONG: [[FUN]]:
25 ; CHECK-LONG-NEXT: .long __aeabi_read_tp