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Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201059 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
8 changed file(s) with 35 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
270270 /// register SI/ESI/ERI with a possible segment override, and also the
271271 /// destination index register DI/ESI/RDI.
272272 RawFrmDstSrc = 10,
273
274 /// MRMX[rm] - The forms are used to represent instructions that use a
275 /// Mod/RM byte, and don't use the middle field for anything.
276 MRMXr = 14, MRMXm = 15,
273277
274278 /// MRM[0-7][rm] - These forms are used to represent instructions that use
275279 /// a Mod/RM byte, and use the middle field to hold extended opcode
673677 // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
674678 return FirstMemOp;
675679 }
680 case X86II::MRMXr:
676681 case X86II::MRM0r: case X86II::MRM1r:
677682 case X86II::MRM2r: case X86II::MRM3r:
678683 case X86II::MRM4r: case X86II::MRM5r:
679684 case X86II::MRM6r: case X86II::MRM7r:
680685 return -1;
686 case X86II::MRMXm:
681687 case X86II::MRM0m: case X86II::MRM1m:
682688 case X86II::MRM2m: case X86II::MRM3m:
683689 case X86II::MRM4m: case X86II::MRM5m:
14251425 break;
14261426 }
14271427
1428 case X86II::MRMXr:
14281429 case X86II::MRM0r: case X86II::MRM1r:
14291430 case X86II::MRM2r: case X86II::MRM3r:
14301431 case X86II::MRM4r: case X86II::MRM5r:
1431 case X86II::MRM6r: case X86II::MRM7r:
1432 case X86II::MRM6r: case X86II::MRM7r: {
14321433 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
14331434 ++CurOp;
14341435 EmitByte(BaseOpcode, CurByte, OS);
1436 uint64_t Form = TSFlags & X86II::FormMask;
14351437 EmitRegModRMByte(MI.getOperand(CurOp++),
1436 (TSFlags & X86II::FormMask)-X86II::MRM0r,
1438 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r,
14371439 CurByte, OS);
14381440 break;
1441 }
1442
1443 case X86II::MRMXm:
14391444 case X86II::MRM0m: case X86II::MRM1m:
14401445 case X86II::MRM2m: case X86II::MRM3m:
14411446 case X86II::MRM4m: case X86II::MRM5m:
1442 case X86II::MRM6m: case X86II::MRM7m:
1447 case X86II::MRM6m: case X86II::MRM7m: {
14431448 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
14441449 ++CurOp;
14451450 EmitByte(BaseOpcode, CurByte, OS);
1446 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
1451 uint64_t Form = TSFlags & X86II::FormMask;
1452 EmitMemModRMByte(MI, CurOp, (Form == X86II::MRMXm) ? 0 : Form-X86II::MRM0m,
14471453 TSFlags, CurByte, OS, Fixups, STI);
14481454 CurOp += X86::AddrNumOperands;
14491455 break;
1456 }
14501457 case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
14511458 case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
14521459 case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0:
12941294 break;
12951295 }
12961296
1297 case X86II::MRMXr:
12971298 case X86II::MRM0r: case X86II::MRM1r:
12981299 case X86II::MRM2r: case X86II::MRM3r:
12991300 case X86II::MRM4r: case X86II::MRM5r:
13011302 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
13021303 ++CurOp;
13031304 MCE.emitByte(BaseOpcode);
1305 uint64_t Form = (Desc->TSFlags & X86II::FormMask);
13041306 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
1305 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
1307 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r);
13061308
13071309 if (CurOp == NumOps)
13081310 break;
13311333 break;
13321334 }
13331335
1336 case X86II::MRMXm:
13341337 case X86II::MRM0m: case X86II::MRM1m:
13351338 case X86II::MRM2m: case X86II::MRM3m:
13361339 case X86II::MRM4m: case X86II::MRM5m:
13421345 X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0;
13431346
13441347 MCE.emitByte(BaseOpcode);
1345 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
1348 uint64_t Form = (Desc->TSFlags & X86II::FormMask);
1349 emitMemModRMByte(MI, CurOp, (Form==X86II::MRMXm) ? 0 : Form - X86II::MRM0m,
13461350 PCAdj);
13471351 CurOp += X86::AddrNumOperands;
13481352
8181 // SetCC instructions.
8282 multiclass SETCC opc, string Mnemonic, PatLeaf OpNode> {
8383 let Uses = [EFLAGS] in {
84 def r : I0r, (outs GR8:$dst), (ins),
84 def r : IXr, (outs GR8:$dst), (ins),
8585 !strconcat(Mnemonic, "\t$dst"),
8686 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
8787 IIC_SET_R>, TB, Sched<[WriteALU]>;
88 def m : I0m, (outs), (ins i8mem:$dst),
88 def m : IXm, (outs), (ins i8mem:$dst),
8989 !strconcat(Mnemonic, "\t$dst"),
9090 [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
9191 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
2323 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
2424 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>;
2525 def RawFrmDstSrc: Format<10>;
26 def MRMXr : Format<14>; def MRMXm : Format<15>;
2627 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
2728 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
2829 def MRM6r : Format<22>; def MRM7r : Format<23>;
927927 // Nop
928928 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
929929 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
930 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
930 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
931931 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
932 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
932 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
933933 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
934934 }
935935
76767676 let Predicates = [HasSSE4A] in {
76777677
76787678 let Constraints = "$src = $dst" in {
7679 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7679 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
76807680 (ins VR128:$src, i8imm:$len, i8imm:$idx),
76817681 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
76827682 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
6262 RawFrmSrc = 8,
6363 RawFrmDst = 9,
6464 RawFrmDstSrc = 10,
65 MRMXr = 14, MRMXm = 15,
6566 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
6667 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
6768 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
164165 form == X86Local::MRMDestMem ||
165166 form == X86Local::MRMSrcReg ||
166167 form == X86Local::MRMSrcMem ||
168 form == X86Local::MRMXr ||
169 form == X86Local::MRMXm ||
167170 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
168171 (form >= X86Local::MRM0m && form <= X86Local::MRM7m));
169172 }
177180 static bool isRegFormat(uint8_t form) {
178181 return (form == X86Local::MRMDestReg ||
179182 form == X86Local::MRMSrcReg ||
183 form == X86Local::MRMXr ||
180184 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
181185 }
182186
740744 HANDLE_OPTIONAL(immediate)
741745 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
742746 break;
747 case X86Local::MRMXr:
743748 case X86Local::MRM0r:
744749 case X86Local::MRM1r:
745750 case X86Local::MRM2r:
766771 HANDLE_OPTIONAL(relocation)
767772 HANDLE_OPTIONAL(immediate)
768773 break;
774 case X86Local::MRMXm:
769775 case X86Local::MRM0m:
770776 case X86Local::MRM1m:
771777 case X86Local::MRM2m: