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ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271667 91177308-0d34-0410-b5e6-96231b3b80d8 Sjoerd Meijer 4 years ago
7 changed file(s) with 105 addition(s) and 142 deletion(s). Raw diff Collapse all Expand all
257257 //===----------------------------------------------------------------------===//
258258 // ARM Assembler alias templates.
259259 //
260 class ARMInstAlias
261 : InstAlias, Requires<[IsARM]>;
262 class tInstAlias
263 : InstAlias, Requires<[IsThumb]>;
264 class t2InstAlias
265 : InstAlias, Requires<[IsThumb2]>;
266 class VFP2InstAlias
267 : InstAlias, Requires<[HasVFP2]>;
268 class VFP2DPInstAlias
269 : InstAlias, Requires<[HasVFP2,HasDPVFP]>;
270 class VFP3InstAlias
271 : InstAlias, Requires<[HasVFP3]>;
272 class NEONInstAlias
273 : InstAlias, Requires<[HasNEON]>;
260 // Note: When EmitPriority == 1, the alias will be used for printing
261 class ARMInstAlias
262 : InstAlias, Requires<[IsARM]>;
263 class tInstAlias
264 : InstAlias, Requires<[IsThumb]>;
265 class t2InstAlias
266 : InstAlias, Requires<[IsThumb2]>;
267 class VFP2InstAlias
268 : InstAlias, Requires<[HasVFP2]>;
269 class VFP2DPInstAlias
270 : InstAlias, Requires<[HasVFP2,HasDPVFP]>;
271 class VFP3InstAlias
272 : InstAlias, Requires<[HasVFP3]>;
273 class NEONInstAlias
274 : InstAlias, Requires<[HasNEON]>;
274275
275276
276277 class VFP2MnemonicAlias : MnemonicAlias,
24582459 }
24592460
24602461 // VFP/NEON Instruction aliases for type suffices.
2461 class VFPDataTypeInstAlias :
2462 InstAlias, Requires<[HasVFP2]>;
2463
2464 multiclass VFPDTAnyInstAlias {
2465 def : VFPDataTypeInstAlias;
2466 def : VFPDataTypeInstAlias;
2467 def : VFPDataTypeInstAlias;
2468 def : VFPDataTypeInstAlias;
2469 }
2470
2471 multiclass NEONDTAnyInstAlias {
2462 // Note: When EmitPriority == 1, the alias will be used for printing
2463 class VFPDataTypeInstAlias :
2464 InstAlias, Requires<[HasVFP2]>;
2465
2466 // Note: When EmitPriority == 1, the alias will be used for printing
2467 multiclass VFPDTAnyInstAlias {
2468 def : VFPDataTypeInstAlias;
2469 def : VFPDataTypeInstAlias;
2470 def : VFPDataTypeInstAlias;
2471 def : VFPDataTypeInstAlias;
2472 }
2473
2474 // Note: When EmitPriority == 1, the alias will be used for printing
2475 multiclass NEONDTAnyInstAlias {
24722476 let Predicates = [HasNEON] in {
2473 def : VFPDataTypeInstAlias;
2474 def : VFPDataTypeInstAlias;
2475 def : VFPDataTypeInstAlias;
2476 def : VFPDataTypeInstAlias64", asm, Result>;
2477 def : VFPDataTypeInstAlias8", asm, Result, EmitPriority>;
2478 def : VFPDataTypeInstAlias;
2479 def : VFPDataTypeInstAlias;
2480 def : VFPDataTypeInstAlias;
24772481 }
24782482 }
24792483
19441944 let Inst{7-4} = 0b0111;
19451945 }
19461946 // default immediate for breakpoint mnemonic
1947 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1947 def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>;
19481948
19491949 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
19501950 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
33323332 }
33333333
33343334 def : InstAlias<"mov${p} $Rd, $imm",
3335 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3335 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
33363336 Requires<[IsARM, HasV6T2]>;
33373337
33383338 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
51865186 let Unpredictable{11-0} = 0b110100001111;
51875187 }
51885188
5189 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5189 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>,
51905190 Requires<[IsARM]>;
51915191
51925192 // The MRSsys instruction is the MRS instruction from the ARM ARM,
55925592 //
55935593
55945594 // Memory barriers
5595 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5596 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5597 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5595 def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>;
5596 def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>;
5597 def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>;
55985598
55995599 // System instructions
56005600 def : MnemonicAlias<"swi", "svc">;
56105610 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
56115611 // input operands swapped when the shift amount is zero (i.e., unspecified).
56125612 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5613 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5613 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>,
56145614 Requires<[IsARM, HasV6]>;
56155615 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5616 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p)>,
5616 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>,
56175617 Requires<[IsARM, HasV6]>;
56185618
56195619 // PUSH/POP aliases for STM/LDM
57715771 // the instruction definitions need difference constraints pre-v6.
57725772 // Use these aliases for the assembly parsing on pre-v6.
57735773 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5774 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5774 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>,
57755775 Requires<[IsARM, NoV6]>;
57765776 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
57775777 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5778 pred:$p, cc_out:$s)>,
5778 pred:$p, cc_out:$s), 0>,
57795779 Requires<[IsARM, NoV6]>;
57805780 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5781 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5781 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
57825782 Requires<[IsARM, NoV6]>;
57835783 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5784 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5784 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
57855785 Requires<[IsARM, NoV6]>;
57865786 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5787 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5787 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
57885788 Requires<[IsARM, NoV6]>;
57895789 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5790 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5790 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
57915791 Requires<[IsARM, NoV6]>;
57925792
57935793 // 'it' blocks in ARM mode just validate the predicates. The IT itself
273273 let Inst{7-4} = imm;
274274 }
275275
276 class tHintAlias : tInstAlias {
276 // Note: When EmitPriority == 1, the alias will be used for printing
277 class tHintAlias : tInstAlias {
277278 let Predicates = [IsThumb, HasV6M];
278279 }
279280
280 def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110
281 def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410
282 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408
283 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409
284 def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157
285 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> {
281 def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110
282 def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410
283 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408
284 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409
285 def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157
286 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> {
286287 let Predicates = [IsThumb2, HasV8];
287288 }
288289
297298 let Inst{7-0} = val;
298299 }
299300 // default immediate for breakpoint mnemonic
300 def : InstAlias<"bkpt", (tBKPT 0)>, Requires<[IsThumb]>;
301 def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>;
301302
302303 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
303304 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {
783784 } // hasSideEffects
784785
785786 def : InstAlias<"ldm${p} $Rn!, $regs",
786 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
787 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
787788 Requires<[IsThumb, IsThumb1Only]>;
788789
789790 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
15151516
15161517 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
15171518 // encoding is available on ARMv6K, but we don't differentiate that finely.
1518 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1519 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0), 0>, Requires<[IsThumb, IsThumb1Only]>;
15191520
15201521
15211522 // For round-trip assembly/disassembly, we have to handle a CPS instruction
19231923 }
19241924
19251925 def : InstAlias<"mov${p} $Rd, $imm",
1926 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>,
1926 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
19271927 Requires<[IsThumb, HasV8MBaseline]>;
19281928
19291929 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
19971997 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
19981998 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
19991999 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
2000 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2000 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
20012001
20022002 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
20032003 // The transformation should probably be done as a combiner action
37193719 let Inst{7-0} = imm;
37203720 }
37213721
3722 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p)>;
3723 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
3724 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
3725 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
3726 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
3727 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
3728 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p)> {
3722 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;
3723 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
3724 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;
3725 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;
3726 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;
3727 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
3728 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
37293729 let Predicates = [IsThumb2, HasV8];
37303730 }
37313731
38523852 // ERET - Return from exception in Hypervisor mode.
38533853 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
38543854 // includes virtualization extensions.
3855 def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p)>,
3855 def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,
38563856 Requires<[IsThumb2, HasVirtualization]>;
38573857
38583858 //===----------------------------------------------------------------------===//
45264526 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
45274527
45284528 // Memory barriers
4529 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p)>, Requires<[HasDB]>;
4530 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p)>, Requires<[HasDB]>;
4531 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p)>, Requires<[HasDB]>;
4529 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4530 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4531 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
45324532
45334533 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
45344534 // width specifier.
45764576 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
45774577 // input operands swapped when the shift amount is zero (i.e., unspecified).
45784578 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4579 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4579 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
45804580 Requires<[HasT2ExtractPack, IsThumb2]>;
45814581 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4582 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p)>,
4582 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
45834583 Requires<[HasT2ExtractPack, IsThumb2]>;
45844584
45854585 // PUSH/POP aliases for STM/LDM
46584658
46594659 // Extend instruction optional rotate operand.
46604660 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4661 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4661 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
46624662 Requires<[HasT2ExtractPack, IsThumb2]>;
46634663 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4664 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4664 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
46654665 Requires<[HasT2ExtractPack, IsThumb2]>;
46664666 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4667 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4667 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
46684668 Requires<[HasT2ExtractPack, IsThumb2]>;
46694669 def : InstAlias<"sxtb16${p} $Rd, $Rm",
4670 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>,
4670 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
46714671 Requires<[HasT2ExtractPack, IsThumb2]>;
46724672
46734673 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
46804680 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
46814681
46824682 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4683 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4683 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
46844684 Requires<[HasT2ExtractPack, IsThumb2]>;
46854685 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4686 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4686 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
46874687 Requires<[HasT2ExtractPack, IsThumb2]>;
46884688 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4689 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4689 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
46904690 Requires<[HasT2ExtractPack, IsThumb2]>;
46914691 def : InstAlias<"uxtb16${p} $Rd, $Rm",
4692 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>,
4692 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
46934693 Requires<[HasT2ExtractPack, IsThumb2]>;
46944694
46954695 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
47054705 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
47064706 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
47074707 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4708 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>,
4708 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
47094709 Requires<[HasT2ExtractPack, IsThumb2]>;
47104710 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
47114711 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
47134713 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
47144714 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
47154715 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4716 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>,
4716 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
47174717 Requires<[HasT2ExtractPack, IsThumb2]>;
47184718 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
47194719 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
48114811 def : t2InstAlias<"pld${p} $addr",
48124812 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
48134813 def : InstAlias<"pli${p} $addr",
4814 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p)>,
4814 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
48154815 Requires<[IsThumb2,HasV7]>;
273273 def : VFP2MnemonicAlias<"fstmead", "vstmia">;
274274 def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;
275275
276 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
276 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>,
277277 Requires<[HasVFP2]>;
278 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
278 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>,
279279 Requires<[HasVFP2]>;
280 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
280 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>,
281281 Requires<[HasVFP2]>;
282 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
282 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>,
283283 Requires<[HasVFP2]>;
284284 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
285285 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
889889 }
890890
891891 def : InstAlias
892 (!cast(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p)>,
892 (!cast(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
893893 Requires<[HasFullFP16]>;
894894 def : InstAlias
895 (!cast(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
895 (!cast(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
896896 Requires<[HasFPARMv8]>;
897897 def : InstAlias
898 (!cast(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
898 (!cast(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>,
899899 Requires<[HasFPARMv8,HasDPVFP]>;
900900 }
901901
930930 }
931931
932932 def : InstAlias
933 (!cast(NAME#"S") SPR:$Sd, SPR:$Sm)>,
933 (!cast(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
934934 Requires<[HasFPARMv8]>;
935935 def : InstAlias
936 (!cast(NAME#"D") DPR:$Dd, DPR:$Dm)>,
936 (!cast(NAME#"D") DPR:$Dd, DPR:$Dm), 0>,
937937 Requires<[HasFPARMv8,HasDPVFP]>;
938938 }
939939
2424
2525 #define DEBUG_TYPE "asm-printer"
2626
27 #define PRINT_ALIAS_INSTR
2728 #include "ARMGenAsmWriter.inc"
2829
2930 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
7172 unsigned Opcode = MI->getOpcode();
7273
7374 switch (Opcode) {
74
75 // Check for HINT instructions w/ canonical names.
76 case ARM::HINT:
77 case ARM::tHINT:
78 case ARM::t2HINT:
79 switch (MI->getOperand(0).getImm()) {
80 case 0:
81 O << "\tnop";
82 break;
83 case 1:
84 O << "\tyield";
85 break;
86 case 2:
87 O << "\twfe";
88 break;
89 case 3:
90 O << "\twfi";
91 break;
92 case 4:
93 O << "\tsev";
94 break;
95 case 5:
96 if (STI.getFeatureBits()[ARM::HasV8Ops]) {
97 O << "\tsevl";
98 break;
99 } // Fallthrough for non-v8
100 default:
101 // Anything else should just print normally.
102 printInstruction(MI, STI, O);
103 printAnnotation(O, Annot);
104 return;
105 }
106 printPredicateOperand(MI, 1, STI, O);
107 if (Opcode == ARM::t2HINT)
108 O << ".w";
109 printAnnotation(O, Annot);
110 return;
11175
11276 // Check for MOVs and print canonical forms, instead.
11377 case ARM::MOVsr: {
296260 }
297261 break;
298262 }
299 // B9.3.3 ERET (Thumb)
300 // For a target that has Virtualization Extensions, ERET is the preferred
301 // disassembly of SUBS PC, LR, #0
302 case ARM::t2SUBS_PC_LR: {
303 if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
304 MI->getOperand(0).getImm() == 0 &&
305 STI.getFeatureBits()[ARM::FeatureVirtualization]) {
306 O << "\teret";
307 printPredicateOperand(MI, 1, STI, O);
308 printAnnotation(O, Annot);
309 return;
310 }
311 break;
312 }
313 }
314
315 printInstruction(MI, STI, O);
263 }
264
265 if (!printAliasInstr(MI, STI, O))
266 printInstruction(MI, STI, O);
267
316268 printAnnotation(O, Annot);
317269 }
318270
2929 // Autogenerated by tblgen.
3030 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
3131 raw_ostream &O);
32 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
33 raw_ostream &O);
34 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
35 unsigned PrintMethodIdx,
36 const MCSubtargetInfo &STI,
37 raw_ostream &O);
3238 static const char *getRegisterName(unsigned RegNo);
3339
3440 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,