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[ARM GlobalISel] Select G_FCONSTANT into pools Put all floating point constants into constant pools and load their values from there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358062 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 9 months ago
2 changed file(s) with 156 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
957957 MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
958958 break;
959959 }
960 case G_FCONSTANT: {
961 // Load from constant pool
962 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits() / 8;
963 unsigned Alignment = Size;
964
965 assert((Size == 4 || Size == 8) && "Unsupported FP constant type");
966 auto LoadOpcode = Size == 4 ? ARM::VLDRS : ARM::VLDRD;
967
968 auto ConstPool = MF.getConstantPool();
969 auto CPIndex =
970 ConstPool->getConstantPoolIndex(I.getOperand(1).getFPImm(), Alignment);
971 MIB->setDesc(TII.get(LoadOpcode));
972 MIB->RemoveOperand(1);
973 MIB.addConstantPoolIndex(CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
974 .addMemOperand(
975 MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
976 MachineMemOperand::MOLoad, Size, Alignment))
977 .addImm(0)
978 .add(predOps(ARMCC::AL));
979 break;
980 }
960981 case G_INTTOPTR:
961982 case G_PTRTOINT: {
962983 auto SrcReg = I.getOperand(1).getReg();
0 # RUN: llc -O0 -mtriple arm-- -mattr=+vfp3,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP3
1 # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp3,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP3
2 # RUN: llc -O0 -mtriple arm-- -mattr=+vfp2,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP2
3 # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp2,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP2
4 --- |
5 define void @test_fpconst_zero_s32() { ret void }
6 define void @test_fpconst_zero_s64() { ret void }
7
8 define void @test_fpconst_8bit_s32() { ret void }
9 define void @test_fpconst_8bit_s64() { ret void }
10 ...
11 ---
12 name: test_fpconst_zero_s32
13 # CHECK-LABEL: name: test_fpconst_zero_s32
14 legalized: true
15 regBankSelected: true
16 selected: false
17 # CHECK: selected: true
18 registers:
19 - { id: 0, class: gprb }
20 - { id: 1, class: fprb }
21 # CHECK: constants:
22 # CHECK-NEXT: id: 0
23 # CHECK-NEXT: value: 'float 0.000000e+00'
24 # CHECK-NEXT: alignment: 4
25 # CHECK-NEXT: isTargetSpecific: false
26 body: |
27 bb.0:
28 liveins: $r0
29
30 %0(p0) = COPY $r0
31 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
32
33 %1(s32) = G_FCONSTANT float 0.0
34 ; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
35
36 G_STORE %1(s32), %0 :: (store 4)
37 ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14, $noreg
38
39 BX_RET 14, $noreg
40 ; CHECK: BX_RET 14, $noreg
41 ...
42 ---
43 name: test_fpconst_zero_s64
44 # CHECK-LABEL: name: test_fpconst_zero_s64
45 legalized: true
46 regBankSelected: true
47 selected: false
48 # CHECK: selected: true
49 registers:
50 - { id: 0, class: gprb }
51 - { id: 1, class: fprb }
52 # CHECK: constants:
53 # CHECK-NEXT: id: 0
54 # CHECK-NEXT: value: 'double 0.000000e+00'
55 # CHECK-NEXT: alignment: 8
56 # CHECK-NEXT: isTargetSpecific: false
57 body: |
58 bb.0:
59 liveins: $r0
60
61 %0(p0) = COPY $r0
62 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
63
64 %1(s64) = G_FCONSTANT double 0.0
65 ; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool)
66
67 G_STORE %1(s64), %0 :: (store 8)
68 ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14, $noreg
69
70 BX_RET 14, $noreg
71 ; CHECK: BX_RET 14, $noreg
72 ...
73 ---
74 name: test_fpconst_8bit_s32
75 # CHECK-LABEL: name: test_fpconst_8bit_s32
76 legalized: true
77 regBankSelected: true
78 selected: false
79 # CHECK: selected: true
80 registers:
81 - { id: 0, class: gprb }
82 - { id: 1, class: fprb }
83 # CHECK: constants:
84 # CHECK-NEXT: id: 0
85 # CHECK-NEXT: value: 'float -2.000000e+00'
86 # CHECK-NEXT: alignment: 4
87 # CHECK-NEXT: isTargetSpecific: false
88 body: |
89 bb.0:
90 liveins: $r0
91
92 %0(p0) = COPY $r0
93 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
94
95 %1(s32) = G_FCONSTANT float -2.0
96 ; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
97
98 G_STORE %1(s32), %0 :: (store 4)
99 ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14, $noreg
100
101 BX_RET 14, $noreg
102 ; CHECK: BX_RET 14, $noreg
103 ...
104 ---
105 name: test_fpconst_8bit_s64
106 # CHECK-LABEL: name: test_fpconst_8bit_s64
107 legalized: true
108 regBankSelected: true
109 selected: false
110 # CHECK: selected: true
111 registers:
112 - { id: 0, class: gprb }
113 - { id: 1, class: fprb }
114 # CHECK: constants:
115 # CHECK-NEXT: id: 0
116 # CHECK-NEXT: value: double 5.000000e-01
117 # CHECK-NEXT: alignment: 8
118 # CHECK-NEXT: isTargetSpecific: false
119 body: |
120 bb.0:
121 liveins: $r0
122
123 %0(p0) = COPY $r0
124 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
125
126 %1(s64) = G_FCONSTANT double 5.0e-1
127 ; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool)
128
129 G_STORE %1(s64), %0 :: (store 8)
130 ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14, $noreg
131
132 BX_RET 14, $noreg
133 ; CHECK: BX_RET 14, $noreg
134 ...