llvm.org GIT mirror llvm / d8c108c
Merging r322372 and r322767: ------------------------------------------------------------------------ r322372 | nemanjai | 2018-01-12 15:58:41 +0100 (Fri, 12 Jan 2018) | 10 lines [PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAP Part of the fix for https://bugs.llvm.org/show_bug.cgi?id=35812. This patch ensures that the compare operand for the atomic compare and swap is properly zero-extended to 32 bits if applicable. A follow-up commit will fix the extension for the SETCC node generated when expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS. That will complete the bug fix. Differential Revision: https://reviews.llvm.org/D41856 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r322767 | efriedma | 2018-01-17 23:04:36 +0100 (Wed, 17 Jan 2018) | 12 lines [LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization. The code wasn't zero-extending correctly, so the comparison could spuriously fail. Adds some AArch64 tests to cover this case. Inspired by D41791. Differential Revision: https://reviews.llvm.org/D41798 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323334 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 1 year, 11 months ago
9 changed file(s) with 246 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
29642964 case ISD::ZERO_EXTEND:
29652965 LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
29662966 DAG.getValueType(AtomicType));
2967 RHS = DAG.getNode(ISD::ZERO_EXTEND, dl, OuterType, Node->getOperand(2));
2967 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
29682968 ExtRes = LHS;
29692969 break;
29702970 case ISD::ANY_EXTEND:
29712971 LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType);
2972 RHS = DAG.getNode(ISD::ZERO_EXTEND, dl, OuterType, Node->getOperand(2));
2972 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
29732973 break;
29742974 default:
29752975 llvm_unreachable("Invalid atomic op extension");
141141 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
142142 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
143143
144 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
145 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
146
144147 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
145148 for (MVT VT : MVT::integer_valuetypes()) {
146149 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
11531156 case PPCISD::Hi: return "PPCISD::Hi";
11541157 case PPCISD::Lo: return "PPCISD::Lo";
11551158 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1159 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1160 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
11561161 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
11571162 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
11581163 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
88338838 return Op;
88348839 }
88358840
8841 // ATOMIC_CMP_SWAP for i8/i16 needs to zero-extend its input since it will be
8842 // compared to a value that is atomically loaded (atomic loads zero-extend).
8843 SDValue PPCTargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op,
8844 SelectionDAG &DAG) const {
8845 assert(Op.getOpcode() == ISD::ATOMIC_CMP_SWAP &&
8846 "Expecting an atomic compare-and-swap here.");
8847 SDLoc dl(Op);
8848 auto *AtomicNode = cast(Op.getNode());
8849 EVT MemVT = AtomicNode->getMemoryVT();
8850 if (MemVT.getSizeInBits() >= 32)
8851 return Op;
8852
8853 SDValue CmpOp = Op.getOperand(2);
8854 // If this is already correctly zero-extended, leave it alone.
8855 auto HighBits = APInt::getHighBitsSet(32, 32 - MemVT.getSizeInBits());
8856 if (DAG.MaskedValueIsZero(CmpOp, HighBits))
8857 return Op;
8858
8859 // Clear the high bits of the compare operand.
8860 unsigned MaskVal = (1 << MemVT.getSizeInBits()) - 1;
8861 SDValue NewCmpOp =
8862 DAG.getNode(ISD::AND, dl, MVT::i32, CmpOp,
8863 DAG.getConstant(MaskVal, dl, MVT::i32));
8864
8865 // Replace the existing compare operand with the properly zero-extended one.
8866 SmallVector Ops;
8867 for (int i = 0, e = AtomicNode->getNumOperands(); i < e; i++)
8868 Ops.push_back(AtomicNode->getOperand(i));
8869 Ops[2] = NewCmpOp;
8870 MachineMemOperand *MMO = AtomicNode->getMemOperand();
8871 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::Other);
8872 auto NodeTy =
8873 (MemVT == MVT::i8) ? PPCISD::ATOMIC_CMP_SWAP_8 : PPCISD::ATOMIC_CMP_SWAP_16;
8874 return DAG.getMemIntrinsicNode(NodeTy, dl, Tys, Ops, MemVT, MMO);
8875 }
8876
88368877 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
88378878 SelectionDAG &DAG) const {
88388879 SDLoc dl(Op);
93249365 return LowerREM(Op, DAG);
93259366 case ISD::BSWAP:
93269367 return LowerBSWAP(Op, DAG);
9368 case ISD::ATOMIC_CMP_SWAP:
9369 return LowerATOMIC_CMP_SWAP(Op, DAG);
93279370 }
93289371 }
93299372
428428 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
429429 /// The 4xf32 load used for v4i1 constants.
430430 QVLFSb,
431
432 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
433 /// except they ensure that the compare input is zero-extended for
434 /// sub-word versions because the atomic loads zero-extend.
435 ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16,
431436
432437 /// GPRC = TOC_ENTRY GA, TOC
433438 /// Loads the entry for GA from the TOC, where the TOC base is given by
954959 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
955960 SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const;
956961 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
962 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
957963 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
958964 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
959965 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
256256 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
257257 [SDNPHasChain, SDNPOptInGlue]>;
258258
259 // PPC-specific atomic operations.
260 def PPCatomicCmpSwap_8 :
261 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3,
262 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
263 def PPCatomicCmpSwap_16 :
264 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3,
265 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
259266 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
260267 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
261268 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
17091716 }
17101717 }
17111718
1719 def : Pat<(PPCatomicCmpSwap_8 xoaddr:$ptr, i32:$old, i32:$new),
1720 (ATOMIC_CMP_SWAP_I8 xoaddr:$ptr, i32:$old, i32:$new)>;
1721 def : Pat<(PPCatomicCmpSwap_16 xoaddr:$ptr, i32:$old, i32:$new),
1722 (ATOMIC_CMP_SWAP_I16 xoaddr:$ptr, i32:$old, i32:$new)>;
1723
17121724 // Instructions to support atomic operations
17131725 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
17141726 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
628628
629629 ; CHECK-NOT: dmb
630630 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
631 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
632
633 ; CHECK: casab w[[NEW:[0-9]+]], w[[OLD:[0-9]+]], [x[[ADDR]]]
634 ; CHECK-NOT: dmb
635
636 ret i8 %old
631 ; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
632 ; CHECK-NEXT: casab w0, w1, [x[[ADDR]]]
633 ; CHECK-NEXT: ret
634
635 ret i8 %old
636 }
637
638 define i1 @test_atomic_cmpxchg_i8_1(i8 %wanted, i8 %new) nounwind {
639 ; CHECK-LABEL: test_atomic_cmpxchg_i8_1:
640 %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire
641 %success = extractvalue { i8, i1 } %pair, 1
642
643 ; CHECK-NOT: dmb
644 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
645 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
646
647 ; CHECK: casab w[[NEW:[0-9]+]], w1, [x[[ADDR]]]
648 ; CHECK-NEXT: cmp w[[NEW]], w0, uxtb
649 ; CHECK-NEXT: cset w0, eq
650 ; CHECK-NEXT: ret
651 ret i1 %success
637652 }
638653
639654 define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
643658
644659 ; CHECK-NOT: dmb
645660 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
646 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
647
648 ; CHECK: casah w0, w1, [x[[ADDR]]]
649 ; CHECK-NOT: dmb
650
651 ret i16 %old
661 ; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
662 ; CHECK-NEXT: casah w0, w1, [x[[ADDR]]]
663 ; CHECK-NEXT: ret
664
665 ret i16 %old
666 }
667
668 define i1 @test_atomic_cmpxchg_i16_1(i16 %wanted, i16 %new) nounwind {
669 ; CHECK-LABEL: test_atomic_cmpxchg_i16_1:
670 %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new acquire acquire
671 %success = extractvalue { i16, i1 } %pair, 1
672
673 ; CHECK-NOT: dmb
674 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
675 ; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
676
677 ; CHECK: casah w[[NEW:[0-9]+]], w1, [x[[ADDR]]]
678 ; CHECK-NEXT: cmp w[[NEW]], w0, uxth
679 ; CHECK-NEXT: cset w0, eq
680 ; CHECK-NEXT: ret
681
682 ret i1 %success
652683 }
653684
654685 define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
4848 ; CHECK-THUMBV6: mov [[EXPECTED:r[0-9]+]], r1
4949 ; CHECK-THUMBV6-NEXT: bl __sync_val_compare_and_swap_1
5050 ; CHECK-THUMBV6-NEXT: mov [[RES:r[0-9]+]], r0
51 ; CHECK-THUMBV6-NEXT: uxtb [[EXPECTED_ZEXT:r[0-9]+]], [[EXPECTED]]
5152 ; CHECK-THUMBV6-NEXT: movs r0, #1
5253 ; CHECK-THUMBV6-NEXT: movs [[ZERO:r[0-9]+]], #0
53 ; CHECK-THUMBV6-NEXT: cmp [[RES]], [[EXPECTED]]
54 ; CHECK-THUMBV6-NEXT: cmp [[RES]], [[EXPECTED_ZEXT]]
5455 ; CHECK-THUMBV6-NEXT: beq [[END:.LBB[0-9_]+]]
5556 ; CHECK-THUMBV6-NEXT: mov r0, [[ZERO]]
5657 ; CHECK-THUMBV6-NEXT: [[END]]:
1616 ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
1717 ; CHECK: bne [[RETRY]]
1818 ; CHECK: [[DONE]]:
19 ; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED]]
19 ; CHECK: uxtb [[DESIRED_ZEXT:r[0-9]+]], [[DESIRED]]
20 ; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED_ZEXT]]
2021 ; CHECK: {{moveq|movweq}} {{r[0-9]+}}, #1
2122 ; CHECK: dmb ish
2223 %res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic
3536 ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
3637 ; CHECK: bne [[RETRY]]
3738 ; CHECK: [[DONE]]:
38 ; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED]]
39 ; CHECK: uxth [[DESIRED_ZEXT:r[0-9]+]], [[DESIRED]]
40 ; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED_ZEXT]]
3941 ; CHECK: {{moveq|movweq}} {{r[0-9]+}}, #1
4042 ; CHECK: dmb ish
4143 %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; Make sure that a negative value for the compare-and-swap is zero extended
2 ; from i8/i16 to i32 since it will be compared for equality.
3 ; RUN: llc -mtriple=powerpc64le-linux-gnu -verify-machineinstrs < %s | FileCheck %s
4 ; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-P7
5
6 @str = private unnamed_addr constant [46 x i8] c"FAILED: __atomic_compare_exchange_n() failed.\00"
7 @str.1 = private unnamed_addr constant [59 x i8] c"FAILED: __atomic_compare_exchange_n() set the wrong value.\00"
8 @str.2 = private unnamed_addr constant [7 x i8] c"PASSED\00"
9
10 define signext i32 @main() {
11 ; CHECK-LABEL: main:
12 ; CHECK: li 3, -32477
13 ; CHECK: lis 12, 0
14 ; CHECK: li 6, 234
15 ; CHECK: sth 3, 46(1)
16 ; CHECK: ori 4, 12, 33059
17 ; CHECK: sync
18 ; CHECK: .LBB0_1: # %L.entry
19 ; CHECK: lharx 3, 0, 5
20 ; CHECK: cmpw 4, 3
21 ; CHECK: bne 0, .LBB0_3
22 ; CHECK: sthcx. 6, 0, 5
23 ; CHECK: bne 0, .LBB0_1
24 ; CHECK: b .LBB0_4
25 ; CHECK: .LBB0_3: # %L.entry
26 ; CHECK: sthcx. 3, 0, 5
27 ; CHECK: .LBB0_4: # %L.entry
28 ; CHECK: cmplwi 3, 33059
29 ; CHECK: lwsync
30 ; CHECK: lhz 3, 46(1)
31 ; CHECK: cmplwi 3, 234
32 ;
33 ; CHECK-P7-LABEL: main:
34 ; CHECK-P7: lis 4, 0
35 ; CHECK-P7: li 7, 0
36 ; CHECK-P7: li 3, -32477
37 ; CHECK-P7: sth 3, 46(1)
38 ; CHECK-P7: li 5, 234
39 ; CHECK-P7: ori 4, 4, 33059
40 ; CHECK-P7: rlwinm 3, 6, 3, 27, 27
41 ; CHECK-P7: ori 7, 7, 65535
42 ; CHECK-P7: sync
43 ; CHECK-P7: slw 8, 5, 3
44 ; CHECK-P7: slw 5, 7, 3
45 ; CHECK-P7: slw 9, 4, 3
46 ; CHECK-P7: and 7, 8, 5
47 ; CHECK-P7: rldicr 4, 6, 0, 61
48 ; CHECK-P7: and 8, 9, 5
49 ; CHECK-P7: .LBB0_1: # %L.entry
50 ; CHECK-P7: lwarx 9, 0, 4
51 ; CHECK-P7: and 6, 9, 5
52 ; CHECK-P7: cmpw 0, 6, 8
53 ; CHECK-P7: bne 0, .LBB0_3
54 ; CHECK-P7: andc 9, 9, 5
55 ; CHECK-P7: or 9, 9, 7
56 ; CHECK-P7: stwcx. 9, 0, 4
57 ; CHECK-P7: bne 0, .LBB0_1
58 ; CHECK-P7: b .LBB0_4
59 ; CHECK-P7: .LBB0_3: # %L.entry
60 ; CHECK-P7: stwcx. 9, 0, 4
61 ; CHECK-P7: .LBB0_4: # %L.entry
62 ; CHECK-P7: srw 3, 6, 3
63 ; CHECK-P7: lwsync
64 ; CHECK-P7: cmplwi 3, 33059
65 ; CHECK-P7: lhz 3, 46(1)
66 ; CHECK-P7: cmplwi 3, 234
67 L.entry:
68 %value.addr = alloca i16, align 2
69 store i16 -32477, i16* %value.addr, align 2
70 %0 = cmpxchg i16* %value.addr, i16 -32477, i16 234 seq_cst seq_cst
71 %1 = extractvalue { i16, i1 } %0, 1
72 br i1 %1, label %L.B0000, label %L.B0003
73
74 L.B0003: ; preds = %L.entry
75 %puts = call i32 @puts(i8* getelementptr inbounds ([46 x i8], [46 x i8]* @str, i64 0, i64 0))
76 ret i32 1
77
78 L.B0000: ; preds = %L.entry
79 %2 = load i16, i16* %value.addr, align 2
80 %3 = icmp eq i16 %2, 234
81 br i1 %3, label %L.B0001, label %L.B0005
82
83 L.B0005: ; preds = %L.B0000
84 %puts1 = call i32 @puts(i8* getelementptr inbounds ([59 x i8], [59 x i8]* @str.1, i64 0, i64 0))
85 ret i32 1
86
87 L.B0001: ; preds = %L.B0000
88 %puts2 = call i32 @puts(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @str.2, i64 0, i64 0))
89 ret i32 0
90 }
91
92 ; Function Attrs: nounwind
93 declare i32 @puts(i8* nocapture readonly) #0
403403 define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
404404 ; PPC64LE-LABEL: test40:
405405 ; PPC64LE: # %bb.0:
406 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
406407 ; PPC64LE-NEXT: b .LBB40_2
407408 ; PPC64LE-NEXT: .p2align 5
408409 ; PPC64LE-NEXT: .LBB40_1:
422423 define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
423424 ; PPC64LE-LABEL: test41:
424425 ; PPC64LE: # %bb.0:
426 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
425427 ; PPC64LE-NEXT: .LBB41_1:
426428 ; PPC64LE-NEXT: lbarx 6, 0, 3
427429 ; PPC64LE-NEXT: cmpw 4, 6
443445 define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
444446 ; PPC64LE-LABEL: test42:
445447 ; PPC64LE: # %bb.0:
448 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
446449 ; PPC64LE-NEXT: .LBB42_1:
447450 ; PPC64LE-NEXT: lbarx 6, 0, 3
448451 ; PPC64LE-NEXT: cmpw 4, 6
464467 define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
465468 ; PPC64LE-LABEL: test43:
466469 ; PPC64LE: # %bb.0:
470 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
467471 ; PPC64LE-NEXT: lwsync
468472 ; PPC64LE-NEXT: b .LBB43_2
469473 ; PPC64LE-NEXT: .p2align 5
484488 define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
485489 ; PPC64LE-LABEL: test44:
486490 ; PPC64LE: # %bb.0:
491 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
487492 ; PPC64LE-NEXT: lwsync
488493 ; PPC64LE-NEXT: b .LBB44_2
489494 ; PPC64LE-NEXT: .p2align 5
504509 define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
505510 ; PPC64LE-LABEL: test45:
506511 ; PPC64LE: # %bb.0:
512 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
507513 ; PPC64LE-NEXT: lwsync
508514 ; PPC64LE-NEXT: .LBB45_1:
509515 ; PPC64LE-NEXT: lbarx 6, 0, 3
526532 define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
527533 ; PPC64LE-LABEL: test46:
528534 ; PPC64LE: # %bb.0:
535 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
529536 ; PPC64LE-NEXT: lwsync
530537 ; PPC64LE-NEXT: .LBB46_1:
531538 ; PPC64LE-NEXT: lbarx 6, 0, 3
548555 define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
549556 ; PPC64LE-LABEL: test47:
550557 ; PPC64LE: # %bb.0:
558 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
551559 ; PPC64LE-NEXT: sync
552560 ; PPC64LE-NEXT: .LBB47_1:
553561 ; PPC64LE-NEXT: lbarx 6, 0, 3
570578 define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
571579 ; PPC64LE-LABEL: test48:
572580 ; PPC64LE: # %bb.0:
581 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
573582 ; PPC64LE-NEXT: sync
574583 ; PPC64LE-NEXT: .LBB48_1:
575584 ; PPC64LE-NEXT: lbarx 6, 0, 3
592601 define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
593602 ; PPC64LE-LABEL: test49:
594603 ; PPC64LE: # %bb.0:
604 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
595605 ; PPC64LE-NEXT: sync
596606 ; PPC64LE-NEXT: .LBB49_1:
597607 ; PPC64LE-NEXT: lbarx 6, 0, 3
614624 define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
615625 ; PPC64LE-LABEL: test50:
616626 ; PPC64LE: # %bb.0:
627 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
617628 ; PPC64LE-NEXT: b .LBB50_2
618629 ; PPC64LE-NEXT: .p2align 5
619630 ; PPC64LE-NEXT: .LBB50_1:
633644 define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
634645 ; PPC64LE-LABEL: test51:
635646 ; PPC64LE: # %bb.0:
647 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
636648 ; PPC64LE-NEXT: .LBB51_1:
637649 ; PPC64LE-NEXT: lharx 6, 0, 3
638650 ; PPC64LE-NEXT: cmpw 4, 6
654666 define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
655667 ; PPC64LE-LABEL: test52:
656668 ; PPC64LE: # %bb.0:
669 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
657670 ; PPC64LE-NEXT: .LBB52_1:
658671 ; PPC64LE-NEXT: lharx 6, 0, 3
659672 ; PPC64LE-NEXT: cmpw 4, 6
675688 define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
676689 ; PPC64LE-LABEL: test53:
677690 ; PPC64LE: # %bb.0:
691 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
678692 ; PPC64LE-NEXT: lwsync
679693 ; PPC64LE-NEXT: b .LBB53_2
680694 ; PPC64LE-NEXT: .p2align 5
695709 define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
696710 ; PPC64LE-LABEL: test54:
697711 ; PPC64LE: # %bb.0:
712 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
698713 ; PPC64LE-NEXT: lwsync
699714 ; PPC64LE-NEXT: b .LBB54_2
700715 ; PPC64LE-NEXT: .p2align 5
715730 define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
716731 ; PPC64LE-LABEL: test55:
717732 ; PPC64LE: # %bb.0:
733 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
718734 ; PPC64LE-NEXT: lwsync
719735 ; PPC64LE-NEXT: .LBB55_1:
720736 ; PPC64LE-NEXT: lharx 6, 0, 3
737753 define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
738754 ; PPC64LE-LABEL: test56:
739755 ; PPC64LE: # %bb.0:
756 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
740757 ; PPC64LE-NEXT: lwsync
741758 ; PPC64LE-NEXT: .LBB56_1:
742759 ; PPC64LE-NEXT: lharx 6, 0, 3
759776 define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
760777 ; PPC64LE-LABEL: test57:
761778 ; PPC64LE: # %bb.0:
779 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
762780 ; PPC64LE-NEXT: sync
763781 ; PPC64LE-NEXT: .LBB57_1:
764782 ; PPC64LE-NEXT: lharx 6, 0, 3
781799 define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
782800 ; PPC64LE-LABEL: test58:
783801 ; PPC64LE: # %bb.0:
802 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
784803 ; PPC64LE-NEXT: sync
785804 ; PPC64LE-NEXT: .LBB58_1:
786805 ; PPC64LE-NEXT: lharx 6, 0, 3
803822 define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
804823 ; PPC64LE-LABEL: test59:
805824 ; PPC64LE: # %bb.0:
825 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
806826 ; PPC64LE-NEXT: sync
807827 ; PPC64LE-NEXT: .LBB59_1:
808828 ; PPC64LE-NEXT: lharx 6, 0, 3
12471267 define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
12481268 ; PPC64LE-LABEL: test80:
12491269 ; PPC64LE: # %bb.0:
1270 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
12501271 ; PPC64LE-NEXT: b .LBB80_2
12511272 ; PPC64LE-NEXT: .p2align 5
12521273 ; PPC64LE-NEXT: .LBB80_1:
12661287 define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
12671288 ; PPC64LE-LABEL: test81:
12681289 ; PPC64LE: # %bb.0:
1290 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
12691291 ; PPC64LE-NEXT: .LBB81_1:
12701292 ; PPC64LE-NEXT: lbarx 6, 0, 3
12711293 ; PPC64LE-NEXT: cmpw 4, 6
12871309 define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
12881310 ; PPC64LE-LABEL: test82:
12891311 ; PPC64LE: # %bb.0:
1312 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
12901313 ; PPC64LE-NEXT: .LBB82_1:
12911314 ; PPC64LE-NEXT: lbarx 6, 0, 3
12921315 ; PPC64LE-NEXT: cmpw 4, 6
13081331 define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
13091332 ; PPC64LE-LABEL: test83:
13101333 ; PPC64LE: # %bb.0:
1334 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
13111335 ; PPC64LE-NEXT: lwsync
13121336 ; PPC64LE-NEXT: b .LBB83_2
13131337 ; PPC64LE-NEXT: .p2align 5
13281352 define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
13291353 ; PPC64LE-LABEL: test84:
13301354 ; PPC64LE: # %bb.0:
1355 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
13311356 ; PPC64LE-NEXT: lwsync
13321357 ; PPC64LE-NEXT: b .LBB84_2
13331358 ; PPC64LE-NEXT: .p2align 5
13481373 define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
13491374 ; PPC64LE-LABEL: test85:
13501375 ; PPC64LE: # %bb.0:
1376 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
13511377 ; PPC64LE-NEXT: lwsync
13521378 ; PPC64LE-NEXT: .LBB85_1:
13531379 ; PPC64LE-NEXT: lbarx 6, 0, 3
13701396 define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
13711397 ; PPC64LE-LABEL: test86:
13721398 ; PPC64LE: # %bb.0:
1399 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
13731400 ; PPC64LE-NEXT: lwsync
13741401 ; PPC64LE-NEXT: .LBB86_1:
13751402 ; PPC64LE-NEXT: lbarx 6, 0, 3
13921419 define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
13931420 ; PPC64LE-LABEL: test87:
13941421 ; PPC64LE: # %bb.0:
1422 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
13951423 ; PPC64LE-NEXT: sync
13961424 ; PPC64LE-NEXT: .LBB87_1:
13971425 ; PPC64LE-NEXT: lbarx 6, 0, 3
14141442 define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
14151443 ; PPC64LE-LABEL: test88:
14161444 ; PPC64LE: # %bb.0:
1445 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
14171446 ; PPC64LE-NEXT: sync
14181447 ; PPC64LE-NEXT: .LBB88_1:
14191448 ; PPC64LE-NEXT: lbarx 6, 0, 3
14361465 define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
14371466 ; PPC64LE-LABEL: test89:
14381467 ; PPC64LE: # %bb.0:
1468 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
14391469 ; PPC64LE-NEXT: sync
14401470 ; PPC64LE-NEXT: .LBB89_1:
14411471 ; PPC64LE-NEXT: lbarx 6, 0, 3
14581488 define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
14591489 ; PPC64LE-LABEL: test90:
14601490 ; PPC64LE: # %bb.0:
1491 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
14611492 ; PPC64LE-NEXT: b .LBB90_2
14621493 ; PPC64LE-NEXT: .p2align 5
14631494 ; PPC64LE-NEXT: .LBB90_1:
14771508 define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
14781509 ; PPC64LE-LABEL: test91:
14791510 ; PPC64LE: # %bb.0:
1511 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
14801512 ; PPC64LE-NEXT: .LBB91_1:
14811513 ; PPC64LE-NEXT: lharx 6, 0, 3
14821514 ; PPC64LE-NEXT: cmpw 4, 6
14981530 define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
14991531 ; PPC64LE-LABEL: test92:
15001532 ; PPC64LE: # %bb.0:
1533 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
15011534 ; PPC64LE-NEXT: .LBB92_1:
15021535 ; PPC64LE-NEXT: lharx 6, 0, 3
15031536 ; PPC64LE-NEXT: cmpw 4, 6
15191552 define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
15201553 ; PPC64LE-LABEL: test93:
15211554 ; PPC64LE: # %bb.0:
1555 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
15221556 ; PPC64LE-NEXT: lwsync
15231557 ; PPC64LE-NEXT: b .LBB93_2
15241558 ; PPC64LE-NEXT: .p2align 5
15391573 define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
15401574 ; PPC64LE-LABEL: test94:
15411575 ; PPC64LE: # %bb.0:
1576 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
15421577 ; PPC64LE-NEXT: lwsync
15431578 ; PPC64LE-NEXT: b .LBB94_2
15441579 ; PPC64LE-NEXT: .p2align 5
15591594 define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
15601595 ; PPC64LE-LABEL: test95:
15611596 ; PPC64LE: # %bb.0:
1597 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
15621598 ; PPC64LE-NEXT: lwsync
15631599 ; PPC64LE-NEXT: .LBB95_1:
15641600 ; PPC64LE-NEXT: lharx 6, 0, 3
15811617 define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
15821618 ; PPC64LE-LABEL: test96:
15831619 ; PPC64LE: # %bb.0:
1620 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
15841621 ; PPC64LE-NEXT: lwsync
15851622 ; PPC64LE-NEXT: .LBB96_1:
15861623 ; PPC64LE-NEXT: lharx 6, 0, 3
16031640 define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
16041641 ; PPC64LE-LABEL: test97:
16051642 ; PPC64LE: # %bb.0:
1643 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
16061644 ; PPC64LE-NEXT: sync
16071645 ; PPC64LE-NEXT: .LBB97_1:
16081646 ; PPC64LE-NEXT: lharx 6, 0, 3
16251663 define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
16261664 ; PPC64LE-LABEL: test98:
16271665 ; PPC64LE: # %bb.0:
1666 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
16281667 ; PPC64LE-NEXT: sync
16291668 ; PPC64LE-NEXT: .LBB98_1:
16301669 ; PPC64LE-NEXT: lharx 6, 0, 3
16471686 define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
16481687 ; PPC64LE-LABEL: test99:
16491688 ; PPC64LE: # %bb.0:
1689 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
16501690 ; PPC64LE-NEXT: sync
16511691 ; PPC64LE-NEXT: .LBB99_1:
16521692 ; PPC64LE-NEXT: lharx 6, 0, 3