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[mips][FastISel] Simplify callabi.ll by using multiple check prefixes. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9635 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237119 91177308-0d34-0410-b5e6-96231b3b80d8 Vasileios Kalintiris 5 years ago
1 changed file(s) with 336 addition(s) and 459 deletion(s). Raw diff Collapse all Expand all
None ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
1 ; RUN: < %s | FileCheck %s
2 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
3 ; RUN: < %s | FileCheck %s
4 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
5 ; RUN: < %s | FileCheck %s -check-prefix=mips32r2
6 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
7 ; RUN: < %s | FileCheck %s -check-prefix=mips32
8 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
9 ; RUN: < %s | FileCheck %s -check-prefix=CHECK2
10 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
11 ; RUN: < %s | FileCheck %s -check-prefix=CHECK2
12
0 ; RUN: llc -march=mipsel -mcpu=mips32 -O0 \
1 ; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \
2 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1
3 ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \
4 ; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \
5 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2
6
7 declare void @xi(i32)
8
9 define void @cxi() {
10 ; ALL-LABEL: cxi:
11
12 ; ALL-DAG: addiu $4, $zero, 10
13 ; ALL-DAG: lw $25, %got(xi)(${{[0-9]+}})
14 ; ALL: jalr $25
15 call void @xi(i32 10)
16 ret void
17 }
18
19 declare void @xii(i32, i32)
20
21 define void @cxii() {
22 ; ALL-LABEL: cxii:
23
24 ; ALL-DAG: addiu $4, $zero, 746
25 ; ALL-DAG: addiu $5, $zero, 892
26 ; ALL-DAG: lw $25, %got(xii)(${{[0-9]+}})
27 ; ALL: jalr $25
28 call void @xii(i32 746, i32 892)
29 ret void
30 }
31
32 declare void @xiii(i32, i32, i32)
33
34 define void @cxiii() {
35 ; ALL-LABEL: cxiii:
36
37 ; ALL-DAG: addiu $4, $zero, 88
38 ; ALL-DAG: addiu $5, $zero, 44
39 ; ALL-DAG: addiu $6, $zero, 11
40 ; ALL-DAG: lw $25, %got(xiii)(${{[0-9]+}})
41 ; ALL: jalr $25
42 call void @xiii(i32 88, i32 44, i32 11)
43 ret void
44 }
45
46 declare void @xiiii(i32, i32, i32, i32)
47
48 define void @cxiiii() {
49 ; ALL-LABEL: cxiiii:
50
51 ; ALL-DAG: addiu $4, $zero, 167
52 ; ALL-DAG: addiu $5, $zero, 320
53 ; ALL-DAG: addiu $6, $zero, 97
54 ; ALL-DAG: addiu $7, $zero, 14
55 ; ALL-DAG: lw $25, %got(xiiii)(${{[0-9]+}})
56 ; ALL: jalr $25
57 call void @xiiii(i32 167, i32 320, i32 97, i32 14)
58 ret void
59 }
1360
1461 @c1 = global i8 -45, align 1
1562 @uc1 = global i8 27, align 1
1663 @s1 = global i16 -1789, align 2
1764 @us1 = global i16 1256, align 2
1865
19 ; Function Attrs: nounwind
20 define void @cxi() #0 {
21 entry:
22 ; CHECK-LABEL: cxi
23 call void @xi(i32 10)
24 ; CHECK-DAG: addiu $4, $zero, 10
25 ; CHECK-DAG: lw $25, %got(xi)(${{[0-9]+}})
26 ; CHECK: jalr $25
27
28 ret void
29 }
30
31 declare void @xi(i32) #1
32
33 ; Function Attrs: nounwind
34 define void @cxii() #0 {
35 entry:
36 ; CHECK-LABEL: cxii
37 call void @xii(i32 746, i32 892)
38 ; CHECK-DAG: addiu $4, $zero, 746
39 ; CHECK-DAG: addiu $5, $zero, 892
40 ; CHECK-DAG: lw $25, %got(xii)(${{[0-9]+}})
41 ; CHECK: jalr $25
42
43 ret void
44 }
45
46 declare void @xii(i32, i32) #1
47
48 ; Function Attrs: nounwind
49 define void @cxiii() #0 {
50 entry:
51 ; CHECK-LABEL: cxiii
52 call void @xiii(i32 88, i32 44, i32 11)
53 ; CHECK-DAG: addiu $4, $zero, 88
54 ; CHECK-DAG: addiu $5, $zero, 44
55 ; CHECK-DAG: addiu $6, $zero, 11
56 ; CHECK-DAG: lw $25, %got(xiii)(${{[0-9]+}})
57 ; CHECK: jalr $25
58 ret void
59 }
60
61 declare void @xiii(i32, i32, i32) #1
62
63 ; Function Attrs: nounwind
64 define void @cxiiii() #0 {
65 entry:
66 ; CHECK-LABEL: cxiiii
67 call void @xiiii(i32 167, i32 320, i32 97, i32 14)
68 ; CHECK-DAG: addiu $4, $zero, 167
69 ; CHECK-DAG: addiu $5, $zero, 320
70 ; CHECK-DAG: addiu $6, $zero, 97
71 ; CHECK-DAG: addiu $7, $zero, 14
72 ; CHECK-DAG: lw $25, %got(xiiii)(${{[0-9]+}})
73 ; CHECK: jalr $25
74
75 ret void
76 }
77
78 declare void @xiiii(i32, i32, i32, i32) #1
79
80 ; Function Attrs: nounwind
81 define void @cxiiiiconv() #0 {
82 entry:
83 ; CHECK-LABEL: cxiiiiconv
84 ; mips32r2-LABEL: cxiiiiconv
85 ; mips32-LABEL: cxiiiiconv
86 %0 = load i8, i8* @c1, align 1
87 %conv = sext i8 %0 to i32
88 %1 = load i8, i8* @uc1, align 1
89 %conv1 = zext i8 %1 to i32
90 %2 = load i16, i16* @s1, align 2
91 %conv2 = sext i16 %2 to i32
92 %3 = load i16, i16* @us1, align 2
93 %conv3 = zext i16 %3 to i32
66 define void @cxiiiiconv() {
67 ; ALL-LABEL: cxiiiiconv:
68
69 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
70 ; ALL-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
71 ; ALL-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
72 ; 32R1-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24
73 ; 32R1-DAG: sra $4, $[[REG_C1_1]], 24
74 ; 32R2-DAG: seb $4, $[[REG_C1]]
75 ; FIXME: andi is superfulous
76 ; ALL-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
77 ; ALL-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])
78 ; ALL-DAG: andi $5, $[[REG_UC1]], 255
79 ; ALL-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
80 ; ALL-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
81 ; 32R1-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16
82 ; 32R1-DAG: sra $6, $[[REG_S1_1]], 16
83 ; 32R2-DAG: seh $6, $[[REG_S1]]
84 ; FIXME andi is superfulous
85 ; ALL-DAG: lw $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
86 ; ALL-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]])
87 ; ALL-DAG: andi $7, $[[REG_US1]], 65535
88 ; ALL: jalr $25
89 %1 = load i8, i8* @c1, align 1
90 %conv = sext i8 %1 to i32
91 %2 = load i8, i8* @uc1, align 1
92 %conv1 = zext i8 %2 to i32
93 %3 = load i16, i16* @s1, align 2
94 %conv2 = sext i16 %3 to i32
95 %4 = load i16, i16* @us1, align 2
96 %conv3 = zext i16 %4 to i32
9497 call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3)
95 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
96 ; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
97 ; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
98 ; mips32r2-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
99 ; mips32r2-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
100 ; mips32r2-DAG seb $3, $[[REG_C1]]
101 ; mips32-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
102 ; mips32-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
103 ; mips32-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24
104 ; mips32-DAG: sra $4, $[[REG_C1_1]], 24
105 ; CHECK-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
106 ; CHECK-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])
107 ; FIXME andi is superfulous
108 ; CHECK-DAG: andi $5, $[[REG_UC1]], 255
109 ; mips32r2-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
110 ; mips32r2-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
111 ; mips32r2-DAG: seh $6, $[[REG_S1]]
112 ; mips32-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
113 ; mips32-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
114 ; mips32-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16
115 ; mips32-DAG: sra $6, $[[REG_S1_1]], 16
116 ; CHECK-DAG: lw $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
117 ; CHECK-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]])
118 ; FIXME andi is superfulous
119 ; CHECK-DAG: andi $7, $[[REG_US1]], 65535
120 ; mips32r2: jalr $25
121 ; mips32r2: jalr $25
122 ; CHECK: jalr $25
123 ret void
124 }
125
126 ; Function Attrs: nounwind
127 define void @cxf() #0 {
128 entry:
129 ; CHECK-LABEL: cxf
98 ret void
99 }
100
101 declare void @xf(float)
102
103 define void @cxf() {
104 ; ALL-LABEL: cxf:
105
106 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
107 ; ALL: lui $[[REG_FPCONST_1:[0-9]+]], 17886
108 ; ALL: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067
109 ; ALL: mtc1 $[[REG_FPCONST]], $f12
110 ; ALL: lw $25, %got(xf)($[[REG_GP]])
111 ; ALL: jalr $25
130112 call void @xf(float 0x40BBC85560000000)
131 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
132 ; CHECK: lui $[[REG_FPCONST_1:[0-9]+]], 17886
133 ; CHECK: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067
134 ; CHECK: mtc1 $[[REG_FPCONST]], $f12
135 ; CHECK: lw $25, %got(xf)($[[REG_GP]])
136 ; CHECK: jalr $25
137 ret void
138 }
139
140 declare void @xf(float) #1
141
142 ; Function Attrs: nounwind
143 define void @cxff() #0 {
144 entry:
145 ; CHECK-LABEL: cxff
113 ret void
114 }
115
116 declare void @xff(float, float)
117
118 define void @cxff() {
119 ; ALL-LABEL: cxff:
120
121 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
122 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16314
123 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349
124 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
125 ; ALL-DAG: lui $[[REG_FPCONST_2:[0-9]+]], 16593
126 ; ALL-DAG: ori $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642
127 ; ALL-DAG: mtc1 $[[REG_FPCONST_3]], $f14
128 ; ALL-DAG: lw $25, %got(xff)($[[REG_GP]])
129 ; ALL: jalr $25
146130 call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000)
147 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
148 ; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16314
149 ; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349
150 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
151 ; CHECK-DAG: lui $[[REG_FPCONST_2:[0-9]+]], 16593
152 ; CHECK-DAG: ori $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642
153 ; CHECK-DAG: mtc1 $[[REG_FPCONST_3]], $f14
154 ; CHECK: lw $25, %got(xff)($[[REG_GP]])
155 ; CHECK: jalr $25
156 ret void
157 }
158
159 declare void @xff(float, float) #1
160
161 ; Function Attrs: nounwind
162 define void @cxfi() #0 {
163 entry:
164 ; CHECK-LABEL: cxfi
131 ret void
132 }
133
134 declare void @xfi(float, i32)
135
136 define void @cxfi() {
137 ; ALL-LABEL: cxfi:
138
139 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
140 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16540
141 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554
142 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
143 ; ALL-DAG: addiu $5, $zero, 102
144 ; ALL-DAG: lw $25, %got(xfi)($[[REG_GP]])
145 ; ALL: jalr $25
165146 call void @xfi(float 0x4013906240000000, i32 102)
166 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
167 ; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16540
168 ; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554
169 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
170 ; CHECK-DAG: addiu $5, $zero, 102
171 ; CHECK: lw $25, %got(xfi)($[[REG_GP]])
172 ; CHECK: jalr $25
173
174 ret void
175 }
176
177 declare void @xfi(float, i32) #1
178
179 ; Function Attrs: nounwind
180 define void @cxfii() #0 {
181 entry:
182 ; CHECK-LABEL: cxfii
147 ret void
148 }
149
150 declare void @xfii(float, i32, i32)
151
152 define void @cxfii() {
153 ; ALL-LABEL: cxfii:
154
155 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
156 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17142
157 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240
158 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
159 ; ALL-DAG: addiu $5, $zero, 9993
160 ; ALL-DAG: addiu $6, $zero, 10922
161 ; ALL-DAG: lw $25, %got(xfii)($[[REG_GP]])
162 ; ALL: jalr $25
183163 call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922)
184 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
185 ; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17142
186 ; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240
187 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
188 ; CHECK-DAG: addiu $5, $zero, 9993
189 ; CHECK-DAG: addiu $6, $zero, 10922
190 ; CHECK: lw $25, %got(xfii)($[[REG_GP]])
191 ; CHECK: jalr $25
192 ret void
193 }
194
195 declare void @xfii(float, i32, i32) #1
196
197 ; Function Attrs: nounwind
198 define void @cxfiii() #0 {
199 entry:
200 ; CHECK-LABEL: cxfiii
164 ret void
165 }
166
167 declare void @xfiii(float, i32, i32, i32)
168
169 define void @cxfiii() {
170 ; ALL-LABEL: cxfiii:
171
172 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
173 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17120
174 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681
175 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
176 ; ALL-DAG: addiu $5, $zero, 3948
177 ; ALL-DAG: lui $[[REG_I_1:[0-9]+]], 1
178 ; ALL-DAG: ori $6, $[[REG_I_1]], 23475
179 ; ALL-DAG: lui $[[REG_I_2:[0-9]+]], 1
180 ; ALL-DAG: ori $7, $[[REG_I_2]], 45686
181 ; ALL-DAG: lw $25, %got(xfiii)($[[REG_GP]])
182 ; ALL: jalr $25
201183 call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222)
202 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
203 ; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17120
204 ; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681
205 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
206 ; CHECK-DAG: addiu $5, $zero, 3948
207 ; CHECK-DAG: lui $[[REG_I_1:[0-9]+]], 1
208 ; CHECK-DAG: ori $6, $[[REG_I_1]], 23475
209 ; CHECK-DAG: lui $[[REG_I_2:[0-9]+]], 1
210 ; CHECK-DAG: ori $7, $[[REG_I_2]], 45686
211 ; CHECK: lw $25, %got(xfiii)($[[REG_GP]])
212 ; CHECK: jalr $25
213 ret void
214 }
215
216 declare void @xfiii(float, i32, i32, i32) #1
217
218 ; Function Attrs: nounwind
219 define void @cxd() #0 {
220 entry:
221 ; mips32r2-LABEL: cxd:
222 ; mips32-LABEL: cxd:
184 ret void
185 }
186
187 declare void @xd(double)
188
189 define void @cxd() {
190 ; ALL-LABEL: cxd:
191
192 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
193 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514
194 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
195 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195
196 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
197 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12
198 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13
199 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
200 ; ALL-DAG: lw $25, %got(xd)($[[REG_GP]])
201 ; ALL: jalr $25
223202 call void @xd(double 5.994560e+02)
224 ; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
225 ; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514
226 ; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
227 ; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195
228 ; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
229 ; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12
230 ; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13
231 ; mips32-DAG: lw $25, %got(xd)($[[REG_GP]])
232 ; mips32: jalr $25
233 ; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
234 ; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514
235 ; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
236 ; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195
237 ; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
238 ; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12
239 ; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
240 ; mips32r2-DAG: lw $25, %got(xd)($[[REG_GP]])
241 ; mips32r2 : jalr $25
242 ret void
243 }
244
245 declare void @xd(double) #1
246
247 ; Function Attrs: nounwind
248 define void @cxdd() #0 {
249 ; mips32r2-LABEL: cxdd:
250 ; mips32-LABEL: cxdd:
251 entry:
203 ret void
204 }
205
206 declare void @xdd(double, double)
207
208 define void @cxdd() {
209 ; ALL-LABEL: cxdd:
210
211 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
212 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531
213 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
214 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078
215 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
216 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12
217 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13
218 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
219 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629
220 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
221 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438
222 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
223 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f14
224 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f15
225 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f14
226 ; ALL-DAG: lw $25, %got(xdd)($[[REG_GP]])
227 ; ALL: jalr $25
252228 call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917)
253 ; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
254 ; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531
255 ; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
256 ; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078
257 ; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
258 ; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12
259 ; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13
260 ; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629
261 ; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
262 ; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438
263 ; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
264 ; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f14
265 ; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f15
266 ; mips32-DAG: lw $25, %got(xdd)($[[REG_GP]])
267 ; mips32: jalr $25
268 ; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
269 ; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531
270 ; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
271 ; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078
272 ; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
273 ; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12
274 ; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
275 ; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629
276 ; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
277 ; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438
278 ; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
279 ; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f14
280 ; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f14
281 ; mips32r2-DAG: lw $25, %got(xdd)($[[REG_GP]])
282 ; mips32r2 : jalr $25
283 ret void
284 }
285
286 declare void @xdd(double, double) #1
287
288 ; Function Attrs: nounwind
289 define void @cxif() #0 {
290 entry:
291 ; CHECK-LABEL: cxif:
229 ret void
230 }
231
232 declare void @xif(i32, float)
233
234 define void @cxif() {
235 ; ALL-LABEL: cxif:
236
237 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
238 ; ALL-DAG: addiu $4, $zero, 345
239 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 17374
240 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393
241 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
242 ; ALL-DAG: mfc1 $5, $f[[REGF_3]]
243 ; ALL-DAG: lw $25, %got(xif)($[[REG_GP]])
244 ; ALL: jalr $25
292245 call void @xif(i32 345, float 0x407BCE5A20000000)
293 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
294 ; CHECK-DAG: addiu $4, $zero, 345
295 ; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17374
296 ; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393
297 ; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
298 ; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
299 ; CHECK-DAG: lw $25, %got(xif)($[[REG_GP]])
300 ; CHECK: jalr $25
301
302 ret void
303 }
304
305 declare void @xif(i32, float) #1
306
307 ; Function Attrs: nounwind
308 define void @cxiff() #0 {
309 entry:
310 ; CHECK-LABEL: cxiff:
311 ; CHECK2-LABEL: cxiff:
246 ret void
247 }
248
249 declare void @xiff(i32, float, float)
250
251 define void @cxiff() {
252 ; ALL-LABEL: cxiff:
253
254 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
255 ; ALL-DAG: addiu $4, $zero, 12239
256 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17526
257 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 55706
258 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
259 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 16543
260 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 65326
261 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
262 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]]
263 ; ALL-DAG: mfc1 $6, $f[[REGF1_3]]
264 ; ALL-DAG: lw $25, %got(xiff)($[[REG_GP]])
265 ; ALL: jalr $25
312266 call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000)
313 ; We need to do the two floating point parameters in a separate
314 ; check because we can't control the ordering of parts of the sequence
315 ;;
316 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
317 ; CHECK: addiu $4, $zero, 12239
318 ; CHECK2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
319 ; CHECK2: addiu $4, $zero, 12239
320 ; CHECK: lui $[[REGF_1:[0-9]+]], 17526
321 ; CHECK: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
322 ; CHECK: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
323 ; CHECK: mfc1 $5, $f[[REGF_3]]
324 ; CHECK2: lui $[[REGF2_1:[0-9]+]], 16543
325 ; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 65326
326 ; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
327 ; CHECK2: mfc1 $6, $f[[REGF2_3]]
328 ; CHECK: lw $25, %got(xiff)($[[REG_GP]])
329 ; CHECK2: lw $25, %got(xiff)($[[REG_GP]])
330 ; CHECK: jalr $25
331 ; CHECK2: jalr $25
332 ret void
333 }
334
335 declare void @xiff(i32, float, float) #1
336
337 ; Function Attrs: nounwind
338 define void @cxifi() #0 {
339 entry:
340 ; CHECK: cxifi:
267 ret void
268 }
269
270 declare void @xifi(i32, float, i32)
271
272 define void @cxifi() {
273 ; ALL-LABEL: cxifi:
274
275 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
276 ; ALL-DAG: addiu $4, $zero, 887
277 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 16659
278 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759
279 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
280 ; ALL-DAG: mfc1 $5, $f[[REGF_3]]
281 ; ALL-DAG: addiu $6, $zero, 888
282 ; ALL-DAG: lw $25, %got(xifi)($[[REG_GP]])
283 ; ALL: jalr $25
341284 call void @xifi(i32 887, float 0x402277CEE0000000, i32 888)
342 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
343 ; CHECK-DAG: addiu $4, $zero, 887
344 ; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 16659
345 ; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759
346 ; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
347 ; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
348 ; CHECk-DAG: addiu $6, $zero, 888
349 ; CHECK-DAG: lw $25, %got(xifi)($[[REG_GP]])
350 ; CHECK: jalr $25
351
352 ret void
353 }
354
355 declare void @xifi(i32, float, i32) #1
356
357 ; Function Attrs: nounwind
358 define void @cxifif() #0 {
359 entry:
360 ; CHECK: cxifif:
361 ; CHECK2: cxifif:
362 call void @xifif(i32 67774, float 0x408EE0FBE0000000, i32 9991, float 0x40B15C8CC0000000)
363 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
364 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
365 ; CHECK-DAG: lui $[[REGI:[0-9]+]], 1
366 ; CHECK-DAG: ori $4, $[[REGI]], 2238
367 ; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17527
368 ; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 2015
369 ; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
370 ; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
371 ; CHECk-DAG: addiu $6, $zero, 888
372 ; CHECK2: lui $[[REGF2_1:[0-9]+]], 17802
373 ; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 58470
374 ; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
375 ; CHECK2: mfc1 $7, $f[[REGF2_3]]
376 ; CHECK: lw $25, %got(xifif)($[[REG_GP]])
377 ; CHECK2: lw $25, %got(xifif)($[[REG_GP]])
378 ; CHECK2: jalr $25
379 ; CHECK: jalr $25
380
381 ret void
382 }
383
384 declare void @xifif(i32, float, i32, float) #1
385
386 ; Function Attrs: nounwind
387 define void @cxiffi() #0 {
388 entry:
389 ; CHECK-label: cxiffi:
390 ; CHECK2-label: cxiffi:
391 call void @xiffi(i32 45, float 0x3FF6666660000000, float 0x408F333340000000, i32 234)
392 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
393 ; CHECK-DAG: addiu $4, $zero, 45
394 ; CHECK2-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
395 ; CHECK2-DAG: addiu $4, $zero, 45
396 ; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 16307
397 ; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 13107
398 ; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
399 ; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
400 ; CHECK2: lui $[[REGF2_1:[0-9]+]], 17529
401 ; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 39322
402 ; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
403 ; CHECK2: mfc1 $6, $f[[REGF2_3]]
404 ; CHECK-DAG: lw $25, %got(xiffi)($[[REG_GP]])
405 ; CHECK-DAG: addiu $7, $zero, 234
406 ; CHECK2-DAG: lw $25, %got(xiffi)($[[REG_GP]])
407 ; CHECK: jalr $25
408 ; CHECK2: jalr $25
409
410 ret void
411 }
412
413 declare void @xiffi(i32, float, float, i32) #1
414
415 ; Function Attrs: nounwind
416 define void @cxifii() #0 {
417 entry:
418 ; CHECK-DAG: cxifii:
285 ret void
286 }
287
288 declare void @xifif(i32, float, i32, float)
289
290 define void @cxifif() {
291 ; ALL-LABEL: cxifif:
292
293 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
294 ; ALL-DAG: lui $[[REGI:[0-9]+]], 1
295 ; ALL-DAG: ori $4, $[[REGI]], 2238
296 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17527
297 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 2015
298 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
299 ; ALL-DAG: addiu $6, $zero, 9991
300 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17802
301 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 58470
302 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
303 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]]
304 ; ALL-DAG: mfc1 $7, $f[[REGF1_3]]
305 ; ALL-DAG: lw $25, %got(xifif)($[[REG_GP]])
306 ; ALL: jalr $25
307 call void @xifif(i32 67774, float 0x408EE0FBE0000000,
308 i32 9991, float 0x40B15C8CC0000000)
309 ret void
310 }
311
312 declare void @xiffi(i32, float, float, i32)
313
314 define void @cxiffi() {
315 ; ALL-LABEL: cxiffi:
316
317 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
318 ; ALL-DAG: addiu $4, $zero, 45
319 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 16307
320 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 13107
321 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
322 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17529
323 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 39322
324 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
325 ; ALL-DAG: addiu $7, $zero, 234
326 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]]
327 ; ALL-DAG: mfc1 $6, $f[[REGF1_3]]
328 ; ALL-DAG: lw $25, %got(xiffi)($[[REG_GP]])
329 ; ALL: jalr $25
330 call void @xiffi(i32 45, float 0x3FF6666660000000,
331 float 0x408F333340000000, i32 234)
332 ret void
333 }
334
335 declare void @xifii(i32, float, i32, i32)
336
337 define void @cxifii() {
338 ; ALL-LABEL: cxifii:
339
340 ; ALL-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
341 ; ALL-DAG: addiu $4, $zero, 12239
342 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 17526
343 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
344 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
345 ; ALL-DAG: mfc1 $5, $f[[REGF_3]]
346 ; ALL-DAG: lui $[[REGI2:[0-9]+]], 15
347 ; ALL-DAG: ori $6, $[[REGI2]], 15837
348 ; ALL-DAG: addiu $7, $zero, 1234
349 ; ALL-DAG: lw $25, %got(xifii)($[[REG_GP]])
350 ; ALL: jalr $25
419351 call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234)
420 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
421 ; CHECK-DAG: addiu $4, $zero, 12239
422 ; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17526
423 ; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
424 ; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
425 ; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
426 ; CHECK-DAG: lui $[[REGI2:[0-9]+]], 15
427 ; CHECK-DAG: ori $6, $[[REGI2]], 15837
428 ; CHECk-DAG: addiu $7, $zero, 1234
429 ; CHECK-DAG: lw $25, %got(xifii)($[[REG_GP]])
430 ; CHECK: jalr $25
431 ret void
432 }
433
434 declare void @xifii(i32, float, i32, i32) #1
435
436 ; FIXME: this function will not pass yet.
437 ; Function Attrs: nounwind
438 ; define void @cxfid() #0 {
439 ;entry:
440 ; call void @xfid(float 0x4013B851E0000000, i32 811123, double 0x40934BFF487FCB92)
441 ; ret void
442 ;}
443
444 declare void @xfid(float, i32, double) #1
445
446 ; Function Attrs: nounwind
447 define void @g() #0 {
448 entry:
449 call void @cxi()
450 call void @cxii()
451 call void @cxiii()
452 call void @cxiiii()
453 call void @cxiiiiconv()
454 call void @cxf()
455 call void @cxff()
456 call void @cxd()
457 call void @cxfi()
458 call void @cxfii()
459 call void @cxfiii()
460 call void @cxdd()
461 call void @cxif()
462 call void @cxiff()
463 call void @cxifi()
464 call void @cxifii()
465 call void @cxifif()
466 call void @cxiffi()
467 ret void
468 }
469
470
471 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
472 attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
473
474 !llvm.ident = !{!0}
475
476 !0 = !{!"clang version 3.6.0 (gitosis@dmz-portal.mips.com:clang 43992fe7b17de5553ac06d323cb80cc6723a9ae3) (gitosis@dmz-portal.mips.com:llvm.git 0834e6839eb170197c81bb02e916258d1527e312)"}
352 ret void
353 }