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MIR Serialization: Serialize the null register operands. This commit serializes the null register machine operands. It uses the '_' keyword to represent them, but the parser also allows the '%noreg' named register syntax. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10580 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240558 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Lorenz 5 years ago
5 changed file(s) with 39 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
6363 auto Range = C;
6464 while (isIdentifierChar(C.peek()))
6565 C.advance();
66 Token = MIToken(MIToken::Identifier, Range.upto(C));
66 auto Identifier = Range.upto(C);
67 Token = MIToken(Identifier == "_" ? MIToken::underscore : MIToken::Identifier,
68 Identifier);
6769 return C;
6870 }
6971
3333 // Tokens with no info.
3434 comma,
3535 equal,
36 underscore,
3637
3738 // Identifier tokens
3839 Identifier,
5758
5859 bool isError() const { return Kind == Error; }
5960
60 bool isRegister() const { return Kind == NamedRegister; }
61 bool isRegister() const {
62 return Kind == NamedRegister || Kind == underscore;
63 }
6164
6265 bool is(TokenKind K) const { return Kind == K; }
6366
173173
174174 bool MIParser::parseRegister(unsigned &Reg) {
175175 switch (Token.kind()) {
176 case MIToken::underscore:
177 Reg = 0;
178 break;
176179 case MIToken::NamedRegister: {
177180 StringRef Name = Token.stringValue().drop_front(1); // Drop the '%'
178181 if (getRegisterByName(Name, Reg))
210213
211214 bool MIParser::parseMachineOperand(MachineOperand &Dest) {
212215 switch (Token.kind()) {
216 case MIToken::underscore:
213217 case MIToken::NamedRegister:
214218 return parseRegisterOperand(Dest);
215219 case MIToken::IntegerLiteral:
244248 void MIParser::initNames2Regs() {
245249 if (!Names2Regs.empty())
246250 return;
251 // The '%noreg' register is the register 0.
252 Names2Regs.insert(std::make_pair("noreg", 0));
247253 const auto *TRI = MF.getSubtarget().getRegisterInfo();
248254 assert(TRI && "Expected target register info");
249255 for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {
143143 static void printReg(unsigned Reg, raw_ostream &OS,
144144 const TargetRegisterInfo *TRI) {
145145 // TODO: Print Stack Slots.
146 // TODO: Print no register.
147146 // TODO: Print virtual registers.
148 if (Reg < TRI->getNumRegs())
147 if (!Reg)
148 OS << '_';
149 else if (Reg < TRI->getNumRegs())
149150 OS << '%' << StringRef(TRI->getName(Reg)).lower();
150151 else
151152 llvm_unreachable("Can't print this kind of register yet");
0 # RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
1 # This test ensures that the MIR parser parses null register operands correctly.
2
3 --- |
4
5 define i32 @deref(i32* %p) {
6 entry:
7 %a = load i32, i32* %p
8 ret i32 %a
9 }
10
11 ...
12 ---
13 # CHECK: name: deref
14 name: deref
15 body:
16 - name: entry
17 instructions:
18 # CHECK: - '%eax = MOV32rm %rdi, 1, _, 0, _'
19 # CHECK-NEXT: - 'RETQ %eax'
20 - '%eax = MOV32rm %rdi, 1, _, 0, %noreg'
21 - 'RETQ %eax'
22 ...