llvm.org GIT mirror llvm / d86e30a
Remove the need to cache the subtarget in the ARM TargetRegisterInfo classes. Replace the frame pointer initialization with a static function that'll look it up via the subtarget on the MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232010 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 5 years ago
11 changed file(s) with 39 addition(s) and 44 deletion(s). Raw diff Collapse all Expand all
4444
4545 using namespace llvm;
4646
47 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti)
48 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), BasePtr(ARM::R6) {
47 ARMBaseRegisterInfo::ARMBaseRegisterInfo()
48 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {}
49
50 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
4951 if (STI.isTargetMachO()) {
5052 if (STI.isTargetDarwin() || STI.isThumb1Only())
51 FramePtr = ARM::R7;
53 return ARM::R7;
5254 else
53 FramePtr = ARM::R11;
55 return ARM::R11;
5456 } else if (STI.isTargetWindows())
55 FramePtr = ARM::R11;
57 return ARM::R11;
5658 else // ARM EABI
57 FramePtr = STI.isThumb() ? ARM::R7 : ARM::R11;
59 return STI.isThumb() ? ARM::R7 : ARM::R11;
5860 }
5961
6062 const MCPhysReg*
6163 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
64 const ARMSubtarget &STI = MF->getSubtarget();
6265 const MCPhysReg *RegList =
6366 STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
6467
8992 const uint32_t *
9093 ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
9194 CallingConv::ID CC) const {
95 const ARMSubtarget &STI = MF.getSubtarget();
9296 if (CC == CallingConv::GHC)
9397 // This is academic becase all GHC calls are (supposed to be) tail calls
9498 return CSR_NoRegs_RegMask;
103107 const uint32_t *
104108 ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
105109 CallingConv::ID CC) const {
110 const ARMSubtarget &STI = MF.getSubtarget();
106111 // This should return a register mask that is the same as that returned by
107112 // getCallPreservedMask but that additionally preserves the register used for
108113 // the first i32 argument (which must also be the register used to return a
120125
121126 BitVector ARMBaseRegisterInfo::
122127 getReservedRegs(const MachineFunction &MF) const {
123 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
128 const ARMSubtarget &STI = MF.getSubtarget();
129 const TargetFrameLowering *TFI = STI.getFrameLowering();
124130
125131 // FIXME: avoid re-calculating this every time.
126132 BitVector Reserved(getNumRegs());
129135 Reserved.set(ARM::FPSCR);
130136 Reserved.set(ARM::APSR_NZCV);
131137 if (TFI->hasFP(MF))
132 Reserved.set(FramePtr);
138 Reserved.set(getFramePointerReg(STI));
133139 if (hasBasePointer(MF))
134140 Reserved.set(BasePtr);
135141 // Some targets reserve R9.
186192 unsigned
187193 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
188194 MachineFunction &MF) const {
189 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
195 const ARMSubtarget &STI = MF.getSubtarget();
196 const TargetFrameLowering *TFI = STI.getFrameLowering();
190197
191198 switch (RC->getID()) {
192199 default:
326333 return false;
327334 // Stack realignment requires a frame pointer. If we already started
328335 // register allocation with frame pointer elimination, it is too late now.
329 if (!MRI->canReserveReg(FramePtr))
336 if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget())))
330337 return false;
331338 // We may also need a base pointer if there are dynamic allocas or stack
332339 // pointer adjustments around calls.
360367
361368 unsigned
362369 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
363 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
370 const ARMSubtarget &STI = MF.getSubtarget();
371 const TargetFrameLowering *TFI = STI.getFrameLowering();
364372
365373 if (TFI->hasFP(MF))
366 return FramePtr;
374 return getFramePointerReg(STI);
367375 return ARM::SP;
368376 }
369377
8181
8282 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
8383 protected:
84 const ARMSubtarget &STI;
85
86 /// FramePtr - ARM physical register used as frame ptr.
87 unsigned FramePtr;
88
8984 /// BasePtr - ARM physical register used as a base ptr in complex stack
9085 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
9186 /// variable size stack objects.
9287 unsigned BasePtr;
9388
9489 // Can be only subclassed.
95 explicit ARMBaseRegisterInfo(const ARMSubtarget &STI);
90 explicit ARMBaseRegisterInfo();
9691
9792 // Return the opcode that implements 'Op', or 0 if no opcode
9893 unsigned getOpcode(int Op) const;
2929 using namespace llvm;
3030
3131 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
32 : ARMBaseInstrInfo(STI), RI(STI) {
33 }
32 : ARMBaseInstrInfo(STI), RI() {}
3433
3534 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3635 void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
1515
1616 void ARMRegisterInfo::anchor() { }
1717
18 ARMRegisterInfo::ARMRegisterInfo(const ARMSubtarget &sti)
19 : ARMBaseRegisterInfo(sti) {
20 }
18 ARMRegisterInfo::ARMRegisterInfo() : ARMBaseRegisterInfo() {}
2222 struct ARMRegisterInfo : public ARMBaseRegisterInfo {
2323 virtual void anchor();
2424 public:
25 ARMRegisterInfo(const ARMSubtarget &STI);
25 ARMRegisterInfo();
2626 };
2727
2828 } // end namespace llvm
2121 using namespace llvm;
2222
2323 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
24 : ARMBaseInstrInfo(STI), RI(STI) {
25 }
24 : ARMBaseInstrInfo(STI), RI() {}
2625
2726 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
2827 void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3737
3838 using namespace llvm;
3939
40 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMSubtarget &sti)
41 : ARMBaseRegisterInfo(sti) {
42 }
40 Thumb1RegisterInfo::Thumb1RegisterInfo() : ARMBaseRegisterInfo() {}
4341
4442 const TargetRegisterClass *
4543 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
5755
5856 /// emitLoadConstPool - Emits a load from constpool to materialize the
5957 /// specified immediate.
60 void
61 Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator &MBBI,
63 DebugLoc dl,
64 unsigned DestReg, unsigned SubIdx,
65 int Val,
66 ARMCC::CondCodes Pred, unsigned PredReg,
67 unsigned MIFlags) const {
58 void Thumb1RegisterInfo::emitLoadConstPool(
59 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl,
60 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred,
61 unsigned PredReg, unsigned MIFlags) const {
6862 assert((isARMLowRegister(DestReg) ||
6963 isVirtualRegister(DestReg)) &&
7064 "Thumb1 does not have ldr to high register");
7165
7266 MachineFunction &MF = *MBB.getParent();
67 const ARMSubtarget &STI = MF.getSubtarget();
7368 const TargetInstrInfo &TII = *STI.getInstrInfo();
7469 MachineConstantPool *ConstantPool = MF.getConstantPool();
7570 const Constant *C = ConstantInt::get(
387382
388383 void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
389384 int64_t Offset) const {
385 const MachineFunction &MF = *MI.getParent()->getParent();
386 const ARMSubtarget &STI = MF.getSubtarget();
390387 const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
391388 int Off = Offset; // ARM doesn't need the general 64-bit offsets
392389 unsigned i = 0;
413410 // off the frame pointer (if, for example, there are alloca() calls in
414411 // the function, the offset will be negative. Use R12 instead since that's
415412 // a call clobbered register that we know won't be used in Thumb1 mode.
413 const ARMSubtarget &STI = MBB.getParent()->getSubtarget();
416414 const TargetInstrInfo &TII = *STI.getInstrInfo();
417415 DebugLoc DL;
418416 AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
459457 MachineInstr &MI = *II;
460458 MachineBasicBlock &MBB = *MI.getParent();
461459 MachineFunction &MF = *MBB.getParent();
460 const ARMSubtarget &STI = MF.getSubtarget();
462461 const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
463462 ARMFunctionInfo *AFI = MF.getInfo();
464463 DebugLoc dl = MI.getDebugLoc();
2323
2424 struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
2525 public:
26 Thumb1RegisterInfo(const ARMSubtarget &STI);
26 Thumb1RegisterInfo();
2727
2828 const TargetRegisterClass *
2929 getLargestLegalSuperClass(const TargetRegisterClass *RC,
2929 cl::init(false));
3030
3131 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
32 : ARMBaseInstrInfo(STI), RI(STI) {
33 }
32 : ARMBaseInstrInfo(STI), RI() {}
3433
3534 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3635 void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
2424 #include "llvm/Target/TargetMachine.h"
2525 using namespace llvm;
2626
27 Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMSubtarget &sti)
28 : ARMBaseRegisterInfo(sti) {
29 }
27 Thumb2RegisterInfo::Thumb2RegisterInfo() : ARMBaseRegisterInfo() {}
3028
3129 /// emitLoadConstPool - Emits a load from constpool to materialize the
3230 /// specified immediate.
2222
2323 struct Thumb2RegisterInfo : public ARMBaseRegisterInfo {
2424 public:
25 Thumb2RegisterInfo(const ARMSubtarget &STI);
25 Thumb2RegisterInfo();
2626
2727 /// emitLoadConstPool - Emits a load from constpool to materialize the
2828 /// specified immediate.