llvm.org GIT mirror llvm / d7ea7d5
Use a SparseSet instead of a BitVector for UsedInInstr in RAFast. This is just as fast, and it makes it possible to avoid leaking the UsedPhysRegs BitVector implementation through MachineRegisterInfo::addPhysRegsUsed(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166083 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
2 changed file(s) with 30 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
375375 /// setPhysRegUsed - Mark the specified register used in this function.
376376 /// This should only be called during and after register allocation.
377377 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); }
378
379 /// addPhysRegsUsed - Mark the specified registers used in this function.
380 /// This should only be called during and after register allocation.
381 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; }
382378
383379 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
384380 /// This corresponds to the bit mask attached to register mask operands.
112112 // PhysRegState - One of the RegState enums, or a virtreg.
113113 std::vector PhysRegState;
114114
115 // UsedInInstr - BitVector of physregs that are used in the current
116 // instruction, and so cannot be allocated.
117 BitVector UsedInInstr;
115 typedef SparseSet UsedInInstrSet;
116
117 // UsedInInstr - Set of physregs that are used in the current instruction,
118 // and so cannot be allocated.
119 UsedInInstrSet UsedInInstr;
118120
119121 // SkippedInstrs - Descriptors of instructions whose clobber list was
120122 // ignored because all registers were spilled. It is still necessary to
339341 PhysRegState[PhysReg] = regFree;
340342 // Fall through
341343 case regFree:
342 UsedInInstr.set(PhysReg);
344 UsedInInstr.insert(PhysReg);
343345 MO.setIsKill();
344346 return;
345347 default:
359361 "Instruction is not using a subregister of a reserved register");
360362 // Leave the superregister in the working set.
361363 PhysRegState[Alias] = regFree;
362 UsedInInstr.set(Alias);
364 UsedInInstr.insert(Alias);
363365 MO.getParent()->addRegisterKilled(Alias, TRI, true);
364366 return;
365367 case regFree:
366368 if (TRI->isSuperRegister(PhysReg, Alias)) {
367369 // Leave the superregister in the working set.
368 UsedInInstr.set(Alias);
370 UsedInInstr.insert(Alias);
369371 MO.getParent()->addRegisterKilled(Alias, TRI, true);
370372 return;
371373 }
379381
380382 // All aliases are disabled, bring register into working set.
381383 PhysRegState[PhysReg] = regFree;
382 UsedInInstr.set(PhysReg);
384 UsedInInstr.insert(PhysReg);
383385 MO.setIsKill();
384386 }
385387
388390 /// reserved instead of allocated.
389391 void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
390392 RegState NewState) {
391 UsedInInstr.set(PhysReg);
393 UsedInInstr.insert(PhysReg);
392394 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
393395 case regDisabled:
394396 break;
428430 // can be allocated directly.
429431 // Returns spillImpossible when PhysReg or an alias can't be spilled.
430432 unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
431 if (UsedInInstr.test(PhysReg)) {
433 if (UsedInInstr.count(PhysReg)) {
432434 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n");
433435 return spillImpossible;
434436 }
453455 unsigned Cost = 0;
454456 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
455457 unsigned Alias = *AI;
456 if (UsedInInstr.test(Alias))
458 if (UsedInInstr.count(Alias))
457459 return spillImpossible;
458460 switch (unsigned VirtReg = PhysRegState[Alias]) {
459461 case regDisabled:
529531 // First try to find a completely free register.
530532 for (ArrayRef::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
531533 unsigned PhysReg = *I;
532 if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg)) {
534 if (PhysRegState[PhysReg] == regFree && !UsedInInstr.count(PhysReg)) {
533535 assignVirtToPhysReg(*LRI, PhysReg);
534536 return LRI;
535537 }
595597 LRI->LastUse = MI;
596598 LRI->LastOpNum = OpNum;
597599 LRI->Dirty = true;
598 UsedInInstr.set(LRI->PhysReg);
600 UsedInInstr.insert(LRI->PhysReg);
599601 return LRI;
600602 }
601603
645647 assert(LRI->PhysReg && "Register not assigned");
646648 LRI->LastUse = MI;
647649 LRI->LastOpNum = OpNum;
648 UsedInInstr.set(LRI->PhysReg);
650 UsedInInstr.insert(LRI->PhysReg);
649651 return LRI;
650652 }
651653
707709 unsigned Reg = MO.getReg();
708710 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
709711 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
710 UsedInInstr.set(*AI);
712 UsedInInstr.insert(*AI);
711713 if (ThroughRegs.count(PhysRegState[*AI]))
712714 definePhysReg(MI, *AI, regFree);
713715 }
755757 }
756758
757759 // Restore UsedInInstr to a state usable for allocating normal virtual uses.
758 UsedInInstr.reset();
760 UsedInInstr.clear();
759761 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
760762 MachineOperand &MO = MI->getOperand(i);
761763 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
763765 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
764766 DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI)
765767 << " as used in instr\n");
766 UsedInInstr.set(Reg);
768 UsedInInstr.insert(Reg);
767769 }
768770
769771 // Also mark PartialDefs as used to avoid reallocation.
770772 for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
771 UsedInInstr.set(PartialDefs[i]);
773 UsedInInstr.insert(PartialDefs[i]);
772774 }
773775
774776 /// addRetOperand - ensure that a return instruction has an operand for each
941943 }
942944
943945 // Track registers used by instruction.
944 UsedInInstr.reset();
946 UsedInInstr.clear();
945947
946948 // First scan.
947949 // Mark physreg uses and early clobbers as used.
10151017 }
10161018 }
10171019
1018 MRI->addPhysRegsUsed(UsedInInstr);
1020 for (UsedInInstrSet::iterator
1021 I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I)
1022 MRI->setPhysRegUsed(*I);
10191023
10201024 // Track registers defined by instruction - early clobbers and tied uses at
10211025 // this point.
1022 UsedInInstr.reset();
1026 UsedInInstr.clear();
10231027 if (hasEarlyClobbers) {
10241028 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
10251029 MachineOperand &MO = MI->getOperand(i);
10291033 // Look for physreg defs and tied uses.
10301034 if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
10311035 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
1032 UsedInInstr.set(*AI);
1036 UsedInInstr.insert(*AI);
10331037 }
10341038 }
10351039
10791083 killVirtReg(VirtDead[i]);
10801084 VirtDead.clear();
10811085
1082 MRI->addPhysRegsUsed(UsedInInstr);
1086 for (UsedInInstrSet::iterator
1087 I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I)
1088 MRI->setPhysRegUsed(*I);
10831089
10841090 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
10851091 DEBUG(dbgs() << "-- coalescing: " << *MI);
11171123 TII = TM->getInstrInfo();
11181124 MRI->freezeReservedRegs(Fn);
11191125 RegClassInfo.runOnMachineFunction(Fn);
1120 UsedInInstr.resize(TRI->getNumRegs());
1126 UsedInInstr.clear();
1127 UsedInInstr.setUniverse(TRI->getNumRegs());
11211128
11221129 assert(!MRI->isSSA() && "regalloc requires leaving SSA");
11231130