llvm.org GIT mirror llvm / d78ebe1
Remove a check from ARM shifted operand isel helper methods, which were blocking merging an lsl #2 that has multiple uses on A9. This shift is free, so there is no problem merging it in multiple places. Other unprofitable shifts will not be merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8 Cameron Zwarich 8 years ago
2 changed file(s) with 4 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
516516 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
517517 -0x1000+1, 0x1000, RHSC)) // 12 bits.
518518 return false;
519 }
520
521 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
522 // Compute R +/- (R << N) and reuse it.
523 return false;
524519 }
525520
526521 // Otherwise this is R +/- [possibly shifted] R.
12831278 return false;
12841279 else if (RHSC < 0 && RHSC >= -255) // 8 bits
12851280 return false;
1286 }
1287
1288 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1289 // Compute R + (R << [1,2,3]) and reuse it.
1290 return false;
12911281 }
12921282
12931283 // Look for (R + R) or (R + (R << [1,2,3])).
5353 define fastcc void @test4(i16 %addr) nounwind {
5454 entry:
5555 ; A8: test4:
56 ; A8: ldr r2, [r0, r1, lsl #2]
57 ; A8: str r2, [r0, r1, lsl #2]
56 ; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
57 ; A8: str [[REG]], [r0, r1, lsl #2]
5858
5959 ; A9: test4:
60 ; A9: add r0, r0, r{{[0-9]+}}, lsl #2
61 ; A9: ldr r1, [r0]
62 ; A9: str r1, [r0]
60 ; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
61 ; A9: str [[REG]], [r0, r1, lsl #2]
6362 %0 = tail call i8* (...)* @malloc(i32 undef) nounwind
6463 %1 = bitcast i8* %0 to i32*
6564 %2 = sext i16 %addr to i32