llvm.org GIT mirror llvm / d74ea77
Teach FastISel to deal with instructions that have two immediate operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130033 91177308-0d34-0410-b5e6-96231b3b80d8 Owen Anderson 9 years ago
2 changed file(s) with 33 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
287287 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
288288 const TargetRegisterClass *RC,
289289 uint64_t Imm);
290
290
291 /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands.
292 unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
293 const TargetRegisterClass *RC,
294 uint64_t Imm1, uint64_t Imm2);
295
291296 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
292297 /// from a specified index of a superregister to a specified type.
293298 unsigned FastEmitInst_extractsubreg(MVT RetVT,
337337 if (Op1 == 0) return false;
338338
339339 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
340
340
341341 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
342342 Op1IsKill, CI->getZExtValue(),
343343 VT.getSimpleVT());
344344 if (ResultReg == 0) return false;
345
345
346346 // We successfully emitted code for the given LLVM Instruction.
347347 UpdateValueMap(I, ResultReg);
348348 return true;
349349 }
350
351
350
351
352352 unsigned Op0 = getRegForValue(I->getOperand(0));
353353 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
354354 return false;
358358 // Check if the second operand is a constant and handle it appropriately.
359359 if (ConstantInt *CI = dyn_cast(I->getOperand(1))) {
360360 uint64_t Imm = CI->getZExtValue();
361
361
362362 // Transform "sdiv exact X, 8" -> "sra X, 3".
363363 if (ISDOpcode == ISD::SDIV && isa(I) &&
364364 cast(I)->isExact() &&
366366 Imm = Log2_64(Imm);
367367 ISDOpcode = ISD::SRA;
368368 }
369
369
370370 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
371371 Op0IsKill, Imm, VT.getSimpleVT());
372372 if (ResultReg == 0) return false;
373
373
374374 // We successfully emitted code for the given LLVM Instruction.
375375 UpdateValueMap(I, ResultReg);
376376 return true;
552552 EVT VT = TLI.getValueType(I->getType());
553553 if (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)!=TargetLowering::Expand)
554554 break;
555
555
556556 assert(FuncInfo.MBB->isLandingPad() &&
557557 "Call to eh.exception not in landing pad!");
558558 unsigned Reg = TLI.getExceptionAddressRegister();
994994 Opcode = ISD::SRL;
995995 Imm = Log2_64(Imm);
996996 }
997
997
998998 // Horrible hack (to be removed), check to make sure shift amounts are
999999 // in-range.
10001000 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
10011001 Imm >= VT.getSizeInBits())
10021002 return 0;
1003
1003
10041004 // First check if immediate type is legal. If not, we can't use the ri form.
10051005 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
10061006 if (ResultReg != 0)
12121212 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
12131213 else {
12141214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm);
1215 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1216 ResultReg).addReg(II.ImplicitDefs[0]);
1217 }
1218 return ResultReg;
1219 }
1220
1221 unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
1222 const TargetRegisterClass *RC,
1223 uint64_t Imm1, uint64_t Imm2) {
1224 unsigned ResultReg = createResultReg(RC);
1225 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1226
1227 if (II.getNumDefs() >= 1)
1228 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1229 .addImm(Imm1).addImm(Imm2);
1230 else {
1231 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm1).addImm(Imm2);
12151232 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
12161233 ResultReg).addReg(II.ImplicitDefs[0]);
12171234 }