llvm.org GIT mirror llvm / d735b80
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 11 years ago
71 changed file(s) with 539 addition(s) and 531 deletion(s). Raw diff Collapse all Expand all
5656 // crit_mbb.
5757 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
5858 MachineOperand & mo = mii->getOperand(i);
59 if (mo.isMachineBasicBlock() &&
60 mo.getMBB() == dst) {
59 if (mo.isMBB() && mo.getMBB() == dst) {
6160 found_branch = true;
6261 mo.setMBB(crit_mbb);
6362 }
8382 std::vector toRemove;
8483 unsigned reg = 0;
8584 for (unsigned u = 0; u != mii->getNumOperands(); ++u)
86 if (mii->getOperand(u).isMachineBasicBlock() &&
85 if (mii->getOperand(u).isMBB() &&
8786 mii->getOperand(u).getMBB() == src) {
8887 reg = mii->getOperand(u-1).getReg();
8988 toRemove.push_back(u-1);
202202 bool Removed = false;
203203 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
204204 MachineOperand &MO = MI->getOperand(i);
205 if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) {
205 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
206206 MO.setIsKill(false);
207207 Removed = true;
208208 break;
237237 bool Removed = false;
238238 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
239239 MachineOperand &MO = MI->getOperand(i);
240 if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) {
240 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
241241 MO.setIsDead(false);
242242 Removed = true;
243243 break;
5151 {}
5252
5353 // Accessors
54 bool isRegister() const { return IsRegister; }
55 unsigned getRegister() const { return Register; }
54 bool isReg() const { return IsRegister; }
55 unsigned getReg() const { return Register; }
5656 int getOffset() const { return Offset; }
5757 void setIsRegister(bool Is) { IsRegister = Is; }
5858 void setRegister(unsigned R) { Register = R; }
124124 void print(std::ostream &os, const TargetMachine *TM = 0) const;
125125 void print(raw_ostream &os, const TargetMachine *TM = 0) const;
126126
127 /// Accessors that tell you what kind of MachineOperand you're looking at.
128 ///
129 bool isRegister() const { return OpKind == MO_Register; }
130 bool isImmediate() const { return OpKind == MO_Immediate; }
131 bool isFPImmediate() const { return OpKind == MO_FPImmediate; }
132 bool isMachineBasicBlock() const { return OpKind == MO_MachineBasicBlock; }
133 bool isFrameIndex() const { return OpKind == MO_FrameIndex; }
134 bool isConstantPoolIndex() const { return OpKind == MO_ConstantPoolIndex; }
135 bool isJumpTableIndex() const { return OpKind == MO_JumpTableIndex; }
136 bool isGlobalAddress() const { return OpKind == MO_GlobalAddress; }
137 bool isExternalSymbol() const { return OpKind == MO_ExternalSymbol; }
127 //===--------------------------------------------------------------------===//
128 // Accessors that tell you what kind of MachineOperand you're looking at.
129 //===--------------------------------------------------------------------===//
130
131 /// isReg - Tests if this is a MO_Register operand.
132 bool isReg() const { return OpKind == MO_Register; }
133 /// isImm - Tests if this is a MO_Immediate operand.
134 bool isImm() const { return OpKind == MO_Immediate; }
135 /// isFPImm - Tests if this is a MO_FPImmediate operand.
136 bool isFPImm() const { return OpKind == MO_FPImmediate; }
137 /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
138 bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
139 /// isFI - Tests if this is a MO_FrameIndex operand.
140 bool isFI() const { return OpKind == MO_FrameIndex; }
141 /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
142 bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
143 /// isJTI - Tests if this is a MO_JumpTableIndex operand.
144 bool isJTI() const { return OpKind == MO_JumpTableIndex; }
145 /// isGlobal - Tests if this is a MO_GlobalAddress operand.
146 bool isGlobal() const { return OpKind == MO_GlobalAddress; }
147 /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
148 bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
138149
139150 //===--------------------------------------------------------------------===//
140151 // Accessors for Register Operands
142153
143154 /// getReg - Returns the register number.
144155 unsigned getReg() const {
145 assert(isRegister() && "This is not a register operand!");
156 assert(isReg() && "This is not a register operand!");
146157 return Contents.Reg.RegNo;
147158 }
148159
149160 unsigned getSubReg() const {
150 assert(isRegister() && "Wrong MachineOperand accessor");
161 assert(isReg() && "Wrong MachineOperand accessor");
151162 return (unsigned)SubReg;
152163 }
153164
154165 bool isUse() const {
155 assert(isRegister() && "Wrong MachineOperand accessor");
166 assert(isReg() && "Wrong MachineOperand accessor");
156167 return !IsDef;
157168 }
158169
159170 bool isDef() const {
160 assert(isRegister() && "Wrong MachineOperand accessor");
171 assert(isReg() && "Wrong MachineOperand accessor");
161172 return IsDef;
162173 }
163174
164175 bool isImplicit() const {
165 assert(isRegister() && "Wrong MachineOperand accessor");
176 assert(isReg() && "Wrong MachineOperand accessor");
166177 return IsImp;
167178 }
168179
169180 bool isDead() const {
170 assert(isRegister() && "Wrong MachineOperand accessor");
181 assert(isReg() && "Wrong MachineOperand accessor");
171182 return IsDead;
172183 }
173184
174185 bool isKill() const {
175 assert(isRegister() && "Wrong MachineOperand accessor");
186 assert(isReg() && "Wrong MachineOperand accessor");
176187 return IsKill;
177188 }
178189
179190 bool isEarlyClobber() const {
180 assert(isRegister() && "Wrong MachineOperand accessor");
191 assert(isReg() && "Wrong MachineOperand accessor");
181192 return IsEarlyClobber;
182193 }
183194
184195 /// getNextOperandForReg - Return the next MachineOperand in the function that
185196 /// uses or defines this register.
186197 MachineOperand *getNextOperandForReg() const {
187 assert(isRegister() && "This is not a register operand!");
198 assert(isReg() && "This is not a register operand!");
188199 return Contents.Reg.Next;
189200 }
190201
197208 void setReg(unsigned Reg);
198209
199210 void setSubReg(unsigned subReg) {
200 assert(isRegister() && "Wrong MachineOperand accessor");
211 assert(isReg() && "Wrong MachineOperand accessor");
201212 SubReg = (unsigned char)subReg;
202213 }
203214
204215 void setIsUse(bool Val = true) {
205 assert(isRegister() && "Wrong MachineOperand accessor");
216 assert(isReg() && "Wrong MachineOperand accessor");
206217 IsDef = !Val;
207218 }
208219
209220 void setIsDef(bool Val = true) {
210 assert(isRegister() && "Wrong MachineOperand accessor");
221 assert(isReg() && "Wrong MachineOperand accessor");
211222 IsDef = Val;
212223 }
213224
214225 void setImplicit(bool Val = true) {
215 assert(isRegister() && "Wrong MachineOperand accessor");
226 assert(isReg() && "Wrong MachineOperand accessor");
216227 IsImp = Val;
217228 }
218229
219230 void setIsKill(bool Val = true) {
220 assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
231 assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
221232 IsKill = Val;
222233 }
223234
224235 void setIsDead(bool Val = true) {
225 assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
236 assert(isReg() && IsDef && "Wrong MachineOperand accessor");
226237 IsDead = Val;
227238 }
228239
229240 void setIsEarlyClobber(bool Val = true) {
230 assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
241 assert(isReg() && IsDef && "Wrong MachineOperand accessor");
231242 IsEarlyClobber = Val;
232243 }
233244
236247 //===--------------------------------------------------------------------===//
237248
238249 int64_t getImm() const {
239 assert(isImmediate() && "Wrong MachineOperand accessor");
250 assert(isImm() && "Wrong MachineOperand accessor");
240251 return Contents.ImmVal;
241252 }
242253
243254 const ConstantFP *getFPImm() const {
244 assert(isFPImmediate() && "Wrong MachineOperand accessor");
255 assert(isFPImm() && "Wrong MachineOperand accessor");
245256 return Contents.CFP;
246257 }
247258
248259 MachineBasicBlock *getMBB() const {
249 assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
260 assert(isMBB() && "Wrong MachineOperand accessor");
250261 return Contents.MBB;
251262 }
252263
253264 int getIndex() const {
254 assert((isFrameIndex() || isConstantPoolIndex() || isJumpTableIndex()) &&
265 assert((isFI() || isCPI() || isJTI()) &&
255266 "Wrong MachineOperand accessor");
256267 return Contents.OffsetedInfo.Val.Index;
257268 }
258269
259270 GlobalValue *getGlobal() const {
260 assert(isGlobalAddress() && "Wrong MachineOperand accessor");
271 assert(isGlobal() && "Wrong MachineOperand accessor");
261272 return Contents.OffsetedInfo.Val.GV;
262273 }
263274
264275 int getOffset() const {
265 assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
276 assert((isGlobal() || isSymbol() || isCPI()) &&
266277 "Wrong MachineOperand accessor");
267278 return Contents.OffsetedInfo.Offset;
268279 }
269280
270281 const char *getSymbolName() const {
271 assert(isExternalSymbol() && "Wrong MachineOperand accessor");
282 assert(isSymbol() && "Wrong MachineOperand accessor");
272283 return Contents.OffsetedInfo.Val.SymbolName;
273284 }
274285
277288 //===--------------------------------------------------------------------===//
278289
279290 void setImm(int64_t immVal) {
280 assert(isImmediate() && "Wrong MachineOperand mutator");
291 assert(isImm() && "Wrong MachineOperand mutator");
281292 Contents.ImmVal = immVal;
282293 }
283294
284295 void setOffset(int Offset) {
285 assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
296 assert((isGlobal() || isSymbol() || isCPI()) &&
286297 "Wrong MachineOperand accessor");
287298 Contents.OffsetedInfo.Offset = Offset;
288299 }
289300
290301 void setIndex(int Idx) {
291 assert((isFrameIndex() || isConstantPoolIndex() || isJumpTableIndex()) &&
302 assert((isFI() || isCPI() || isJTI()) &&
292303 "Wrong MachineOperand accessor");
293304 Contents.OffsetedInfo.Val.Index = Idx;
294305 }
295306
296307 void setMBB(MachineBasicBlock *MBB) {
297 assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
308 assert(isMBB() && "Wrong MachineOperand accessor");
298309 Contents.MBB = MBB;
299310 }
300311
406417 /// or false if not. This can only be called for register operands that are
407418 /// part of a machine instruction.
408419 bool isOnRegUseList() const {
409 assert(isRegister() && "Can only add reg operand to use lists");
420 assert(isReg() && "Can only add reg operand to use lists");
410421 return Contents.Reg.Prev != 0;
411422 }
412423
11781178
11791179 // Count the number of register definitions.
11801180 unsigned NumDefs = 0;
1181 for (; MI->getOperand(NumDefs).isRegister() && MI->getOperand(NumDefs).isDef();
1181 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
11821182 ++NumDefs)
11831183 assert(NumDefs != NumOperands-1 && "No asm string?");
11841184
1185 assert(MI->getOperand(NumDefs).isExternalSymbol() && "No asm string?");
1185 assert(MI->getOperand(NumDefs).isSymbol() && "No asm string?");
11861186
11871187 // Disassemble the AsmStr, printing out the literal pieces, the operands, etc.
11881188 const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
10491049 }
10501050
10511051 // If advancing cfa.
1052 if (Dst.isRegister() && Dst.getRegister() == MachineLocation::VirtualFP) {
1053 if (!Src.isRegister()) {
1054 if (Src.getRegister() == MachineLocation::VirtualFP) {
1052 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
1053 if (!Src.isReg()) {
1054 if (Src.getReg() == MachineLocation::VirtualFP) {
10551055 Asm->EmitInt8(DW_CFA_def_cfa_offset);
10561056 Asm->EOL("DW_CFA_def_cfa_offset");
10571057 } else {
10581058 Asm->EmitInt8(DW_CFA_def_cfa);
10591059 Asm->EOL("DW_CFA_def_cfa");
1060 Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister(), isEH));
1060 Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getReg(), isEH));
10611061 Asm->EOL("Register");
10621062 }
10631063
10681068 } else {
10691069 assert(0 && "Machine move no supported yet.");
10701070 }
1071 } else if (Src.isRegister() &&
1072 Src.getRegister() == MachineLocation::VirtualFP) {
1073 if (Dst.isRegister()) {
1071 } else if (Src.isReg() &&
1072 Src.getReg() == MachineLocation::VirtualFP) {
1073 if (Dst.isReg()) {
10741074 Asm->EmitInt8(DW_CFA_def_cfa_register);
10751075 Asm->EOL("DW_CFA_def_cfa_register");
1076 Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister(), isEH));
1076 Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), isEH));
10771077 Asm->EOL("Register");
10781078 } else {
10791079 assert(0 && "Machine move no supported yet.");
10801080 }
10811081 } else {
1082 unsigned Reg = RI->getDwarfRegNum(Src.getRegister(), isEH);
1082 unsigned Reg = RI->getDwarfRegNum(Src.getReg(), isEH);
10831083 int Offset = Dst.getOffset() / stackGrowth;
10841084
10851085 if (Offset < 0) {
14081408 /// provided.
14091409 void AddAddress(DIE *Die, unsigned Attribute,
14101410 const MachineLocation &Location) {
1411 unsigned Reg = RI->getDwarfRegNum(Location.getRegister(), false);
1411 unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false);
14121412 DIEBlock *Block = new DIEBlock();
14131413
1414 if (Location.isRegister()) {
1414 if (Location.isReg()) {
14151415 if (Reg < 32) {
14161416 AddUInt(Block, 0, DW_FORM_data1, DW_OP_reg0 + Reg);
14171417 } else {
160160 // See if it uses any of the implicitly defined registers.
161161 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
162162 MachineOperand &MO = I->getOperand(i);
163 if (!MO.isRegister() || !MO.isUse())
163 if (!MO.isReg() || !MO.isUse())
164164 continue;
165165 unsigned Reg = MO.getReg();
166166 if (ImpDefRegs.count(Reg))
234234 I != E; ++I)
235235 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
236236 MachineOperand &Op = I->getOperand(op);
237 if (!Op.isJumpTableIndex()) continue;
237 if (!Op.isJTI()) continue;
238238 unsigned NewIdx = JTMapping[Op.getIndex()];
239239 Op.setIndex(NewIdx);
240240
5757 // Examine each operand.
5858 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5959 const MachineOperand &MO = MI->getOperand(i);
60 if (MO.isRegister() && MO.isDef()) {
60 if (MO.isReg() && MO.isDef()) {
6161 unsigned Reg = MO.getReg();
6262 if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
6363 LivePhysRegs[Reg] : !MRI->use_empty(Reg)) {
121121 // Record the physreg defs.
122122 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
123123 const MachineOperand &MO = MI->getOperand(i);
124 if (MO.isRegister() && MO.isDef()) {
124 if (MO.isReg() && MO.isDef()) {
125125 unsigned Reg = MO.getReg();
126126 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
127127 LivePhysRegs.reset(Reg);
135135 // both defined and used in the same instruction.
136136 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
137137 const MachineOperand &MO = MI->getOperand(i);
138 if (MO.isRegister() && MO.isUse()) {
138 if (MO.isReg() && MO.isUse()) {
139139 unsigned Reg = MO.getReg();
140140 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
141141 LivePhysRegs.set(Reg);
301301 continue;
302302 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
303303 MachineOperand& mop = MI->getOperand(i);
304 if (!mop.isRegister())
304 if (!mop.isReg())
305305 continue;
306306 unsigned PhysReg = mop.getReg();
307307 if (PhysReg == 0 || PhysReg == li.reg)
722722 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
723723 MachineOperand &MO = MI->getOperand(i);
724724 // handle register defs - build intervals
725 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
725 if (MO.isReg() && MO.getReg() && MO.isDef()) {
726726 handleRegisterDef(MBB, MI, MIIndex, MO, i);
727727 }
728728 }
788788 unsigned RegOp = 0;
789789 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
790790 MachineOperand &MO = MI->getOperand(i);
791 if (!MO.isRegister() || !MO.isUse())
791 if (!MO.isReg() || !MO.isUse())
792792 continue;
793793 unsigned Reg = MO.getReg();
794794 if (Reg == 0 || Reg == li.reg)
875875 unsigned ImpUse = 0;
876876 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
877877 const MachineOperand &MO = MI->getOperand(i);
878 if (MO.isRegister()) {
878 if (MO.isReg()) {
879879 unsigned Reg = MO.getReg();
880880 if (Reg == 0)
881881 continue;
10921092 // use operand. Make sure we rewrite that as well.
10931093 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
10941094 MachineOperand &MO = MI->getOperand(i);
1095 if (!MO.isRegister())
1095 if (!MO.isReg())
10961096 continue;
10971097 unsigned Reg = MO.getReg();
10981098 if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
11271127 RestartInstruction:
11281128 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
11291129 MachineOperand& mop = MI->getOperand(i);
1130 if (!mop.isRegister())
1130 if (!mop.isReg())
11311131 continue;
11321132 unsigned Reg = mop.getReg();
11331133 unsigned RegI = Reg;
11791179 Ops.push_back(i);
11801180 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
11811181 const MachineOperand &MOj = MI->getOperand(j);
1182 if (!MOj.isRegister())
1182 if (!MOj.isReg())
11831183 continue;
11841184 unsigned RegJ = MOj.getReg();
11851185 if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ))
16171617 NewLIs.push_back(&getOrCreateInterval(NewVReg));
16181618 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
16191619 MachineOperand &MO = MI->getOperand(i);
1620 if (MO.isRegister() && MO.getReg() == li.reg)
1620 if (MO.isReg() && MO.getReg() == li.reg)
16211621 MO.setReg(NewVReg);
16221622 }
16231623 }
16611661
16621662 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
16631663 MachineOperand& mop = MI->getOperand(i);
1664 if (!mop.isRegister() || mop.getReg() != li.reg) continue;
1664 if (!mop.isReg() || mop.getReg() != li.reg) continue;
16651665
16661666 HasUse |= MI->getOperand(i).isUse();
16671667 HasDef |= MI->getOperand(i).isDef();
19151915 CanFold = true;
19161916 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
19171917 MachineOperand &MO = MI->getOperand(j);
1918 if (!MO.isRegister() || MO.getReg() != VReg)
1918 if (!MO.isReg() || MO.getReg() != VReg)
19191919 continue;
19201920
19211921 Ops.push_back(j);
19861986 CanFold = true;
19871987 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
19881988 MachineOperand &MO = MI->getOperand(j);
1989 if (!MO.isRegister() || MO.getReg() != VReg)
1989 if (!MO.isReg() || MO.getReg() != VReg)
19901990 continue;
19911991
19921992 if (MO.isDef()) {
557557 SmallVector DefRegs;
558558 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
559559 const MachineOperand &MO = MI->getOperand(i);
560 if (MO.isRegister() && MO.getReg()) {
560 if (MO.isReg() && MO.getReg()) {
561561 unsigned MOReg = MO.getReg();
562562 if (MO.isUse())
563563 UseRegs.push_back(MOReg);
671671 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
672672 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
673673 MachineOperand &MO = MI->getOperand(i);
674 if (MO.isRegister() && MO.isKill()) {
674 if (MO.isReg() && MO.isKill()) {
675675 MO.setIsKill(false);
676676 unsigned Reg = MO.getReg();
677677 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6363 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
6464 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
6565
66 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
67 MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
68 MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
66 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
67 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
68 MI->getOperand(2).isImm() && "Malformed extract_subreg");
6969
7070 unsigned DstReg = MI->getOperand(0).getReg();
7171 unsigned SuperReg = MI->getOperand(1).getReg();
101101 MachineFunction &MF = *MBB->getParent();
102102 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
103103 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
104 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
105 MI->getOperand(1).isImmediate() &&
106 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
107 MI->getOperand(3).isImmediate() && "Invalid subreg_to_reg");
104 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
105 MI->getOperand(1).isImm() &&
106 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
107 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
108108
109109 unsigned DstReg = MI->getOperand(0).getReg();
110110 unsigned InsReg = MI->getOperand(2).getReg();
145145 MachineFunction &MF = *MBB->getParent();
146146 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
147147 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
148 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
149 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
150 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
151 MI->getOperand(3).isImmediate() && "Invalid insert_subreg");
148 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
149 (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
150 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
151 MI->getOperand(3).isImm() && "Invalid insert_subreg");
152152
153153 unsigned DstReg = MI->getOperand(0).getReg();
154154 unsigned SrcReg = MI->getOperand(1).getReg();
289289 // Scan the operands of this machine instruction, replacing any uses of Old
290290 // with New.
291291 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
292 if (I->getOperand(i).isMachineBasicBlock() &&
292 if (I->getOperand(i).isMBB() &&
293293 I->getOperand(i).getMBB() == Old)
294294 I->getOperand(i).setMBB(New);
295295 }
3636 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
3737 /// explicitly nulled out.
3838 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
39 assert(isRegister() && "Can only add reg operand to use lists");
39 assert(isReg() && "Can only add reg operand to use lists");
4040
4141 // If the reginfo pointer is null, just explicitly null out or next/prev
4242 // pointers, to ensure they are not garbage.
9191 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
9292 // If this operand is currently a register operand, and if this is in a
9393 // function, deregister the operand from the register's use/def list.
94 if (isRegister() && getParent() && getParent()->getParent() &&
94 if (isReg() && getParent() && getParent()->getParent() &&
9595 getParent()->getParent()->getParent())
9696 RemoveRegOperandFromRegInfo();
9797
106106 bool isKill, bool isDead) {
107107 // If this operand is already a register operand, use setReg to update the
108108 // register's use/def lists.
109 if (isRegister()) {
109 if (isReg()) {
110110 assert(!isEarlyClobber());
111111 setReg(Reg);
112112 } else {
355355 #ifndef NDEBUG
356356 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
357357 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
358 assert((!Operands[i].isRegister() || !Operands[i].isOnRegUseList()) &&
358 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
359359 "Reg operand def/use list corrupted");
360360 }
361361 #endif
375375 /// operands already be on their use lists.
376376 void MachineInstr::RemoveRegOperandsFromUseLists() {
377377 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
378 if (Operands[i].isRegister())
378 if (Operands[i].isReg())
379379 Operands[i].RemoveRegOperandFromRegInfo();
380380 }
381381 }
385385 /// operands not be on their use lists yet.
386386 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
387387 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
388 if (Operands[i].isRegister())
388 if (Operands[i].isReg())
389389 Operands[i].AddRegOperandToRegInfo(&RegInfo);
390390 }
391391 }
396396 /// an explicit operand it is added at the end of the explicit operand list
397397 /// (before the first implicit operand).
398398 void MachineInstr::addOperand(const MachineOperand &Op) {
399 bool isImpReg = Op.isRegister() && Op.isImplicit();
399 bool isImpReg = Op.isReg() && Op.isImplicit();
400400 assert((isImpReg || !OperandsComplete()) &&
401401 "Trying to add an operand to a machine instr that is already done!");
402402
412412 Operands.back().ParentMI = this;
413413
414414 // If the operand is a register, update the operand's use list.
415 if (Op.isRegister())
415 if (Op.isReg())
416416 Operands.back().AddRegOperandToRegInfo(getRegInfo());
417417 return;
418418 }
432432
433433 // Do explicitly set the reginfo for this operand though, to ensure the
434434 // next/prev fields are properly nulled out.
435 if (Operands[OpNo].isRegister())
435 if (Operands[OpNo].isReg())
436436 Operands[OpNo].AddRegOperandToRegInfo(0);
437437
438438 } else if (Operands.size()+1 <= Operands.capacity()) {
445445 // list, just remove the implicit operands, add the operand, then re-add all
446446 // the rest of the operands.
447447 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
448 assert(Operands[i].isRegister() && "Should only be an implicit reg!");
448 assert(Operands[i].isReg() && "Should only be an implicit reg!");
449449 Operands[i].RemoveRegOperandFromRegInfo();
450450 }
451451
453453 Operands.insert(Operands.begin()+OpNo, Op);
454454 Operands[OpNo].ParentMI = this;
455455
456 if (Operands[OpNo].isRegister())
456 if (Operands[OpNo].isReg())
457457 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
458458
459459 // Re-add all the implicit ops.
460460 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
461 assert(Operands[i].isRegister() && "Should only be an implicit reg!");
461 assert(Operands[i].isReg() && "Should only be an implicit reg!");
462462 Operands[i].AddRegOperandToRegInfo(RegInfo);
463463 }
464464 } else {
484484 // Special case removing the last one.
485485 if (OpNo == Operands.size()-1) {
486486 // If needed, remove from the reg def/use list.
487 if (Operands.back().isRegister() && Operands.back().isOnRegUseList())
487 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
488488 Operands.back().RemoveRegOperandFromRegInfo();
489489
490490 Operands.pop_back();
497497 MachineRegisterInfo *RegInfo = getRegInfo();
498498 if (RegInfo) {
499499 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
500 if (Operands[i].isRegister())
500 if (Operands[i].isReg())
501501 Operands[i].RemoveRegOperandFromRegInfo();
502502 }
503503 }
506506
507507 if (RegInfo) {
508508 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
509 if (Operands[i].isRegister())
509 if (Operands[i].isReg())
510510 Operands[i].AddRegOperandToRegInfo(RegInfo);
511511 }
512512 }
560560
561561 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
562562 const MachineOperand &MO = getOperand(NumOperands);
563 if (!MO.isRegister() || !MO.isImplicit())
563 if (!MO.isReg() || !MO.isImplicit())
564564 NumOperands++;
565565 }
566566 return NumOperands;
588588 const TargetRegisterInfo *TRI) const {
589589 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
590590 const MachineOperand &MO = getOperand(i);
591 if (!MO.isRegister() || !MO.isUse())
591 if (!MO.isReg() || !MO.isUse())
592592 continue;
593593 unsigned MOReg = MO.getReg();
594594 if (!MOReg)
612612 const TargetRegisterInfo *TRI) const {
613613 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
614614 const MachineOperand &MO = getOperand(i);
615 if (!MO.isRegister() || !MO.isDef())
615 if (!MO.isReg() || !MO.isDef())
616616 continue;
617617 unsigned MOReg = MO.getReg();
618618 if (MOReg == Reg ||
646646 const TargetInstrDesc &TID = getDesc();
647647 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
648648 const MachineOperand &MO = getOperand(i);
649 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
649 if (MO.isReg() && MO.isUse() && MO.getReg() == Reg &&
650650 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
651651 return true;
652652 }
658658 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
659659 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
660660 const MachineOperand &MO = MI->getOperand(i);
661 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
661 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
662662 continue;
663663 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
664664 MachineOperand &MOp = getOperand(j);
721721 return false;
722722 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
723723 MachineOperand &MO = getOperand(i);
724 if (!MO.isRegister())
724 if (!MO.isReg())
725725 continue;
726726 // FIXME: For now, do not remat any instruction with register operands.
727727 // Later on, we can loosen the restriction is the register operands have
769769 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
770770 // Specialize printing if op#0 is definition
771771 unsigned StartOp = 0;
772 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
772 if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
773773 getOperand(0).print(OS, TM);
774774 OS << " = ";
775775 ++StartOp; // Don't print this operand again!
830830 SmallVector DeadOps;
831831 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
832832 MachineOperand &MO = getOperand(i);
833 if (!MO.isRegister() || !MO.isUse())
833 if (!MO.isReg() || !MO.isUse())
834834 continue;
835835 unsigned Reg = MO.getReg();
836836 if (!Reg)
885885 SmallVector DeadOps;
886886 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
887887 MachineOperand &MO = getOperand(i);
888 if (!MO.isRegister() || !MO.isDef())
888 if (!MO.isReg() || !MO.isDef())
889889 continue;
890890 unsigned Reg = MO.getReg();
891891 if (!Reg)
247247 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
248248 const MachineOperand &MO = I.getOperand(i);
249249
250 if (!MO.isRegister())
250 if (!MO.isReg())
251251 continue;
252252
253253 if (MO.isDef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
154154
155155 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
156156 const MachineOperand &MO = MI->getOperand(i);
157 if (!MO.isRegister()) continue; // Ignore non-register operands.
157 if (!MO.isReg()) continue; // Ignore non-register operands.
158158
159159 unsigned Reg = MO.getReg();
160160 if (Reg == 0) continue;
559559 bool DoIncr = true;
560560
561561 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
562 if (MI->getOperand(i).isFrameIndex()) {
562 if (MI->getOperand(i).isFI()) {
563563 // Some instructions (e.g. inline asm instructions) can have
564564 // multiple frame indices and/or cause eliminateFrameIndex
565565 // to insert more than one instruction. We need the register
559559 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
560560 MachineOperand& MO = MI->getOperand(i);
561561 // look for vreg reads..
562 if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
562 if (MO.isReg() && !MO.isDef() && MO.getReg() &&
563563 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
564564 // ..and add them to the read table.
565565 VRegTimes* &Times = VRegReadTable[MO.getReg()];
588588 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
589589 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
590590 MachineOperand& MO = MI->getOperand(i);
591 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
591 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
592592 MO.isDef() && !MO.isDead())
593593 return true;
594594 }
600600 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
601601 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
602602 MachineOperand& MO = MI->getOperand(i);
603 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
603 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
604604 !MO.isDef() && MO.isKill())
605605 return true;
606606 }
652652 SmallVector Kills;
653653 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
654654 MachineOperand& MO = MI->getOperand(i);
655 if (MO.isRegister() && MO.isKill()) {
655 if (MO.isReg() && MO.isKill()) {
656656 if (!MO.isImplicit())
657657 Kills.push_back(MO.getReg());
658658 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
672672 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
673673 MachineOperand& MO = MI->getOperand(i);
674674 // here we are looking for only used operands (never def&use)
675 if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
675 if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
676676 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
677677 MI = reloadVirtReg(MBB, MI, i);
678678 }
718718 // are defined, and marking explicit destinations in the PhysRegsUsed map.
719719 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
720720 MachineOperand& MO = MI->getOperand(i);
721 if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
721 if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
722722 TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
723723 unsigned Reg = MO.getReg();
724724 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
763763 SmallVector DeadDefs;
764764 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
765765 MachineOperand& MO = MI->getOperand(i);
766 if (MO.isRegister() && MO.isDead())
766 if (MO.isReg() && MO.isDead())
767767 DeadDefs.push_back(MO.getReg());
768768 }
769769
774774 //
775775 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
776776 MachineOperand& MO = MI->getOperand(i);
777 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
777 if (MO.isReg() && MO.isDef() && MO.getReg() &&
778778 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
779779 unsigned DestVirtReg = MO.getReg();
780780 unsigned DestPhysReg;
520520 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
521521 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
522522 MachineOperand& MO = MI->getOperand(i);
523 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
523 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
524524 MO.isDef() && !MO.isDead())
525525 return true;
526526 }
532532 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
533533 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
534534 MachineOperand& MO = MI->getOperand(i);
535 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
535 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
536536 !MO.isDef() && MO.isKill())
537537 return true;
538538 }
574574 // them for later. Also, we have to process these
575575 // _before_ processing the defs, since an instr
576576 // uses regs before it defs them.
577 if (MO.isRegister() && MO.getReg() && MO.isUse())
577 if (MO.isReg() && MO.getReg() && MO.isUse())
578578 LastUseDef[MO.getReg()] = std::make_pair(I, i);
579579 }
580580
583583 // Defs others than 2-addr redefs _do_ trigger flag changes:
584584 // - A def followed by a def is dead
585585 // - A use followed by a def is a kill
586 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
586 if (MO.isReg() && MO.getReg() && MO.isDef()) {
587587 DenseMap >::iterator
588588 last = LastUseDef.find(MO.getReg());
589589 if (last != LastUseDef.end()) {
710710 SmallVector Kills;
711711 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
712712 MachineOperand& MO = MI->getOperand(i);
713 if (MO.isRegister() && MO.isKill()) {
713 if (MO.isReg() && MO.isKill()) {
714714 if (!MO.isImplicit())
715715 Kills.push_back(MO.getReg());
716716 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
728728 if (MI->getOpcode()==TargetInstrInfo::INLINEASM) {
729729 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
730730 MachineOperand& MO = MI->getOperand(i);
731 if (MO.isRegister() && MO.isDef() && MO.isEarlyClobber() &&
731 if (MO.isReg() && MO.isDef() && MO.isEarlyClobber() &&
732732 MO.getReg()) {
733733 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
734734 unsigned DestVirtReg = MO.getReg();
779779 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
780780 MachineOperand& MO = MI->getOperand(i);
781781 // here we are looking for only used operands (never def&use)
782 if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
782 if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
783783 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
784784 MI = reloadVirtReg(MBB, MI, i);
785785 }
825825 // are defined, and marking explicit destinations in the PhysRegsUsed map.
826826 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
827827 MachineOperand& MO = MI->getOperand(i);
828 if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
828 if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
829829 !MO.isEarlyClobber() &&
830830 TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
831831 unsigned Reg = MO.getReg();
876876 SmallVector DeadDefs;
877877 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
878878 MachineOperand& MO = MI->getOperand(i);
879 if (MO.isRegister() && MO.isDead())
879 if (MO.isReg() && MO.isDead())
880880 DeadDefs.push_back(MO.getReg());
881881 }
882882
887887 //
888888 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
889889 MachineOperand& MO = MI->getOperand(i);
890 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
890 if (MO.isReg() && MO.isDef() && MO.getReg() &&
891891 !MO.isEarlyClobber() &&
892892 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
893893 unsigned DestVirtReg = MO.getReg();
264264 const MachineOperand &mo = instr->getOperand(opNo);
265265
266266 // We're not interested in non-registers...
267 if (!mo.isRegister())
267 if (!mo.isReg())
268268 continue;
269269
270270 unsigned moReg = mo.getReg();
189189 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
190190 MachineOperand &MO = MI->getOperand(i);
191191
192 if (MO.isRegister() && MO.getReg() &&
192 if (MO.isReg() && MO.getReg() &&
193193 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
194194 unsigned virtualReg = (unsigned) MO.getReg();
195195 DOUT << "op: " << MO << "\n";
208208 // must be same register number as the source operand that is
209209 // tied to. This maps a = b + c into b = b + c, and saves b into
210210 // a's spot.
211 assert(MI->getOperand(TiedOp).isRegister() &&
211 assert(MI->getOperand(TiedOp).isReg() &&
212212 MI->getOperand(TiedOp).getReg() &&
213213 MI->getOperand(TiedOp).isUse() &&
214214 "Two address instruction invalid!");
3434 bool SeenSuperDef = false;
3535 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3636 const MachineOperand &MO = MI->getOperand(i);
37 if (!MO.isRegister())
37 if (!MO.isReg())
3838 continue;
3939 if (TRI->isSuperRegister(SubReg, MO.getReg())) {
4040 if (MO.isUse())
5050 static bool RedefinesSuperRegPart(const MachineInstr *MI,
5151 const MachineOperand &MO,
5252 const TargetRegisterInfo *TRI) {
53 assert(MO.isRegister() && MO.isDef() && "Not a register def!");
53 assert(MO.isReg() && MO.isDef() && "Not a register def!");
5454 return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
5555 }
5656
193193 BitVector ChangedRegs(NumPhysRegs);
194194 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
195195 const MachineOperand &MO = MI->getOperand(i);
196 if (!MO.isRegister() || !MO.isUse())
196 if (!MO.isReg() || !MO.isUse())
197197 continue;
198198
199199 unsigned Reg = MO.getReg();
227227 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
228228 const MachineOperand &MO = MI->getOperand(i);
229229
230 if (!MO.isRegister() || !MO.isDef())
230 if (!MO.isReg() || !MO.isDef())
231231 continue;
232232
233233 unsigned Reg = MO.getReg();
269269 const TargetInstrDesc &TID = MI->getDesc();
270270 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
271271 const MachineOperand &MO = MI->getOperand(i);
272 if (!MO.isRegister() || !MO.isDef())
272 if (!MO.isReg() || !MO.isDef())
273273 continue;
274274 // Skip two-address destination operand.
275275 if (TID.findTiedToSrcOperand(i) != -1)
284284 BitVector ChangedRegs(NumPhysRegs);
285285 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
286286 const MachineOperand &MO = MI->getOperand(i);
287 if (!MO.isRegister() || !MO.isUse())
287 if (!MO.isReg() || !MO.isUse())
288288 continue;
289289 unsigned Reg = MO.getReg();
290290 if (Reg == 0)
377377 // Exclude all the registers being used by the instruction.
378378 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
379379 MachineOperand &MO = I->getOperand(i);
380 if (MO.isRegister())
380 if (MO.isReg())
381381 Candidates.reset(MO.getReg());
382382 }
383383
465465 for (unsigned i = CopyMI->getDesc().getNumOperands(),
466466 e = CopyMI->getNumOperands(); i != e; ++i) {
467467 MachineOperand &MO = CopyMI->getOperand(i);
468 if (MO.isRegister() && MO.isImplicit())
468 if (MO.isReg() && MO.isImplicit())
469469 NewMI->addOperand(MO);
470470 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
471471 unsigned Reg = MO.getReg();
874874 // Each use MI may have multiple uses of this register. Change them all.
875875 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
876876 MachineOperand &MO = MI->getOperand(i);
877 if (MO.isRegister() && MO.getReg() == li.reg)
877 if (MO.isReg() && MO.getReg() == li.reg)
878878 MO.setReg(DstReg);
879879 }
880880 JoinedCopies.insert(MI);
21592159 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg))
21602160 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
21612161 MachineOperand &Use = MI->getOperand(i);
2162 if (Use.isRegister() && Use.isUse() && Use.getReg() &&
2162 if (Use.isReg() && Use.isUse() && Use.getReg() &&
21632163 tri_->regsOverlap(Use.getReg(), Reg)) {
21642164 UseIdx = e;
21652165 return &Use;
22972297 bool isDead = true;
22982298 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
22992299 const MachineOperand &MO = MI->getOperand(i);
2300 if (!MO.isRegister() || MO.isDead())
2300 if (!MO.isReg() || MO.isDead())
23012301 continue;
23022302 unsigned Reg = MO.getReg();
23032303 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
23322332 SmallSet UniqueUses;
23332333 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
23342334 const MachineOperand &mop = MI->getOperand(i);
2335 if (mop.isRegister() && mop.getReg() &&
2335 if (mop.isReg() && mop.getReg() &&
23362336 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
23372337 unsigned reg = mop.getReg();
23382338 // Multiple uses of reg by the same instruction. It should not
219219 MachineInstr &MI = *MII;
220220 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
221221 MachineOperand &MO = MI.getOperand(i);
222 if (!MO.isFrameIndex())
222 if (!MO.isFI())
223223 continue;
224224 int FI = MO.getIndex();
225225 if (FI < 0)
811811 continue;
812812
813813 for (unsigned i = 0; i < I->getNumOperands(); ++i)
814 if (I->getOperand(i).isRegister() &&
814 if (I->getOperand(i).isReg() &&
815815 Stacks[I->getOperand(i).getReg()].size()) {
816816 // Remove the live range for the old vreg.
817817 LiveInterval& OldInt = LI.getInterval(I->getOperand(i).getReg());
2121 // operand 1 and 2.
2222 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
2323 bool NewMI) const {
24 assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
24 assert(MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
2525 "This only knows how to commute register operands so far");
2626 unsigned Reg1 = MI->getOperand(1).getReg();
2727 unsigned Reg2 = MI->getOperand(2).getReg();
6363 /// two-address instruction.
6464 bool TargetInstrInfoImpl::CommuteChangesDestination(MachineInstr *MI,
6565 unsigned &OpIdx) const{
66 assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
66 assert(MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
6767 "This only knows how to commute register operands so far");
6868 if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
6969 // Must be two address instruction!
8686 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
8787 if (TID.OpInfo[i].isPredicate()) {
8888 MachineOperand &MO = MI->getOperand(i);
89 if (MO.isRegister()) {
89 if (MO.isReg()) {
9090 MO.setReg(Pred[j].getReg());
9191 MadeChange = true;
92 } else if (MO.isImmediate()) {
92 } else if (MO.isImm()) {
9393 MO.setImm(Pred[j].getImm());
9494 MadeChange = true;
95 } else if (MO.isMachineBasicBlock()) {
95 } else if (MO.isMBB()) {
9696 MO.setMBB(Pred[j].getMBB());
9797 MadeChange = true;
9898 }
107107
108108 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
109109 const MachineOperand &MO = MI->getOperand(i);
110 if (!MO.isRegister())
110 if (!MO.isReg())
111111 continue;
112112 unsigned MOReg = MO.getReg();
113113 if (!MOReg)
157157 ++NumVisited;
158158 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
159159 MachineOperand &MO = OtherMI->getOperand(i);
160 if (!MO.isRegister())
160 if (!MO.isReg())
161161 continue;
162162 unsigned MOReg = MO.getReg();
163163 if (!MOReg)
199199 const TargetInstrDesc &TID = UseMI->getDesc();
200200 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
201201 MachineOperand &MO = UseMI->getOperand(i);
202 if (MO.isRegister() && MO.getReg() == Reg &&
202 if (MO.isReg() && MO.getReg() == Reg &&
203203 (MO.isDef() || TID.getOperandConstraint(i, TOI::TIED_TO) != -1))
204204 // Earlier use is a two-address one.
205205 return true;
291291
292292 FirstTied = false;
293293
294 assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() &&
294 assert(mi->getOperand(si).isReg() && mi->getOperand(si).getReg() &&
295295 mi->getOperand(si).isUse() && "two address instruction invalid");
296296
297297 // If the two operands are the same we just remove the use
315315 // should never occur because we are in SSA form.
316316 for (unsigned i = 0; i != mi->getNumOperands(); ++i)
317317 assert((int)i == ti ||
318 !mi->getOperand(i).isRegister() ||
318 !mi->getOperand(i).isReg() ||
319319 mi->getOperand(i).getReg() != regA);
320320 #endif
321321
329329 // and C joinable.
330330 // FIXME: This code also works for A := B op C instructions.
331331 if (TID.isCommutable() && mi->getNumOperands() >= 3) {
332 assert(mi->getOperand(3-si).isRegister() &&
332 assert(mi->getOperand(3-si).isReg() &&
333333 "Not a proper commutative instruction!");
334334 unsigned regC = mi->getOperand(3-si).getReg();
335335
432432
433433 // Replace all occurences of regB with regA.
434434 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
435 if (mi->getOperand(i).isRegister() &&
435 if (mi->getOperand(i).isReg() &&
436436 mi->getOperand(i).getReg() == regB)
437437 mi->getOperand(i).setReg(regA);
438438 }
126126 while (start != succ->end() &&
127127 start->getOpcode() == TargetInstrInfo::PHI) {
128128 for (unsigned i = start->getNumOperands() - 1; i >= 2; i-=2)
129 if (start->getOperand(i).isMachineBasicBlock() &&
129 if (start->getOperand(i).isMBB() &&
130130 start->getOperand(i).getMBB() == BB) {
131131 start->RemoveOperand(i);
132132 start->RemoveOperand(i-1);
181181 void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
182182 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
183183 MachineOperand &MO = MI->getOperand(i);
184 if (!MO.isFrameIndex())
184 if (!MO.isFI())
185185 continue;
186186 int FI = MO.getIndex();
187187 if (MF.getFrameInfo()->isFixedObjectIndex(FI))
258258 MachineInstr &MI = *MII;
259259 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
260260 MachineOperand &MO = MI.getOperand(i);
261 if (MO.isRegister() && MO.getReg()) {
261 if (MO.isReg() && MO.getReg()) {
262262 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
263263 unsigned VirtReg = MO.getReg();
264264 unsigned SubIdx = MO.getSubReg();
559559 SmallVector *KillRegs = NULL) {
560560 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
561561 MachineOperand &MO = MI.getOperand(i);
562 if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
562 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
563563 continue;
564564 unsigned Reg = MO.getReg();
565565 if (TargetRegisterInfo::isVirtualRegister(Reg))
598598 MachineOperand *DefOp = NULL;
599599 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
600600 MachineOperand &MO = DefMI->getOperand(i);
601 if (MO.isRegister() && MO.isDef()) {
601 if (MO.isReg() && MO.isDef()) {
602602 if (MO.getReg() == Reg)
603603 DefOp = &MO;
604604 else if (!MO.isDead())
615615 MachineInstr *NMI = I;
616616 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
617617 MachineOperand &MO = NMI->getOperand(j);
618 if (!MO.isRegister() || MO.getReg() != Reg)
618 if (!MO.isReg() || MO.getReg() != Reg)
619619 continue;
620620 if (MO.isUse())
621621 FoundUse = true;
638638 const TargetInstrDesc &TID = MI.getDesc();
639639 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
640640 MachineOperand &MO = MI.getOperand(i);
641 if (!MO.isRegister() || !MO.isUse())
641 if (!MO.isReg() || !MO.isUse())
642642 continue;
643643 unsigned Reg = MO.getReg();
644644 if (Reg == 0)
663663
664664 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
665665 const MachineOperand &MO = MI.getOperand(i);
666 if (!MO.isRegister() || !MO.isDef())
666 if (!MO.isReg() || !MO.isDef())
667667 continue;
668668 unsigned Reg = MO.getReg();
669669 RegKills.reset(Reg);
683683 MachineInstr *NewMI = prior(MII);
684684 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
685685 MachineOperand &MO = NewMI->getOperand(i);
686 if (!MO.isRegister() || MO.getReg() == 0)
686 if (!MO.isReg() || MO.getReg() == 0)
687687 continue;
688688 unsigned VirtReg = MO.getReg();
689689 if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
932932
933933 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
934934 MachineOperand &MO = MI.getOperand(i);
935 if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse())
935 if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse())
936936 continue;
937937 unsigned VirtReg = MO.getReg();
938938 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
10321032 int DefIdx = TID.getOperandConstraint(UseIdx, TOI::TIED_TO);
10331033 if (DefIdx == -1)
10341034 return false;
1035 assert(DefMI->getOperand(DefIdx).isRegister() &&
1035 assert(DefMI->getOperand(DefIdx).isReg() &&
10361036 DefMI->getOperand(DefIdx).getReg() == SrcReg);
10371037
10381038 // Now commute def instruction.
11751175 MachineOperand *LastUD = NULL;
11761176 for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) {
11771177 MachineOperand &MO = LastUDMI->getOperand(i);
1178 if (!MO.isRegister() || MO.getReg() != Reg)
1178 if (!MO.isReg() || MO.getReg() != Reg)
11791179 continue;
11801180 if (!LastUD || (LastUD->isUse() && MO.isDef()))
11811181 LastUD = &MO;
13141314 SmallVector VirtUseOps;
13151315 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
13161316 MachineOperand &MO = MI.getOperand(i);
1317 if (!MO.isRegister() || MO.getReg() == 0)
1317 if (!MO.isReg() || MO.getReg() == 0)
13181318 continue; // Ignore non-register operands.
13191319
13201320 unsigned VirtReg = MO.getReg();
13941394 bool CanReuse = true;
13951395 int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
13961396 if (ti != -1 &&
1397 MI.getOperand(ti).isRegister() &&
1397 MI.getOperand(ti).isReg() &&
13981398 MI.getOperand(ti).getReg() == VirtReg) {
13991399 // Okay, we have a two address operand. We can reuse this physreg as
14001400 // long as we are allowed to clobber the value and there isn't an
17241724 // Process all of the spilled defs.
17251725 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
17261726 MachineOperand &MO = MI.getOperand(i);
1727 if (!(MO.isRegister() && MO.getReg() && MO.isDef()))
1727 if (!(MO.isReg() && MO.getReg() && MO.isDef()))
17281728 continue;
17291729
17301730 unsigned VirtReg = MO.getReg();
755755 unsigned NumOps = Desc.getNumOperands();
756756 for (unsigned CurOp = 0; CurOp < NumOps; CurOp++) {
757757 const MachineOperand &MO = MI.getOperand(CurOp);
758 if (MO.isGlobalAddress()) {
758 if (MO.isGlobal()) {
759759 GlobalValue* V = MO.getGlobal();
760760 const GlobalVariable *GV = dyn_cast(V);
761761 if (!GV)
180180 /// operand requires relocation, record the relocation and return zero.
181181 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
182182 const MachineOperand &MO) {
183 if (MO.isRegister())
183 if (MO.isReg())
184184 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
185 else if (MO.isImmediate())
185 else if (MO.isImm())
186186 return static_cast(MO.getImm());
187 else if (MO.isGlobalAddress())
187 else if (MO.isGlobal())
188188 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, false);
189 else if (MO.isExternalSymbol())
189 else if (MO.isSymbol())
190190 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
191 else if (MO.isConstantPoolIndex())
191 else if (MO.isCPI())
192192 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
193 else if (MO.isJumpTableIndex())
193 else if (MO.isJTI())
194194 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
195 else if (MO.isMachineBasicBlock())
195 else if (MO.isMBB())
196196 emitMachineBasicBlock(MO.getMBB());
197197 else {
198198 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
350350 const TargetInstrDesc &TID) const {
351351 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
352352 const MachineOperand &MO = MI.getOperand(i-1);
353 if (MO.isRegister() && MO.isDef() && MO.getReg() == ARM::CPSR)
353 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
354354 return 1 << ARMII::S_BitShift;
355355 }
356356 return 0;
413413 return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
414414
415415 const MachineOperand &MO = MI.getOperand(OpIdx);
416 if (MO.isRegister())
416 if (MO.isReg())
417417 // Encode register Rm.
418418 return Binary | getMachineOpValue(MI, NumDefs + 1);
419419
537537 // Set registers
538538 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
539539 const MachineOperand &MO = MI.getOperand(i);
540 if (MO.isRegister() && MO.isImplicit())
540 if (MO.isReg() && MO.isImplicit())
541541 continue;
542542 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
543543 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
415415
416416 // Scan the instructions for constant pool operands.
417417 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
418 if (I->getOperand(op).isConstantPoolIndex()) {
418 if (I->getOperand(op).isCPI()) {
419419 // We found one. The addressing mode tells us the max displacement
420420 // from the PC that this instruction permits.
421421
817817 U.CPEMI = CPEs[i].CPEMI;
818818 // Change the CPI in the instruction operand to refer to the clone.
819819 for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
820 if (UserMI->getOperand(j).isConstantPoolIndex()) {
820 if (UserMI->getOperand(j).isCPI()) {
821821 UserMI->getOperand(j).setIndex(CPEs[i].CPI);
822822 break;
823823 }
10571057
10581058 // Finally, change the CPI in the instruction operand to be ID.
10591059 for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
1060 if (UserMI->getOperand(i).isConstantPoolIndex()) {
1060 if (UserMI->getOperand(i).isCPI()) {
10611061 UserMI->getOperand(i).setIndex(ID);
10621062 break;
10631063 }
6363 case ARM::MOVr:
6464 case ARM::tMOVr:
6565 assert(MI.getDesc().getNumOperands() >= 2 &&
66 MI.getOperand(0).isRegister() &&
67 MI.getOperand(1).isRegister() &&
66 MI.getOperand(0).isReg() &&
67 MI.getOperand(1).isReg() &&
6868 "Invalid ARM MOV instruction");
6969 SrcReg = MI.getOperand(1).getReg();
7070 DstReg = MI.getOperand(0).getReg();
7676 switch (MI->getOpcode()) {
7777 default: break;
7878 case ARM::LDR:
79 if (MI->getOperand(1).isFrameIndex() &&
80 MI->getOperand(2).isRegister() &&
81 MI->getOperand(3).isImmediate() &&
79 if (MI->getOperand(1).isFI() &&
80 MI->getOperand(2).isReg() &&
81 MI->getOperand(3).isImm() &&
8282 MI->getOperand(2).getReg() == 0 &&
8383 MI->getOperand(3).getImm() == 0) {
8484 FrameIndex = MI->getOperand(1).getIndex();
8787 break;
8888 case ARM::FLDD:
8989 case ARM::FLDS:
90 if (MI->getOperand(1).isFrameIndex() &&
91 MI->getOperand(2).isImmediate() &&
90 if (MI->getOperand(1).isFI() &&
91 MI->getOperand(2).isImm() &&
9292 MI->getOperand(2).getImm() == 0) {
9393 FrameIndex = MI->getOperand(1).getIndex();
9494 return MI->getOperand(0).getReg();
9595 }
9696 break;
9797 case ARM::tRestore:
98 if (MI->getOperand(1).isFrameIndex() &&
99 MI->getOperand(2).isImmediate() &&
98 if (MI->getOperand(1).isFI() &&
99 MI->getOperand(2).isImm() &&
100100 MI->getOperand(2).getImm() == 0) {
101101 FrameIndex = MI->getOperand(1).getIndex();
102102 return MI->getOperand(0).getReg();
110110 switch (MI->getOpcode()) {
111111 default: break;
112112 case ARM::STR:
113 if (MI->getOperand(1).isFrameIndex() &&
114 MI->getOperand(2).isRegister() &&
115 MI->getOperand(3).isImmediate() &&
113 if (MI->getOperand(1).isFI() &&
114 MI->getOperand(2).isReg() &&
115 MI->getOperand(3).isImm() &&
116116 MI->getOperand(2).getReg() == 0 &&
117117 MI->getOperand(3).getImm() == 0) {
118118 FrameIndex = MI->getOperand(1).getIndex();
121121 break;
122122 case ARM::FSTD:
123123 case ARM::FSTS:
124 if (MI->getOperand(1).isFrameIndex() &&
125 MI->getOperand(2).isImmediate() &&
124 if (MI->getOperand(1).isFI() &&
125 MI->getOperand(2).isImm() &&
126126 MI->getOperand(2).getImm() == 0) {
127127 FrameIndex = MI->getOperand(1).getIndex();
128128 return MI->getOperand(0).getReg();
129129 }
130130 break;
131131 case ARM::tSpill:
132 if (MI->getOperand(1).isFrameIndex() &&
133 MI->getOperand(2).isImmediate() &&
132 if (MI->getOperand(1).isFI() &&
133 MI->getOperand(2).isImm() &&
134134 MI->getOperand(2).getImm() == 0) {
135135 FrameIndex = MI->getOperand(1).getIndex();
136136 return MI->getOperand(0).getReg();
297297 // Transfer LiveVariables states, kill / dead info.
298298 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
299299 MachineOperand &MO = MI->getOperand(i);
300 if (MO.isRegister() && MO.getReg() &&
300 if (MO.isReg() && MO.getReg() &&
301301 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
302302 unsigned Reg = MO.getReg();
303303
490490
491491 static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
492492 MachineOperand &MO) {
493 if (MO.isRegister())
493 if (MO.isReg())
494494 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
495 else if (MO.isImmediate())
495 else if (MO.isImm())
496496 MIB = MIB.addImm(MO.getImm());
497 else if (MO.isFrameIndex())
497 else if (MO.isFI())
498498 MIB = MIB.addFrameIndex(MO.getIndex());
499499 else
500500 assert(0 && "Unknown operand for ARMInstrAddOperand!");
537537 if (RC == ARM::GPRRegisterClass) {
538538 ARMFunctionInfo *AFI = MF.getInfo();
539539 if (AFI->isThumbFunction()) {
540 Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
540 Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
541541 MachineInstrBuilder MIB =
542542 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
543543 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
593593 if (RC == ARM::GPRRegisterClass) {
594594 ARMFunctionInfo *AFI = MF.getInfo();
595595 if (AFI->isThumbFunction()) {
596 Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
596 Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
597597 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
598598 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
599599 MIB = ARMInstrAddOperand(MIB, Addr[i]);
867867 bool Found = false;
868868 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
869869 const MachineOperand &MO = MI->getOperand(i);
870 if (MO.isRegister() && MO.getReg() == ARM::CPSR) {
870 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
871871 Pred.push_back(MO);
872872 Found = true;
873873 }
543543 default: break;
544544 case ARM::LDR:
545545 case ARM::STR:
546 return MI->getOperand(1).isRegister() && MI->getOperand(2).getReg() == 0;
546 return MI->getOperand(1).isReg() && MI->getOperand(2).getReg() == 0;
547547 case ARM::FLDS:
548548 case ARM::FSTS:
549 return MI->getOperand(1).isRegister();
549 return MI->getOperand(1).isReg();
550550 case ARM::FLDD:
551551 case ARM::FSTD:
552 return MI->getOperand(1).isRegister();
552 return MI->getOperand(1).isReg();
553553 }
554554 return false;
555555 }
539539 ARMFunctionInfo *AFI = MF.getInfo();
540540 bool isThumb = AFI->isThumbFunction();
541541
542 while (!MI.getOperand(i).isFrameIndex()) {
542 while (!MI.getOperand(i).isFI()) {
543543 ++i;
544544 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
545545 }
10191019 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
10201020 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
10211021 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1022 if (I->getOperand(i).isFrameIndex()) {
1022 if (I->getOperand(i).isFI()) {
10231023 unsigned Opcode = I->getOpcode();
10241024 const TargetInstrDesc &Desc = TII.get(Opcode);
10251025 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
10851085 int Opc, unsigned Area,
10861086 const ARMSubtarget &STI) {
10871087 while (MBBI != MBB.end() &&
1088 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
1088 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
10891089 if (Area != 0) {
10901090 bool Done = false;
10911091 unsigned Category = 0;
12491249 return ((MI->getOpcode() == ARM::FLDD ||
12501250 MI->getOpcode() == ARM::LDR ||
12511251 MI->getOpcode() == ARM::tRestore) &&
1252 MI->getOperand(1).isFrameIndex() &&
1252 MI->getOperand(1).isFI() &&
12531253 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
12541254 }
12551255
358358 /// immediate in bits 0-7.
359359 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
360360 const MachineOperand &MO = MI->getOperand(OpNum);
361 assert(MO.isImmediate() && "Not a valid so_imm value!");
361 assert(MO.isImm() && "Not a valid so_imm value!");
362362 printSOImm(O, MO.getImm(), TAI);
363363 }
364364
366366 /// followed by a or to materialize.
367367 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
368368 const MachineOperand &MO = MI->getOperand(OpNum);
369 assert(MO.isImmediate() && "Not a valid so_imm value!");
369 assert(MO.isImm() && "Not a valid so_imm value!");
370370 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
371371 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
372372 printSOImm(O, ARM_AM::getSOImmVal(V1), TAI);
412412 const MachineOperand &MO2 = MI->getOperand(Op+1);
413413 const MachineOperand &MO3 = MI->getOperand(Op+2);
414414
415 if (!MO1.isRegister()) { // FIXME: This is for CP entries, but isn't right.
415 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
416416 printOperand(MI, Op);
417417 return;
418418 }
525525 const MachineOperand &MO1 = MI->getOperand(Op);
526526 const MachineOperand &MO2 = MI->getOperand(Op+1);
527527
528 if (!MO1.isRegister()) { // FIXME: This is for CP entries, but isn't right.
528 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
529529 printOperand(MI, Op);
530530 return;
531531 }
586586 const MachineOperand &MO2 = MI->getOperand(Op+1);
587587 const MachineOperand &MO3 = MI->getOperand(Op+2);
588588
589 if (!MO1.isRegister()) { // FIXME: This is for CP entries, but isn't right.
589 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
590590 printOperand(MI, Op);
591591 return;
592592 }
748748 // Fallthrough
749749 case 'H': // Write second word of DI / DF reference.
750750 // Verify that this operand has two consecutive registers.
751 if (!MI->getOperand(OpNo).isRegister() ||
751 if (!MI->getOperand(OpNo).isReg() ||
752752 OpNo+1 == MI->getNumOperands() ||
753 !MI->getOperand(OpNo+1).isRegister())
753 !MI->getOperand(OpNo+1).isReg())
754754 return true;
755755 ++OpNo; // Return the high-part.
756756 }
7979 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
8080 "Not physreg??");
8181 O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
82 } else if (MO.isImmediate()) {
82 } else if (MO.isImm()) {
8383 O << MO.getImm();
8484 assert(MO.getImm() < (1 << 30));
8585 } else {
147147 unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
148148 // or things that get fixed up later by the JIT.
149149
150 if (MO.isRegister()) {
150 if (MO.isReg()) {
151151 rv = getAlphaRegNumber(MO.getReg());
152 } else if (MO.isImmediate()) {
152 } else if (MO.isImm()) {
153153 rv = MO.getImm();
154 } else if (MO.isGlobalAddress() || MO.isExternalSymbol()
155 || MO.isConstantPoolIndex()) {
154 } else if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
156155 DOUT << MO << " is a relocated op for " << MI << "\n";
157156 unsigned Reloc = 0;
158157 int Offset = 0;
192191 assert(0 && "unknown relocatable instruction");
193192 abort();
194193 }
195 if (MO.isGlobalAddress())
194 if (MO.isGlobal())
196195 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
197196 Reloc, MO.getGlobal(), Offset,
198197 isa(MO.getGlobal()),
199198 useGOT));
200 else if (MO.isExternalSymbol())
199 else if (MO.isSymbol())
201200 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
202201 Reloc, MO.getSymbolName(),
203202 Offset, true));
204203 else
205204 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
206205 Reloc, MO.getIndex(), Offset));
207 } else if (MO.isMachineBasicBlock()) {
206 } else if (MO.isMBB()) {
208207 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
209208 Alpha::reloc_bsr, MO.getMBB()));
210209 }else {
3434 // or r1, r2, r2
3535 // cpys(s|t) r1 r2 r2
3636 assert(MI.getNumOperands() >= 3 &&
37 MI.getOperand(0).isRegister() &&
38 MI.getOperand(1).isRegister() &&
39 MI.getOperand(2).isRegister() &&
37 MI.getOperand(0).isReg() &&
38 MI.getOperand(1).isReg() &&
39 MI.getOperand(2).isReg() &&
4040 "invalid Alpha BIS instruction!");
4141 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
4242 sourceReg = MI.getOperand(1).getReg();
5656 case Alpha::LDWU:
5757 case Alpha::LDS:
5858 case Alpha::LDT:
59 if (MI->getOperand(1).isFrameIndex()) {
59 if (MI->getOperand(1).isFI()) {
6060 FrameIndex = MI->getOperand(1).getIndex();
6161 return MI->getOperand(0).getReg();
6262 }
7474 case Alpha::STW:
7575 case Alpha::STS:
7676 case Alpha::STT:
77 if (MI->getOperand(1).isFrameIndex()) {
77 if (MI->getOperand(1).isFI()) {
7878 FrameIndex = MI->getOperand(1).getIndex();
7979 return MI->getOperand(0).getReg();
8080 }
199199 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
200200 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
201201 MachineOperand &MO = Addr[i];
202 if (MO.isRegister())
202 if (MO.isReg())
203203 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
204204 else
205205 MIB.addImm(MO.getImm());
244244 BuildMI(MF, get(Opc), DestReg);
245245 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
246246 MachineOperand &MO = Addr[i];
247 if (MO.isRegister())
247 if (MO.isReg())
248248 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
249249 else
250250 MIB.addImm(MO.getImm());
158158 MachineFunction &MF = *MBB.getParent();
159159 bool FP = hasFP(MF);
160160
161 while (!MI.getOperand(i).isFrameIndex()) {
161 while (!MI.getOperand(i).isFI()) {
162162 ++i;
163163 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
164164 }
8080
8181 void printOperand(const MachineInstr *MI, unsigned OpNo) {
8282 const MachineOperand &MO = MI->getOperand(OpNo);
83 if (MO.isRegister()) {
83 if (MO.isReg()) {
8484 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
8585 O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
86 } else if (MO.isImmediate()) {
86 } else if (MO.isImm()) {
8787 O << MO.getImm();
8888 } else {
8989 printOp(MO);
185185 printMemRegImmS10(const MachineInstr *MI, unsigned OpNo)
186186 {
187187 const MachineOperand &MO = MI->getOperand(OpNo);
188 assert(MO.isImmediate()
189 && "printMemRegImmS10 first operand is not immedate");
188 assert(MO.isImm() &&
189 "printMemRegImmS10 first operand is not immedate");
190190 printS10ImmOperand(MI, OpNo);
191191 O << "(";
192192 printOperand(MI, OpNo+1);
197197 printAddr256K(const MachineInstr *MI, unsigned OpNo)
198198 {
199199 /* Note: operand 1 is an offset or symbol name. */
200 if (MI->getOperand(OpNo).isImmediate()) {
200 if (MI->getOperand(OpNo).isImm()) {
201201 printS16ImmOperand(MI, OpNo);
202202 } else {
203203 printOp(MI->getOperand(OpNo));
204 if (MI->getOperand(OpNo+1).isImmediate()) {
204 if (MI->getOperand(OpNo+1).isImm()) {
205205 int displ = int(MI->getOperand(OpNo+1).getImm());
206206 if (displ > 0)
207207 O << "+" << displ;
221221 }
222222
223223 void printSymbolHi(const MachineInstr *MI, unsigned OpNo) {
224 if (MI->getOperand(OpNo).isImmediate()) {
224 if (MI->getOperand(OpNo).isImm()) {
225225 printS16ImmOperand(MI, OpNo);
226226 } else {
227227 printOp(MI->getOperand(OpNo));
230230 }
231231
232232 void printSymbolLo(const MachineInstr *MI, unsigned OpNo) {
233 if (MI->getOperand(OpNo).isImmediate()) {
233 if (MI->getOperand(OpNo).isImm()) {
234234 printS16ImmOperand(MI, OpNo);
235235 } else {
236236 printOp(MI->getOperand(OpNo));
244244 }
245245
246246 void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
247 if (MI->getOperand(OpNo).isImmediate()) {
247 if (MI->getOperand(OpNo).isImm()) {
248248 int value = (int) MI->getOperand(OpNo).getImm();
249249 assert((value >= 0 && value < 16)
250250 && "Invalid negated immediate rotate 7-bit argument");
255255 }
256256
257257 void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
258 if (MI->getOperand(OpNo).isImmediate()) {
258 if (MI->getOperand(OpNo).isImm()) {
259259 int value = (int) MI->getOperand(OpNo).getImm();
260260 assert((value >= 0 && value < 32)
261261 && "Invalid negated immediate rotate 7-bit argument");
371371 default: return true; // Unknown modifier.
372372 case 'L': // Write second word of DImode reference.
373373 // Verify that this operand has two consecutive registers.
374 if (!MI->getOperand(OpNo).isRegister() ||
374 if (!MI->getOperand(OpNo).isReg() ||
375375 OpNo+1 == MI->getNumOperands() ||
376 !MI->getOperand(OpNo+1).isRegister())
376 !MI->getOperand(OpNo+1).isReg())
377377 return true;
378378 ++OpNo; // Return the high-part.
379379 break;
5959 case SPU::AHIr16:
6060 case SPU::AIvec:
6161 assert(MI.getNumOperands() == 3 &&
62 MI.getOperand(0).isRegister() &&
63 MI.getOperand(1).isRegister() &&
64 MI.getOperand(2).isImmediate() &&
62 MI.getOperand(0).isReg() &&
63 MI.getOperand(1).isReg() &&
64 MI.getOperand(2).isImm() &&
6565 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
6666 if (MI.getOperand(2).getImm() == 0) {
6767 sourceReg = MI.getOperand(1).getReg();
7272 case SPU::AIr32:
7373 assert(MI.getNumOperands() == 3 &&
7474 "wrong number of operands to AIr32");
75 if (MI.getOperand(0).isRegister() &&
76 (MI.getOperand(1).isRegister() ||
77 MI.getOperand(1).isFrameIndex()) &&
78 (MI.getOperand(2).isImmediate() &&
75 if (MI.getOperand(0).isReg() &&
76 (MI.getOperand(1).isReg() ||
77 MI.getOperand(1).isFI()) &&
78 (MI.getOperand(2).isImm() &&
7979 MI.getOperand(2).getImm() == 0)) {
8080 sourceReg = MI.getOperand(1).getReg();
8181 destReg = MI.getOperand(0).getReg();
102102 case SPU::ORf32:
103103 case SPU::ORf64:
104104 assert(MI.getNumOperands() == 3 &&
105 MI.getOperand(0).isRegister() &&
106 MI.getOperand(1).isRegister() &&
107 MI.getOperand(2).isRegister() &&
105 MI.getOperand(0).isReg() &&
106 MI.getOperand(1).isReg() &&
107 MI.getOperand(2).isReg() &&
108108 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
109109 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
110110 sourceReg = MI.getOperand(1).getReg();
135135 case SPU::LQXr64:
136136 case SPU::LQXr32:
137137 case SPU::LQXr16:
138 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
139 MI->getOperand(2).isFrameIndex()) {
138 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
139 MI->getOperand(2).isFI()) {
140140 FrameIndex = MI->getOperand(2).getIndex();
141141 return MI->getOperand(0).getReg();
142142 }
169169 case SPU::STQXr32:
170170 case SPU::STQXr16:
171171 // case SPU::STQXr8:
172 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
173 MI->getOperand(2).isFrameIndex()) {
172 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
173 MI->getOperand(2).isFI()) {
174174 FrameIndex = MI->getOperand(2).getIndex();
175175 return MI->getOperand(0).getReg();
176176 }
272272 cerr << "storeRegToAddr() invoked!\n";
273273 abort();
274274
275 if (Addr[0].isFrameIndex()) {
275 if (Addr[0].isFI()) {
276276 /* do what storeRegToStackSlot does here */
277277 } else {
278278 unsigned Opc = 0;
296296 .addReg(SrcReg, false, false, isKill);
297297 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
298298 MachineOperand &MO = Addr[i];
299 if (MO.isRegister())
299 if (MO.isReg())
300300 MIB.addReg(MO.getReg());
301 else if (MO.isImmediate())
301 else if (MO.isImm())
302302 MIB.addImm(MO.getImm());
303303 else
304304 MIB.addFrameIndex(MO.getIndex());
357357 cerr << "loadRegToAddr() invoked!\n";
358358 abort();
359359
360 if (Addr[0].isFrameIndex()) {
360 if (Addr[0].isFI()) {
361361 /* do what loadRegFromStackSlot does here... */
362362 } else {
363363 unsigned Opc = 0;
382382 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
383383 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
384384 MachineOperand &MO = Addr[i];
385 if (MO.isRegister())
385 if (MO.isReg())
386386 MIB.addReg(MO.getReg());
387 else if (MO.isImmediate())
387 else if (MO.isImm())
388388 MIB.addImm(MO.getImm());
389389 else
390390 MIB.addFrameIndex(MO.getIndex());
327327 MachineFunction &MF = *MBB.getParent();
328328 MachineFrameInfo *MFI = MF.getFrameInfo();
329329
330 while (!MI.getOperand(i).isFrameIndex()) {
330 while (!MI.getOperand(i).isFI()) {
331331 ++i;
332332 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
333333 }
9090 // pool entries aren't immediates at this stage, so we check here.
9191 // If it's an immediate, print it the old fashioned way. If it's
9292 // not, we print it as a constant pool index.
93 if(MI->getOperand(OpNo).isImmediate()) {
93 if (MI->getOperand(OpNo).isImm()) {
9494 O << (int64_t)MI->getOperand(OpNo).getImm();
9595 } else { // this is a constant pool reference: FIXME: assert this
9696 printOp(MI->getOperand(OpNo));
8383
8484 for(unsigned i=0; i < CurrentInsn->getNumOperands(); i++) {
8585 MachineOperand &MO=CurrentInsn->getOperand(i);
86 if(MO.isRegister()) {
86 if (MO.isReg()) {
8787 if(MO.isUse()) { // TODO: exclude p0
8888 CurrentReads.insert(MO.getReg());
8989 }
3030 if (oc == IA64::MOV || oc == IA64::FMOV) {
3131 // TODO: this doesn't detect predicate moves
3232 assert(MI.getNumOperands() >= 2 &&
33 /* MI.getOperand(0).isRegister() &&
34 MI.getOperand(1).isRegister() && */
33 /* MI.getOperand(0).isReg() &&
34 MI.getOperand(1).isReg() && */
3535 "invalid register-register move instruction");
36 if( MI.getOperand(0).isRegister() &&
37 MI.getOperand(1).isRegister() ) {
36 if (MI.getOperand(0).isReg() &&
37 MI.getOperand(1).isReg()) {
3838 // if both operands of the MOV/FMOV are registers, then
3939 // yes, this is a move instruction
4040 sourceReg = MI.getOperand(1).getReg();
121121 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
122122 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
123123 MachineOperand &MO = Addr[i];
124 if (MO.isRegister())
124 if (MO.isReg())
125125 MIB.addReg(MO.getReg());
126 else if (MO.isImmediate())
126 else if (MO.isImm())
127127 MIB.addImm(MO.getImm());
128128 else
129129 MIB.addFrameIndex(MO.getIndex());
173173 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
174174 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
175175 MachineOperand &MO = Addr[i];
176 if (MO.isRegister())
176 if (MO.isReg())
177177 MIB.addReg(MO.getReg());
178 else if (MO.isImmediate())
178 else if (MO.isImm())
179179 MIB.addImm(MO.getImm());
180180 else
181181 MIB.addFrameIndex(MO.getIndex());
120120
121121 bool FP = hasFP(MF);
122122
123 while (!MI.getOperand(i).isFrameIndex()) {
123 while (!MI.getOperand(i).isFI()) {
124124 ++i;
125125 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
126126 }
335335 // using PIC_. %call16 is used to load direct call targets
336336 // on PIC_ and small code size. %call_lo and %call_hi load
337337 // direct call targets on PIC_ and large code size.
338 if (MI->getOpcode() == Mips::LUi && !MO.isRegister()
339 && !MO.isImmediate()) {
338 if (MI->getOpcode() == Mips::LUi && !MO.isReg() && !MO.isImm()) {
340339 if ((isPIC) && (isCodeLarge))
341340 O << "%call_hi(";
342341 else
343342 O << "%hi(";
344343 closeP = true;
345 } else if ((MI->getOpcode() == Mips::ADDiu) && !MO.isRegister()
346 && !MO.isImmediate()) {
344 } else if ((MI->getOpcode() == Mips::ADDiu) && !MO.isReg() && !MO.isImm()) {
347345 const MachineOperand &firstMO = MI->getOperand(opNum-1);
348346 if (firstMO.getReg() == Mips::GP)
349347 O << "%gp_rel(";
350348 else
351349 O << "%lo(";
352350 closeP = true;
353 } else if ((isPIC) && (MI->getOpcode() == Mips::LW)
354 && (!MO.isRegister()) && (!MO.isImmediate())) {
351 } else if ((isPIC) && (MI->getOpcode() == Mips::LW) &&
352 (!MO.isReg()) && (!MO.isImm())) {
355353 const MachineOperand &firstMO = MI->getOperand(opNum-1);
356354 const MachineOperand &lastMO = MI->getOperand(opNum+1);
357 if ((firstMO.isRegister()) && (lastMO.isRegister())) {
355 if ((firstMO.isReg()) && (lastMO.isReg())) {
358356 if ((firstMO.getReg() == Mips::T9) && (lastMO.getReg() == Mips::GP)
359357 && (!isCodeLarge))
360358 O << "%call16(";
2323 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
2424
2525 static bool isZeroImm(const MachineOperand &op) {
26 return op.isImmediate() && op.getImm() == 0;
26 return op.isImm() && op.getImm() == 0;
2727 }
2828
2929 /// Return true if the instruction is a register to register move and
5959
6060 // addiu $dst, $src, 0
6161 if (MI.getOpcode() == Mips::ADDiu) {
62 if ((MI.getOperand(1).isRegister()) && (isZeroImm(MI.getOperand(2)))) {
62 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
6363 DstReg = MI.getOperand(0).getReg();
6464 SrcReg = MI.getOperand(1).getReg();
6565 return true;
7878 {
7979 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
8080 (MI->getOpcode() == Mips::LWC1A) || (MI->getOpcode() == Mips::LDC1)) {
81 if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
82 (MI->getOperand(1).isImmediate()) && // the imm is zero
81 if ((MI->getOperand(2).isFI()) && // is a stack slot
82 (MI->getOperand(1).isImm()) && // the imm is zero
8383 (isZeroImm(MI->getOperand(1)))) {
8484 FrameIndex = MI->getOperand(2).getIndex();
8585 return MI->getOperand(0).getReg();
9999 {
100100 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
101101 (MI->getOpcode() == Mips::SWC1A) || (MI->getOpcode() == Mips::SDC1)) {
102 if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
103 (MI->getOperand(1).isImmediate()) && // the imm is zero
102 if ((MI->getOperand(2).isFI()) && // is a stack slot
103 (MI->getOperand(1).isImm()) && // the imm is zero
104104 (isZeroImm(MI->getOperand(1)))) {
105105 FrameIndex = MI->getOperand(2).getIndex();
106106 return MI->getOperand(0).getReg();
216216 .addReg(SrcReg, false, false, isKill);
217217 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
218218 MachineOperand &MO = Addr[i];
219 if (MO.isRegister())
219 if (MO.isReg())
220220 MIB.addReg(MO.getReg());
221 else if (MO.isImmediate())
221 else if (MO.isImm())
222222 MIB.addImm(MO.getImm());
223223 else
224224 MIB.addFrameIndex(MO.getIndex());
266266 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
267267 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
268268 MachineOperand &MO = Addr[i];
269 if (MO.isRegister())
269 if (MO.isReg())
270270 MIB.addReg(MO.getReg());
271 else if (MO.isImmediate())
271 else if (MO.isImm())
272272 MIB.addImm(MO.getImm());
273273 else
274274 MIB.addFrameIndex(MO.getIndex());
288288
289289 switch (MI->getOpcode()) {
290290 case Mips::ADDu:
291 if ((MI->getOperand(0).isRegister()) &&
292 (MI->getOperand(1).isRegister()) &&
291 if ((MI->getOperand(0).isReg()) &&
292 (MI->getOperand(1).isReg()) &&
293293 (MI->getOperand(1).getReg() == Mips::ZERO) &&
294 (MI->getOperand(2).isRegister())) {
294 (MI->getOperand(2).isReg())) {
295295 if (Ops[0] == 0) { // COPY -> STORE
296296 unsigned SrcReg = MI->getOperand(2).getReg();
297297 bool isKill = MI->getOperand(2).isKill();
309309 case Mips::FMOV_SO32:
310310 case Mips::FMOV_AS32:
311311 case Mips::FMOV_D32:
312 if ((MI->getOperand(0).isRegister()) &&
313 (MI->getOperand(1).isRegister())) {
312 if ((MI->getOperand(0).isReg()) &&
313 (MI->getOperand(1).isReg())) {
314314 const TargetRegisterClass
315315 *RC = RI.getRegClass(MI->getOperand(0).getReg());
316316 unsigned StoreOpc, LoadOpc;
347347 MachineFunction &MF = *MI.getParent()->getParent();
348348
349349 unsigned i = 0;
350 while (!MI.getOperand(i).isFrameIndex()) {
350 while (!MI.getOperand(i).isFI()) {
351351 ++i;
352352 assert(i < MI.getNumOperands() &&
353353 "Instr doesn't have FrameIndex operand!");
287287 void PIC16AsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum)
288288 {
289289 const MachineOperand &MO = MI->getOperand(OpNum);
290 assert(MO.isImmediate() && "Not a valid so_imm value!");
290 assert(MO.isImm() && "Not a valid so_imm value!");
291291 printSOImm(O, MO.getImm(), TAI);
292292 }
293293
297297 const MachineOperand &MO1 = MI->getOperand(Op);
298298 const MachineOperand &MO2 = MI->getOperand(Op+1);
299299
300 if (MO2.isFrameIndex ()) {
300 if (MO2.isFI()) {
301301 printOperand(MI, Op+1);
302302 return;
303303 }
304304
305 if (!MO1.isRegister()) {
305 if (!MO1.isReg()) {
306306 // FIXME: This is for CP entries, but isn't right.
307307 printOperand(MI, Op);
308308 return;
309309 }
310310
311311 // If this is Stack Slot
312 if (MO1.isRegister()) {
312 if (MO1.isReg()) {
313313 if (strcmp(TM.getRegisterInfo()->get(MO1.getReg()).Name, "SP") == 0) {
314314 O << CurrentFnName <<"_"<< MO2.getImm();
315315 return;
2626 TM(tm), RI(*this) {}
2727
2828 static bool isZeroImm(const MachineOperand &op) {
29 return op.isImmediate() && op.getImm() == 0;
29 return op.isImm() && op.getImm() == 0;
3030 }
3131
3232
3939 isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
4040 {
4141 if (MI->getOpcode() == PIC16::MOVF) {
42 if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
43 (MI->getOperand(1).isImmediate()) && // the imm is zero
42 if ((MI->getOperand(2).isFI()) && // is a stack slot
43 (MI->getOperand(1).isImm()) && // the imm is zero
4444 (isZeroImm(MI->getOperand(1)))) {
4545 FrameIndex = MI->getOperand(2).getIndex();
4646 return MI->getOperand(0).getReg();
5959 isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
6060 {
6161 if (MI->getOpcode() == PIC16::MOVWF) {
62 if ((MI->getOperand(0).isFrameIndex()) && // is a stack slot
63 (MI->getOperand(1).isImmediate()) && // the imm is zero
62 if ((MI->getOperand(0).isFI()) && // is a stack slot
63 (MI->getOperand(1).isImm()) && // the imm is zero
6464 (isZeroImm(MI->getOperand(1)))) {
6565 FrameIndex = MI->getOperand(0).getIndex();
6666 return MI->getOperand(2).getReg();
140140 MachineFunction &MF = *MI.getParent()->getParent();
141141
142142 unsigned i = 0;
143 while (!MI.getOperand(i).isFrameIndex()) {
143 while (!MI.getOperand(i).isFI()) {
144144 ++i;
145145 assert(i < MI.getNumOperands() &&
146146 "Instr doesn't have FrameIndex operand!");
122122
123123 void printOperand(const MachineInstr *MI, unsigned OpNo) {
124124 const MachineOperand &MO = MI->getOperand(OpNo);
125 if (MO.isRegister()) {
125 if (MO.isReg()) {
126126 printRegister(MO, false);
127 } else if (MO.isImmediate()) {
127 } else if (MO.isImm()) {
128128 O << MO.getImm();
129129 } else {
130130 printOp(MO);
159159 O << (unsigned short)MI->getOperand(OpNo).getImm();
160160 }
161161 void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo) {
162 if (MI->getOperand(OpNo).isImmediate()) {
162 if (MI->getOperand(OpNo).isImm()) {
163163 O << (short)(MI->getOperand(OpNo).getImm()*4);
164164 } else {
165165 O << "lo16(";
173173 void printBranchOperand(const MachineInstr *MI, unsigned OpNo) {
174174 // Branches can take an immediate operand. This is used by the branch
175175 // selection pass to print $+8, an eight byte displacement from the PC.
176 if (MI->getOperand(OpNo).isImmediate()) {
176 if (MI->getOperand(OpNo).isImm()) {
177177 O << "$+" << MI->getOperand(OpNo).getImm()*4;
178178 } else {
179179 printOp(MI->getOperand(OpNo));
213213 O << "\"L" << getFunctionNumber() << "$pb\":";
214214 }
215215 void printSymbolHi(const MachineInstr *MI, unsigned OpNo) {
216 if (MI->getOperand(OpNo).isImmediate()) {
216 if (MI->getOperand(OpNo).isImm()) {
217217 printS16ImmOperand(MI, OpNo);
218218 } else {
219219 if (Subtarget.isDarwin()) O << "ha16(";
227227 }
228228 }
229229 void printSymbolLo(const MachineInstr *MI, unsigned OpNo) {
230 if (MI->getOperand(OpNo).isImmediate()) {
230 if (MI->getOperand(OpNo).isImm()) {
231231 printS16ImmOperand(MI, OpNo);
232232 } else {
233233 if (Subtarget.isDarwin()) O << "lo16(";
249249 void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
250250 printSymbolLo(MI, OpNo);
251251 O << '(';
252 if (MI->getOperand(OpNo+1).isRegister() &&
252 if (MI->getOperand(OpNo+1).isReg() &&
253253 MI->getOperand(OpNo+1).getReg() == PPC::R0)
254254 O << "0";
255255 else
257257 O << ')';
258258 }
259259 void printMemRegImmShifted(const MachineInstr *MI, unsigned OpNo) {
260 if (MI->getOperand(OpNo).isImmediate())
260 if (MI->getOperand(OpNo).isImm())
261261 printS16X4ImmOperand(MI, OpNo);
262262 else
263263 printSymbolLo(MI, OpNo);
264264 O << '(';
265 if (MI->getOperand(OpNo+1).isRegister() &&
265 if (MI->getOperand(OpNo+1).isReg() &&
266266 MI->getOperand(OpNo+1).getReg() == PPC::R0)
267267 O << "0";
268268 else
442442 return false;
443443 case 'L': // Write second word of DImode reference.
444444 // Verify that this operand has two consecutive registers.
445 if (!MI->getOperand(OpNo).isRegister() ||
445 if (!MI->getOperand(OpNo).isReg() ||
446446 OpNo+1 == MI->getNumOperands() ||
447 !MI->getOperand(OpNo+1).isRegister())
447 !MI->getOperand(OpNo+1).isReg())
448448 return true;
449449 ++OpNo; // Return the high-part.
450450 break;
451451 case 'I':
452452 // Write 'i' if an integer constant, otherwise nothing. Used to print
453453 // addi vs add, etc.
454 if (MI->getOperand(OpNo).isImmediate())
454 if (MI->getOperand(OpNo).isImm())
455455 O << "i";
456456 return false;
457457 }
466466 const char *ExtraCode) {
467467 if (ExtraCode && ExtraCode[0])
468468 return true; // Unknown modifier.
469 if (MI->getOperand(OpNo).isRegister())
469 if (MI->getOperand(OpNo).isReg())
470470 printMemRegReg(MI, OpNo);
471471 else
472472 printMemRegImm(MI, OpNo);
102102 unsigned MBBStartOffset = 0;
103103 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
104104 I != E; ++I) {
105 if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImmediate()) {
105 if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) {
106106 MBBStartOffset += TII->GetInstSizeInBytes(I);
107107 continue;
108108 }
125125
126126 unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
127127 // or things that get fixed up later by the JIT.
128 if (MO.isRegister()) {
128 if (MO.isReg()) {
129129 rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg());
130130
131131 // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
134134 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
135135 rv = 0x80 >> rv;
136136 }
137 } else if (MO.isImmediate()) {
137 } else if (MO.isImm()) {
138138 rv = MO.getImm();
139 } else if (MO.isGlobalAddress() || MO.isExternalSymbol() ||
140 MO.isConstantPoolIndex() || MO.isJumpTableIndex()) {
139 } else if (MO.isGlobal() || MO.isSymbol() ||
140 MO.isCPI() || MO.isJTI()) {
141141 unsigned Reloc = 0;
142142 if (MI.getOpcode() == PPC::BL_Macho || MI.getOpcode() == PPC::BL8_Macho ||
143143 MI.getOpcode() == PPC::BL_ELF || MI.getOpcode() == PPC::BL8_ELF ||
192192 }
193193
194194 MachineRelocation R;
195 if (MO.isGlobalAddress()) {
195 if (MO.isGlobal()) {
196196 R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
197197 MO.getGlobal(), 0,
198198 isa(MO.getGlobal()));
199 } else if (MO.isExternalSymbol()) {
199 } else if (MO.isSymbol()) {
200200 R = MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
201201 Reloc, MO.getSymbolName(), 0);
202 } else if (MO.isConstantPoolIndex()) {
202 } else if (MO.isCPI()) {
203203 R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
204204 Reloc, MO.getIndex(), 0);
205205 } else {
206 assert(MO.isJumpTableIndex());
206 assert(MO.isJTI());
207207 R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
208208 Reloc, MO.getIndex(), 0);
209209 }
219219 }
220220 MCE.addRelocation(R);
221221
222 } else if (MO.isMachineBasicBlock()) {
222 } else if (MO.isMBB()) {
223223 unsigned Reloc = 0;
224224 unsigned Opcode = MI.getOpcode();
225225 if (Opcode == PPC::B || Opcode == PPC::BL_Macho ||
4646 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
4747 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
4848 assert(MI.getNumOperands() >= 3 &&
49 MI.getOperand(0).isRegister() &&
50 MI.getOperand(1).isRegister() &&
51 MI.getOperand(2).isRegister() &&
49 MI.getOperand(0).isReg() &&
50 MI.getOperand(1).isReg() &&
51 MI.getOperand(2).isReg() &&
5252 "invalid PPC OR instruction!");
5353 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
5454 sourceReg = MI.getOperand(1).getReg();
5757 }
5858 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
5959 assert(MI.getNumOperands() >= 3 &&
60 MI.getOperand(0).isRegister() &&
61 MI.getOperand(2).isImmediate() &&
60 MI.getOperand(0).isReg() &&
61 MI.getOperand(2).isImm() &&
6262 "invalid PPC ADDI instruction!");
63 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
63 if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
6464 sourceReg = MI.getOperand(1).getReg();
6565 destReg = MI.getOperand(0).getReg();
6666 return true;
6767 }
6868 } else if (oc == PPC::ORI) { // ori r1, r2, 0
6969 assert(MI.getNumOperands() >= 3 &&
70 MI.getOperand(0).isRegister() &&
71 MI.getOperand(1).isRegister() &&
72 MI.getOperand(2).isImmediate() &&
70 MI.getOperand(0).isReg() &&
71 MI.getOperand(1).isReg() &&
72 MI.getOperand(2).isImm() &&
7373 "invalid PPC ORI instruction!");
7474 if (MI.getOperand(2).getImm() == 0) {
7575 sourceReg = MI.getOperand(1).getReg();
7979 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
8080 oc == PPC::FMRSD) { // fmr r1, r2
8181 assert(MI.getNumOperands() >= 2 &&
82 MI.getOperand(0).isRegister() &&
83 MI.getOperand(1).isRegister() &&
82 MI.getOperand(0).isReg() &&
83 MI.getOperand(1).isReg() &&
8484 "invalid PPC FMR instruction");
8585 sourceReg = MI.getOperand(1).getReg();
8686 destReg = MI.getOperand(0).getReg();
8787 return true;
8888 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
8989 assert(MI.getNumOperands() >= 2 &&
90 MI.getOperand(0).isRegister() &&
91 MI.getOperand(1).isRegister() &&
90 MI.getOperand(0).isReg() &&
91 MI.getOperand(1).isReg() &&
9292 "invalid PPC MCRF instruction");
9393 sourceReg = MI.getOperand(1).getReg();
9494 destReg = MI.getOperand(0).getReg();
105105 case PPC::LWZ:
106106 case PPC::LFS:
107107 case PPC::LFD:
108 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
109 MI->getOperand(2).isFrameIndex()) {
108 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
109 MI->getOperand(2).isFI()) {
110110 FrameIndex = MI->getOperand(2).getIndex();
111111 return MI->getOperand(0).getReg();
112112 }
123123 case PPC::STW:
124124 case PPC::STFS:
125125 case PPC::STFD:
126 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
127 MI->getOperand(2).isFrameIndex()) {
126 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
127 MI->getOperand(2).isFI()) {
128128 FrameIndex = MI->getOperand(2).getIndex();
129129 return MI->getOperand(0).getReg();
130130 }
477477 SmallVectorImpl &Addr,
478478 const TargetRegisterClass *RC,
479479 SmallVectorImpl &NewMIs) const{
480 if (Addr[0].isFrameIndex()) {
480 if (Addr[0].isFI()) {
481481 if (StoreRegToStackSlot(MF, SrcReg, isKill,
482482 Addr[0].getIndex(), RC, NewMIs)) {
483483 PPCFunctionInfo *FuncInfo = MF.getInfo();
506506 .addReg(SrcReg, false, false, isKill);
507507 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
508508 MachineOperand &MO = Addr[i];
509 if (MO.isRegister())
509 if (MO.isReg())
510510 MIB.addReg(MO.getReg());
511 else if (MO.isImmediate())
511 else if (MO.isImm())
512512 MIB.addImm(MO.getImm());
513513 else
514514 MIB.addFrameIndex(MO.getIndex());
616616 SmallVectorImpl &Addr,
617617 const TargetRegisterClass *RC,
618618 SmallVectorImpl &NewMIs)const{
619 if (Addr[0].isFrameIndex()) {
619 if (Addr[0].isFI()) {
620620 LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
621621 return;
622622 }
641641 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
642642 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
643643 MachineOperand &MO = Addr[i];
644 if (MO.isRegister())
644 if (MO.isReg())
645645 MIB.addReg(MO.getReg());
646 else if (MO.isImmediate())
646 else if (MO.isImm())
647647 MIB.addImm(MO.getImm());
648648 else
649649 MIB.addFrameIndex(MO.getIndex());
628628
629629 // Find out which operand is the frame index.
630630 unsigned FIOperandNo = 0;
631 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
631 while (!MI.getOperand(FIOperandNo).isFI()) {
632632 ++FIOperandNo;
633633 assert(FIOperandNo != MI.getNumOperands() &&
634634 "Instr doesn't have FrameIndex operand!");
12411241 if (UsesTCRet) {
12421242 int MaxTCRetDelta = FI->getTailCallSPDelta();
12431243 MachineOperand &StackAdjust = MBBI->getOperand(1);
1244 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
1244 assert(StackAdjust.isImm() && "Expecting immediate value.");
12451245 // Adjust stack pointer.
12461246 int StackAdj = StackAdjust.getImm();
12471247 int Delta = StackAdj - MaxTCRetDelta;
13671367 } else if (RetOpcode == PPC::TCRETURNri) {
13681368 MBBI = prior(MBB.end());
13691369 MachineOperand &JumpTarget = MBBI->getOperand(0);
1370 assert(JumpTarget.isRegister() && "Expecting register operand.");
1370 assert(JumpTarget.isReg() && "Expecting register operand.");
13711371 BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR));
13721372 } else if (RetOpcode == PPC::TCRETURNai) {
13731373 MBBI = prior(MBB.end());
13811381 } else if (RetOpcode == PPC::TCRETURNri8) {
13821382 MBBI = prior(MBB.end());
13831383 MachineOperand &JumpTarget = MBBI->getOperand(0);
1384 assert(JumpTarget.isRegister() && "Expecting register operand.");
1384 assert(JumpTarget.isReg() && "Expecting register operand.");
13851385 BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR8));
13861386 } else if (RetOpcode == PPC::TCRETURNai8) {
13871387 MBBI = prior(MBB.end());
140140 const MachineOperand &MO = MI->getOperand (opNum);
141141 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
142142 bool CloseParen = false;
143 if (MI->getOpcode() == SP::SETHIi && !MO.isRegister() && !MO.isImmediate()) {
143 if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) {
144144 O << "%hi(";
145145 CloseParen = true;
146 } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri)
147 && !MO.isRegister() && !MO.isImmediate()) {
146 } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri) &&
147 !MO.isReg() && !MO.isImm()) {
148148 O << "%lo(";
149149 CloseParen = true;
150150 }
189189 return;
190190 }
191191
192 if (MI->getOperand(opNum+1).isRegister() &&
192 if (MI->getOperand(opNum+1).isReg() &&
193193 MI->getOperand(opNum+1).getReg() == SP::G0)
194194 return; // don't print "+%g0"
195 if (MI->getOperand(opNum+1).isImmediate() &&
195 if (MI->getOperand(opNum+1).isImm() &&
196196 MI->getOperand(opNum+1).getImm() == 0)
197197 return; // don't print "+0"
198198
199199 O << "+";
200 if (MI->getOperand(opNum+1).isGlobalAddress() ||
201 MI->getOperand(opNum+1).isConstantPoolIndex()) {
200 if (MI->getOperand(opNum+1).isGlobal() ||
201 MI->getOperand(opNum+1).isCPI()) {
202202 O << "%lo(";
203203 printOperand(MI, opNum+1);
204204 O << ")";
2424 }
2525
2626 static bool isZeroImm(const MachineOperand &op) {
27 return op.isImmediate() && op.getImm() == 0;
27 return op.isImm() && op.getImm() == 0;
2828 }
2929
3030 /// Return true if the instruction is a register to register move and
4747 return true;
4848 }
4949 } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
50 isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
50 isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
5151 DstReg = MI.getOperand(0).getReg();
5252 SrcReg = MI.getOperand(1).getReg();
5353 return true;
7070 if (MI->getOpcode() == SP::LDri ||
7171 MI->getOpcode() == SP::LDFri ||
7272 MI->getOpcode() == SP::LDDFri) {
73 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
73 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
7474 MI->getOperand(2).getImm() == 0) {
7575 FrameIndex = MI->getOperand(1).getIndex();
7676 return MI->getOperand(0).getReg();
8989 if (MI->getOpcode() == SP::STri ||
9090 MI->getOpcode() == SP::STFri ||
9191 MI->getOpcode() == SP::STDFri) {
92 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
92 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
9393 MI->getOperand(1).getImm() == 0) {
9494 FrameIndex = MI->getOperand(0).getIndex();
9595 return MI->getOperand(2).getReg();
167167 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
168168 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
169169 MachineOperand &MO = Addr[i];
170 if (MO.isRegister())
170 if (MO.isReg())
171171 MIB.addReg(MO.getReg());
172 else if (MO.isImmediate())
172 else if (MO.isImm())
173173 MIB.addImm(MO.getImm());
174174 else {
175 assert(MO.isFrameIndex());
175 assert(MO.isFI());
176176 MIB.addFrameIndex(MO.getIndex());
177177 }
178178 }
211211 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
212212 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
213213 MachineOperand &MO = Addr[i];
214 if (MO.isRegister())
214 if (MO.isReg())
215215 MIB.addReg(MO.getReg());
216 else if (MO.isImmediate())
216 else if (MO.isImm())
217217 MIB.addImm(MO.getImm());
218218 else {
219 assert(MO.isFrameIndex());
219 assert(MO.isFI());
220220 MIB.addFrameIndex(MO.getIndex());
221221 }
222222 }
235235 MachineInstr *NewMI = NULL;
236236 switch (MI->getOpcode()) {
237237 case SP::ORrr:
238 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
239 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
238 if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
239 MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
240240 if (OpNum == 0) // COPY -> STORE
241241 NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0)
242242 .addReg(MI->getOperand(2).getReg());
7979
8080 unsigned i = 0;
8181 MachineInstr &MI = *II;
82 while (!MI.getOperand(i).isFrameIndex()) {
82 while (!MI.getOperand(i).isFI()) {
8383 ++i;
8484 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
8585 }
545545 const MachineOperand &DispSpec = MI->getOperand(Op+3);
546546
547547 bool NotRIPRel = IndexReg.getReg() || BaseReg.getReg();
548 if (DispSpec.isGlobalAddress() ||
549 DispSpec.isConstantPoolIndex() ||
550 DispSpec.isJumpTableIndex()) {
548 if (DispSpec.isGlobal() ||
549 DispSpec.isCPI() ||
550 DispSpec.isJTI()) {
551551 printOperand(MI, Op+3, "mem", NotRIPRel);
552552 } else {
553553 int DispVal = DispSpec.getImm();
674674 case 'w': // Print HImode register
675675 case 'k': // Print SImode register
676676 case 'q': // Print DImode register
677 if (MI->getOperand(OpNo).isRegister())
677 if (MI->getOperand(OpNo).isReg())
678678 return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
679679 printOperand(MI, OpNo);
680680 return false;
297297 NeedPlus = true;
298298 }
299299
300 if (DispSpec.isGlobalAddress() || DispSpec.isConstantPoolIndex() ||
301 DispSpec.isJumpTableIndex()) {
300 if (DispSpec.isGlobal() || DispSpec.isCPI() ||
301 DispSpec.isJTI()) {
302302 if (NeedPlus)
303303 O << " + ";
304304 printOp(DispSpec, "mem");
4343 void printOperand(const MachineInstr *MI, unsigned OpNo,
4444 const char *Modifier = 0) {
4545 const MachineOperand &MO = MI->getOperand(OpNo);
46 if (MO.isRegister()) {
46 if (MO.isReg()) {
4747 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
4848 "Not physreg??");
4949 O << TM.getRegisterInfo()->get(MO.getReg()).Name; // Capitalized names
267267
268268 // Otherwise, this is something that requires a relocation. Emit it as such
269269 // now.
270 if (RelocOp->isGlobalAddress()) {
270 if (RelocOp->isGlobal()) {
271271 // In 64-bit static small code model, we could potentially emit absolute.
272272 // But it's probably not beneficial.
273273 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
278278 bool isLazy = gvNeedsLazyPtr(RelocOp->getGlobal());
279279 emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
280280 PCAdj, NeedStub, isLazy);
281 } else if (RelocOp->isConstantPoolIndex()) {
281 } else if (RelocOp->isCPI()) {
282282 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
283283 emitConstPoolAddress(RelocOp->getIndex(), rt,
284284 RelocOp->getOffset(), PCAdj);
285 } else if (RelocOp->isJumpTableIndex()) {
285 } else if (RelocOp->isJTI()) {
286286 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
287287 emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
288288 } else {
298298 const MachineOperand *DispForReloc = 0;
299299
300300 // Figure out what sort of displacement we have to handle here.
301 if (Op3.isGlobalAddress()) {
301 if (Op3.isGlobal()) {
302302 DispForReloc = &Op3;
303 } else if (Op3.isConstantPoolIndex()) {
303 } else if (Op3.isCPI()) {
304304 if (Is64BitMode || IsPIC) {
305305 DispForReloc = &Op3;
306306 } else {
307307 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
308308 DispVal += Op3.getOffset();
309309 }
310 } else if (Op3.isJumpTableIndex()) {
310 } else if (Op3.isJTI()) {
311311 if (Is64BitMode || IsPIC) {
312312 DispForReloc = &Op3;
313313 } else {
521521 const MachineOperand &MO = MI.getOperand(CurOp++);
522522
523523 DOUT << "RawFrm CurOp " << CurOp << "\n";
524 DOUT << "isMachineBasicBlock " << MO.isMachineBasicBlock() << "\n";
525 DOUT << "isGlobalAddress " << MO.isGlobalAddress() << "\n";
526 DOUT << "isExternalSymbol " << MO.isExternalSymbol() << "\n";
527 DOUT << "isImmediate " << MO.isImmediate() << "\n";
528
529 if (MO.isMachineBasicBlock()) {
524 DOUT << "isMBB " << MO.isMBB() << "\n";
525 DOUT << "isGlobal " << MO.isGlobal() << "\n";
526 DOUT << "isSymbol " << MO.isSymbol() << "\n";
527 DOUT << "isImm " << MO.isImm() << "\n";
528
529 if (MO.isMBB()) {
530530 emitPCRelativeBlockAddress(MO.getMBB());
531 } else if (MO.isGlobalAddress()) {
531 } else if (MO.isGlobal()) {
532532 // Assume undefined functions may be outside the Small codespace.
533533 bool NeedStub =
534534 (Is64BitMode &&
537537 Opcode == X86::TAILJMPd;
538538 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
539539 0, 0, NeedStub);
540 } else if (MO.isExternalSymbol()) {
540 } else if (MO.isSymbol()) {
541541 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
542 } else if (MO.isImmediate()) {
542 } else if (MO.isImm()) {
543543 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
544544 } else {
545545 assert(0 && "Unknown RawFrm operand!");
553553 if (CurOp != NumOps) {
554554 const MachineOperand &MO1 = MI.getOperand(CurOp++);
555555 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
556 if (MO1.isImmediate())
556 if (MO1.isImm())
557557 emitConstant(MO1.getImm(), Size);
558558 else {
559559 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
561561 // This should not occur on Darwin for relocatable objects.
562562 if (Opcode == X86::MOV64ri)
563563 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
564 if (MO1.isGlobalAddress()) {
564 if (MO1.isGlobal()) {
565565 bool NeedStub = isa(MO1.getGlobal());
566566 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
567567 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
568568 NeedStub, isLazy);
569 } else if (MO1.isExternalSymbol())
569 } else if (MO1.isSymbol())
570570 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
571 else if (MO1.isConstantPoolIndex())
571 else if (MO1.isCPI())
572572 emitConstPoolAddress(MO1.getIndex(), rt);
573 else if (MO1.isJumpTableIndex())
573 else if (MO1.isJTI())
574574 emitJumpTableAddress(MO1.getIndex(), rt);
575575 }
576576 }
626626 if (CurOp != NumOps) {
627627 const MachineOperand &MO1 = MI.getOperand(CurOp++);
628628 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
629 if (MO1.isImmediate())
629 if (MO1.isImm())
630630 emitConstant(MO1.getImm(), Size);
631631 else {
632632 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
633633 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
634634 if (Opcode == X86::MOV64ri32)
635635 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
636 if (MO1.isGlobalAddress()) {
636 if (MO1.isGlobal()) {
637637 bool NeedStub = isa(MO1.getGlobal());
638638 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
639639 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
640640 NeedStub, isLazy);
641 } else if (MO1.isExternalSymbol())
641 } else if (MO1.isSymbol())
642642 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
643 else if (MO1.isConstantPoolIndex())
643 else if (MO1.isCPI())
644644 emitConstPoolAddress(MO1.getIndex(), rt);
645 else if (MO1.isJumpTableIndex())
645 else if (MO1.isJTI())
646646 emitJumpTableAddress(MO1.getIndex(), rt);
647647 }
648648 }
653653 case X86II::MRM4m: case X86II::MRM5m:
654654 case X86II::MRM6m: case X86II::MRM7m: {
655655 intptr_t PCAdj = (CurOp+4 != NumOps) ?
656 (MI.getOperand(CurOp+4).isImmediate() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
656 (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
657657
658658 MCE.emitByte(BaseOpcode);
659659 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
663663 if (CurOp != NumOps) {
664664 const MachineOperand &MO = MI.getOperand(CurOp++);
665665 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
666 if (MO.isImmediate())
666 if (MO.isImm())
667667 emitConstant(MO.getImm(), Size);
668668 else {
669669 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
670670 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
671671 if (Opcode == X86::MOV64mi32)
672672 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
673 if (MO.isGlobalAddress()) {
673 if (MO.isGlobal()) {
674674 bool NeedStub = isa(MO.getGlobal());
675675 bool isLazy = gvNeedsLazyPtr(MO.getGlobal());
676676 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
677677 NeedStub, isLazy);
678 } else if (MO.isExternalSymbol())
678 } else if (MO.isSymbol())
679679 emitExternalSymbolAddress(MO.getSymbolName(), rt);
680 else if (MO.isConstantPoolIndex())
680 else if (MO.isCPI())
681681 emitConstPoolAddress(MO.getIndex(), rt);
682 else if (MO.isJumpTableIndex())
682 else if (MO.isJTI())
683683 emitJumpTableAddress(MO.getIndex(), rt);
684684 }
685685 }
167167 /// getFPReg - Return the X86::FPx register number for the specified operand.
168168 /// For example, this returns 3 for X86::FP3.
169169 static unsigned getFPReg(const MachineOperand &MO) {
170 assert(MO.isRegister() && "Expected an FP register!");
170 assert(MO.isReg() && "Expected an FP register!");
171171 unsigned Reg = MO.getReg();
172172 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
173173 return Reg - X86::FP0;
239239 SmallVector DeadRegs;
240240 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
241241 const MachineOperand &MO = MI->getOperand(i);
242 if (MO.isRegister() && MO.isDead())
242 if (MO.isReg() && MO.isDead())
243243 DeadRegs.push_back(MO.getReg());
244244 }
245245
10201020 unsigned NumKills = 0;
10211021 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
10221022 MachineOperand &Op = MI->getOperand(i);
1023 if (!Op.isRegister() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1023 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
10241024 continue;
10251025 assert(Op.isUse() && "Only handle inline asm uses right now");
10261026
10601060
10611061 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
10621062 MachineOperand &Op = MI->getOperand(i);
1063 if (!Op.isRegister() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1063 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
10641064 continue;
10651065 // FP Register uses must be kills unless there are two uses of the same
10661066 // register, in which case only one will be a kill.
702702 bool ContainsFPCode = false;
703703 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
704704 !ContainsFPCode && I != E; ++I) {
705 if (I->getNumOperands() != 0 && I->getOperand(0).isRegister()) {
705 if (I->getNumOperands() != 0 && I->getOperand(0).isReg()) {
706706 const TargetRegisterClass *clas;
707707 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
708 if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
708 if (I->getOperand(op).isReg() && I->getOperand(op).isDef() &&
709709 TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
710710 ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) ==
711711 X86::RFP32RegisterClass ||
63846384 tt = t1;
63856385
63866386 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6387 assert((argOpers[valArgIndx]->isRegister() ||
6388 argOpers[valArgIndx]->isImmediate()) &&
6387 assert((argOpers[valArgIndx]->isReg() ||
6388 argOpers[valArgIndx]->isImm()) &&
63896389 "invalid operand");
6390 if (argOpers[valArgIndx]->isRegister())
6390 if (argOpers[valArgIndx]->isReg())
63916391 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
63926392 else
63936393 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
65066506 tt2 = t2;
65076507 }
65086508
6509 assert((argOpers[4]->isRegister() || argOpers[4]->isImmediate()) &&
6509 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) &&
65106510 "invalid operand");
65116511 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
65126512 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
6513 if (argOpers[4]->isRegister())
6513 if (argOpers[4]->isReg())
65146514 MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
65156515 else
65166516 MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
65176517 MIB.addReg(tt1);
65186518 (*MIB).addOperand(*argOpers[4]);
6519 assert(argOpers[5]->isRegister() == argOpers[4]->isRegister());
6520 assert(argOpers[5]->isImmediate() == argOpers[4]->isImmediate());
6521 if (argOpers[5]->isRegister())
6519 assert(argOpers[5]->isReg() == argOpers[4]->isReg());
6520 assert(argOpers[5]->isImm() == argOpers[4]->isImm());
6521 if (argOpers[5]->isReg())
65226522 MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
65236523 else
65246524 MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
66126612 (*MIB).addOperand(*argOpers[i]);
66136613
66146614 // We only support register and immediate values
6615 assert((argOpers[valArgIndx]->isRegister() ||
6616 argOpers[valArgIndx]->isImmediate()) &&
6615 assert((argOpers[valArgIndx]->isReg() ||
6616 argOpers[valArgIndx]->isImm()) &&
66176617 "invalid operand");
66186618
66196619 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6620 if (argOpers[valArgIndx]->isRegister())
6620 if (argOpers[valArgIndx]->isReg())
66216621 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
66226622 else
66236623 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
67656765
67666766 X86AddressMode AM;
67676767 MachineOperand &Op = MI->getOperand(0);
6768 if (Op.isRegister()) {
6768 if (Op.isReg()) {
67696769 AM.BaseType = X86AddressMode::RegBase;
67706770 AM.Base.Reg = Op.getReg();
67716771 } else {
67736773 AM.Base.FrameIndex = Op.getIndex();
67746774 }
67756775 Op = MI->getOperand(1);
6776 if (Op.isImmediate())
6776 if (Op.isImm())
67776777 AM.Scale = Op.getImm();
67786778 Op = MI->getOperand(2);
6779 if (Op.isImmediate())
6779 if (Op.isImm())
67806780 AM.IndexReg = Op.getImm();
67816781 Op = MI->getOperand(3);
6782 if (Op.isGlobalAddress()) {
6782 if (Op.isGlobal()) {
67836783 AM.GV = Op.getGlobal();
67846784 } else {
67856785 AM.Disp = Op.getImm();
678678 case X86::MMX_MOVD64rr:
679679 case X86::MMX_MOVQ64rr:
680680 assert(MI.getNumOperands() >= 2 &&
681 MI.getOperand(0).isRegister() &&
682 MI.getOperand(1).isRegister() &&
681 MI.getOperand(0).isReg() &&
682 MI.getOperand(1).isReg() &&
683683 "invalid register-register move instruction");
684684 sourceReg = MI.getOperand(1).getReg();
685685 destReg = MI.getOperand(0).getReg();
704704 case X86::MOVAPDrm:
705705 case X86::MMX_MOVD64rm:
706706 case X86::MMX_MOVQ64rm:
707 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
708 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
707 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
708 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
709709 MI->getOperand(2).getImm() == 1 &&
710710 MI->getOperand(3).getReg() == 0 &&
711711 MI->getOperand(4).getImm() == 0) {
735735 case X86::MMX_MOVD64mr:
736736 case X86::MMX_MOVQ64mr:
737737 case X86::MMX_MOVNTQmr:
738 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
739 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
738 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
739 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
740740 MI->getOperand(1).getImm() == 1 &&
741741 MI->getOperand(2).getReg() == 0 &&
742742 MI->getOperand(3).getImm() == 0) {
788788 case X86::MMX_MOVD64rm:
789789 case X86::MMX_MOVQ64rm: {
790790 // Loads from constant pools are trivially rematerializable.
791 if (MI->getOperand(1).isRegister() &&
792 MI->getOperand(2).isImmediate() &&
793 MI->getOperand(3).isRegister() && MI->getOperand(3).getReg() == 0 &&
794 (MI->getOperand(4).isConstantPoolIndex() ||
795 (MI->getOperand(4).isGlobalAddress() &&
791 if (MI->getOperand(1).isReg() &&
792 MI->getOperand(2).isImm() &&
793 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
794 (MI->getOperand(4).isCPI() ||
795 (MI->getOperand(4).isGlobal() &&
796796 isGVStub(MI->getOperand(4).getGlobal(), TM)))) {
797797 unsigned BaseReg = MI->getOperand(1).getReg();
798798 if (BaseReg == 0)
799799 return true;
800800 // Allow re-materialization of PIC load.
801 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobalAddress())
801 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
802802 return false;
803803 const MachineFunction &MF = *MI->getParent()->getParent();
804804 const MachineRegisterInfo &MRI = MF.getRegInfo();
818818
819819 case X86::LEA32r:
820820 case X86::LEA64r: {
821 if (MI->getOperand(2).isImmediate() &&
822 MI->getOperand(3).isRegister() && MI->getOperand(3).getReg() == 0 &&
823 !MI->getOperand(4).isRegister()) {
821 if (MI->getOperand(2).isImm() &&
822 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
823 !MI->getOperand(4).isReg()) {
824824 // lea fi#, lea GV, etc. are all rematerializable.
825 if (!MI->getOperand(1).isRegister())
825 if (!MI->getOperand(1).isReg())
826826 return true;
827827 unsigned BaseReg = MI->getOperand(1).getReg();
828828 if (BaseReg == 0)
856856 bool SeenDef = false;
857857 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
858858 MachineOperand &MO = I->getOperand(j);