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TableGen: use PrintMethods to print more aliases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208607 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 6 years ago
38 changed file(s) with 474 addition(s) and 319 deletion(s). Raw diff Collapse all Expand all
15861586
15871587 def inv_cond_code_op : Operand {
15881588 let ParserMatchClass = inv_cond_code_op_asmoperand;
1589 let PrintMethod = "printInverseCondCodeOperand";
15891590 }
15901591
15911592 // Having a separate operand for the selectable use-case is debatable, but gives
38633864 Sched<[WriteALU, ReadALU]>;
38643865 }
38653866
3866
38673867 def : InstAlias<"tst $Rn, $Imm",
38683868 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>;
38693869 def : InstAlias<"tst $Rn, $Imm",
38703870 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>;
3871 // FIXME: these sometimes are canonical.
38713872 def : InstAlias<"mov $Rd, $Imm",
3872 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>;
3873 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm), 0>;
38733874 def : InstAlias<"mov $Rd, $Imm",
3874 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>;
3875 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm), 0>;
38753876
38763877 //===----------------------------------------------------------------------===//
38773878 // Logical (shifted register) instructions
207207 const MCOperand &MO = MI->getOperand(OpNum);
208208
209209 O << A64CondCodeToString(static_cast(MO.getImm()));
210 }
211
212 void
213 AArch64InstPrinter::printInverseCondCodeOperand(const MCInst *MI,
214 unsigned OpNum,
215 raw_ostream &O) {
216 A64CC::CondCodes CC =
217 static_cast(MI->getOperand(OpNum).getImm());
218 O << A64CondCodeToString(A64InvertCondCode(CC));
210219 }
211220
212221 template void
3030 // Autogenerated by tblgen
3131 void printInstruction(const MCInst *MI, raw_ostream &O);
3232 bool printAliasInstr(const MCInst *MI, raw_ostream &O);
33 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
34 unsigned PrintMethodIdx, raw_ostream &O);
3335 static const char *getRegisterName(unsigned RegNo);
3436 static const char *getInstructionName(unsigned Opcode);
3537
6163
6264 void printCondCodeOperand(const MCInst *MI, unsigned OpNum,
6365 raw_ostream &O);
66 void printInverseCondCodeOperand(const MCInst *MI, unsigned OpNum,
67 raw_ostream &O);
6468
6569 void printCRxOperand(const MCInst *MI, unsigned OpNum,
6670 raw_ostream &O);
19011901 // 4-bit immediate. Pretty-printed as
19021902 def ccode : Operand {
19031903 let PrintMethod = "printCondCode";
1904 }
1905
1906 def inv_ccode : Operand {
1907 let PrintMethod = "printInverseCondCode";
19041908 }
19051909
19061910 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
55705574 : BaseSIMDMov
55715575 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
55725576
5577 // FIXME: these aliases should be canonical, but TableGen can't handle the
5578 // alternate syntaxes.
55735579 class SIMDMovAlias
55745580 RegisterClass regtype, Operand idxtype>
55755581 : InstAlias
55765582 "|" # size # "\t$dst, $src$idx}",
5577 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
5583 (inst regtype:$dst, V128:$src, idxtype:$idx), 0>;
55785584
55795585 multiclass SMov {
55805586 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
56585664 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
56595665 idxtype:$idx))]>;
56605666
5667 // FIXME: the MOVs should be canonical, but TableGen's alias printing can't cope
5668 // with syntax variants.
56615669 class SIMDInsMainMovAlias
56625670 RegisterClass regtype, Operand idxtype>
56635671 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
56645672 "|" # size #"\t$dst$idx, $src}",
5665 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
5673 (inst V128:$dst, idxtype:$idx, regtype:$src), 0>;
56665674 class SIMDInsElementMovAlias
56675675 Operand idxtype>
56685676 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
56695677 # "|" # size #" $dst$idx, $src$idx2}",
5670 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
5678 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2), 0>;
56715679
56725680
56735681 multiclass SIMDIns {
59085916 RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
59095917 : InstAlias
59105918 # "|\t$dst, $src$index}",
5911 (inst regtype:$dst, vectype:$src, idxtype:$index)>;
5919 (inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
59125920
59135921
59145922 multiclass SIMDScalarCPY {
553553 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
554554 }
555555
556 // FIXME: TableGen can very nearly handle printing all of these, we should make
557 // it work properly.
556558 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
557559 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
558560 def : InstAlias<"neg $dst, $src, $shift",
672674 defm EOR : LogicalImm<0b10, "eor", xor>;
673675 defm ORR : LogicalImm<0b01, "orr", or>;
674676
677 // FIXME: these aliases *are* canonical sometimes (when movz can't be
678 // used). Actually, it seems to be working right now, but putting logical_immXX
679 // here is a bit dodgy on the AsmParser side too.
675680 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
676 logical_imm32:$imm)>;
681 logical_imm32:$imm), 0>;
677682 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
678 logical_imm64:$imm)>;
683 logical_imm64:$imm), 0>;
679684
680685
681686 // (register)
921926 // The inverse of the condition code from the alias instruction is what is used
922927 // in the aliased instruction. The parser all ready inverts the condition code
923928 // for these aliases.
924 // FIXME: Is this the correct way to handle these aliases?
925 def : InstAlias<"cset $dst, $cc", (CSINCWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
926 def : InstAlias<"cset $dst, $cc", (CSINCXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
927
928 def : InstAlias<"csetm $dst, $cc", (CSINVWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
929 def : InstAlias<"csetm $dst, $cc", (CSINVXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
929 def : InstAlias<"cset $dst, $cc",
930 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
931 def : InstAlias<"cset $dst, $cc",
932 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
933
934 def : InstAlias<"csetm $dst, $cc",
935 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
936 def : InstAlias<"csetm $dst, $cc",
937 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
930938
931939 def : InstAlias<"cinc $dst, $src, $cc",
932 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
940 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
933941 def : InstAlias<"cinc $dst, $src, $cc",
934 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
942 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
935943
936944 def : InstAlias<"cinv $dst, $src, $cc",
937 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
945 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
938946 def : InstAlias<"cinv $dst, $src, $cc",
939 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
947 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
940948
941949 def : InstAlias<"cneg $dst, $src, $cc",
942 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
950 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
943951 def : InstAlias<"cneg $dst, $src, $cc",
944 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
952 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
945953
946954 //===----------------------------------------------------------------------===//
947955 // PC-relative instructions.
37273735 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
37283736 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
37293737
3730 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3731 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3732 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3733 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3738 // FIXME: these should be canonical but the TableGen alias printer can't cope
3739 // with syntax variants.
3740 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3741 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3742 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3743 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
37343744
37353745 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
37363746 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
37673777 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
37683778 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
37693779
3770 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3771 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3772 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3773 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3780 // FIXME: these should be canonical, but TableGen can't do aliases & syntax
3781 // variants together.
3782 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3783 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3784 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3785 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
37743786
37753787 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
37763788 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
169169 // GPR register classes for post increment amount of vector load/store that
170170 // has alternate printing when Rm=31 and prints a constant immediate value
171171 // equal to the total number of bytes transferred.
172
173 // FIXME: TableGen *should* be able to do these itself now. There appears to be
174 // a bug in counting how many operands a Post-indexed MCInst should have which
175 // means the aliases don't trigger.
172176 def GPR64pi1 : RegisterOperand">;
173177 def GPR64pi2 : RegisterOperand">;
174178 def GPR64pi3 : RegisterOperand">;
220220 return;
221221 }
222222
223 // ANDS WZR, Wn, #imm ==> TST Wn, #imm
224 // ANDS XZR, Xn, #imm ==> TST Xn, #imm
225 if (Opcode == ARM64::ANDSWri && MI->getOperand(0).getReg() == ARM64::WZR) {
226 O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
227 printLogicalImm32(MI, 2, O);
228 return;
229 }
230 if (Opcode == ARM64::ANDSXri && MI->getOperand(0).getReg() == ARM64::XZR) {
231 O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
232 printLogicalImm64(MI, 2, O);
233 return;
234 }
223 // FIXME: TableGen should be able to do all of these now.
224
235225 // ANDS WZR, Wn, Wm{, lshift #imm} ==> TST Wn{, lshift #imm}
236226 // ANDS XZR, Xn, Xm{, lshift #imm} ==> TST Xn{, lshift #imm}
237227 if ((Opcode == ARM64::ANDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
11651155 O << ARM64CC::getCondCodeName(CC);
11661156 }
11671157
1158 void ARM64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1159 raw_ostream &O) {
1160 ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
1161 O << ARM64CC::getCondCodeName(ARM64CC::getInvertedCondCode(CC));
1162 }
1163
11681164 void ARM64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
11691165 raw_ostream &O) {
11701166 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
3333 // Autogenerated by tblgen.
3434 virtual void printInstruction(const MCInst *MI, raw_ostream &O);
3535 virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
36 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
37 unsigned PrintMethodIdx, raw_ostream &O);
3638 virtual StringRef getRegName(unsigned RegNo) const {
3739 return getRegisterName(RegNo);
3840 }
6163 void printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
6264 void printExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O);
6365 void printCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
66 void printInverseCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
6467 void printDotCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
6568 void printAlignedLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
6669 void printAMIndexed(const MCInst *MI, unsigned OpNum, unsigned Scale,
131134
132135 void printInstruction(const MCInst *MI, raw_ostream &O) override;
133136 bool printAliasInstr(const MCInst *MI, raw_ostream &O) override;
137 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
138 unsigned PrintMethodIdx, raw_ostream &O);
134139 StringRef getRegName(unsigned RegNo) const override {
135140 return getRegisterName(RegNo);
136141 }
8888 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
8989
9090 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
91 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
92 unsigned PrintMethodIdx, raw_ostream &O);
9193
9294 private:
9395 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
12831283 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
12841284 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
12851285
1286 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
12861287 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1287 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
12881288 def : MipsInstAlias<"ei", (EI ZERO), 1>;
12891289 def : MipsInstAlias<"di", (DI ZERO), 1>;
12901290
3737 // Autogenerated by tblgen.
3838 void printInstruction(const MCInst *MI, raw_ostream &O);
3939 bool printAliasInstr(const MCInst *MI, raw_ostream &O);
40 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
41 unsigned PrintMethodIdx, raw_ostream &O);
4042 static const char *getRegisterName(unsigned RegNo);
4143
4244 void printOperand(const MCInst *MI, int opNum, raw_ostream &OS);
3131 // Autogenerated by tblgen, returns true if we successfully printed an
3232 // alias.
3333 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
35 unsigned PrintMethodIdx, raw_ostream &O);
3436
3537 // Autogenerated by tblgen.
3638 void printInstruction(const MCInst *MI, raw_ostream &OS);
None ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
1 ; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s
0 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
1 ; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
22
33 @var32 = global i32 0
44 @var64 = global i64 0
3535 %shift4a = shl i32 %lhs4a, 15
3636 %val4a = sub i32 0, %shift4a
3737 store volatile i32 %val4a, i32* @var32
38 ; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsl #15
38 ; CHECK-AARCH64: neg {{w[0-9]+}}, {{w[0-9]+}}, lsl #15
39 ; CHECK-ARM64: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsl #15
3940
4041 %rhs5 = load volatile i64* @var64
4142 %shift5 = shl i64 %rhs5, 18
6667 %shift8a = shl i64 %lhs8a, 60
6768 %val8a = sub i64 0, %shift8a
6869 store volatile i64 %val8a, i64* @var64
69 ; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsl #60
70 ; CHECK-AARCH64: neg {{x[0-9]+}}, {{x[0-9]+}}, lsl #60
71 ; CHECK-ARM64: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsl #60
7072
7173 ret void
7274 ; CHECK: ret
99101 %shift4a = lshr i32 %lhs32, 15
100102 %val4a = sub i32 0, %shift4a
101103 store volatile i32 %val4a, i32* @var32
102 ; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsr #15
104 ; CHECK-AARCH64: neg {{w[0-9]+}}, {{w[0-9]+}}, lsr #15
105 ; CHECK-ARM64: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsr #15
103106
104107 %shift5 = lshr i64 %rhs64, 18
105108 %val5 = add i64 %lhs64, %shift5
125128 %shift8a = lshr i64 %lhs64, 45
126129 %val8a = sub i64 0, %shift8a
127130 store volatile i64 %val8a, i64* @var64
128 ; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsr #45
131 ; CHECK-AARCH64: neg {{x[0-9]+}}, {{x[0-9]+}}, lsr #45
132 ; CHECK-ARM64: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsr #45
129133
130134 ret void
131135 ; CHECK: ret
158162 %shift4a = ashr i32 %lhs32, 15
159163 %val4a = sub i32 0, %shift4a
160164 store volatile i32 %val4a, i32* @var32
161 ; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, asr #15
165 ; CHECK-AARCH64: neg {{w[0-9]+}}, {{w[0-9]+}}, asr #15
166 ; CHECK-ARM64: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, asr #15
162167
163168 %shift5 = ashr i64 %rhs64, 18
164169 %val5 = add i64 %lhs64, %shift5
184189 %shift8a = ashr i64 %lhs64, 45
185190 %val8a = sub i64 0, %shift8a
186191 store volatile i64 %val8a, i64* @var64
187 ; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, asr #45
192 ; CHECK-AARCH64: neg {{x[0-9]+}}, {{x[0-9]+}}, asr #45
193 ; CHECK-ARM64: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, asr #45
188194
189195 ret void
190196 ; CHECK: ret
245251 br i1 %tst1, label %t2, label %end
246252 ; Important that this isn't lowered to a cmn instruction because if %rhs32 ==
247253 ; 0 then the results will differ.
248 ; CHECK: sub [[RHS:w[0-9]+]], wzr, {{w[0-9]+}}, lsl #13
254 ; CHECK-AARCH64: neg [[RHS:w[0-9]+]], {{w[0-9]+}}, lsl #13
255 ; CHECK-ARM64: sub [[RHS:w[0-9]+]], wzr, {{w[0-9]+}}, lsl #13
249256 ; CHECK: cmp {{w[0-9]+}}, [[RHS]]
250257
251258 t2:
268275 %tst4 = icmp slt i64 %lhs64, %val4
269276 br i1 %tst4, label %t5, label %end
270277 ; Again, it's important that cmn isn't used here in case %rhs64 == 0.
271 ; CHECK: sub [[RHS:x[0-9]+]], xzr, {{x[0-9]+}}, lsl #43
278 ; CHECK-AARCH64: neg [[RHS:x[0-9]+]], {{x[0-9]+}}, lsl #43
279 ; CHECK-ARM64: sub [[RHS:x[0-9]+]], xzr, {{x[0-9]+}}, lsl #43
272280 ; CHECK: cmp {{x[0-9]+}}, [[RHS]]
273281
274282 t5:
186186 %val1 = zext i1 %tst1 to i32
187187 store i32 %val1, i32* @var32
188188 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
189 ; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ne
189 ; CHECK: cset {{w[0-9]+}}, eq
190190
191191 %rhs64 = sext i32 %rhs to i64
192192 %tst2 = icmp ule i64 %lhs64, %rhs64
193193 %val2 = zext i1 %tst2 to i64
194194 store i64 %val2, i64* @var64
195 ; CHECK: csinc {{w[0-9]+}}, wzr, wzr, hi
195 ; CHECK: cset {{w[0-9]+}}, ls
196196
197197 ret void
198198 ; CHECK: ret
205205 %val1 = sext i1 %tst1 to i32
206206 store i32 %val1, i32* @var32
207207 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
208 ; CHECK: csinv {{w[0-9]+}}, wzr, wzr, ne
208 ; CHECK: csetm {{w[0-9]+}}, eq
209209
210210 %rhs64 = sext i32 %rhs to i64
211211 %tst2 = icmp ule i64 %lhs64, %rhs64
212212 %val2 = sext i1 %tst2 to i64
213213 store i64 %val2, i64* @var64
214 ; CHECK: csinv {{x[0-9]+}}, xzr, xzr, hi
215
216 ret void
217 ; CHECK: ret
218 }
214 ; CHECK: csetm {{x[0-9]+}}, ls
215
216 ret void
217 ; CHECK: ret
218 }
6262 ; CHECK: test_setcc_float
6363 %val = fcmp oeq float %lhs, %rhs
6464 ; CHECK: fcmp s0, s1
65 ; CHECK: csinc w0, wzr, wzr, ne
65 ; CHECK: cset w0, eq
6666 ; CHECK-NOFP-NOT: fcmp
6767 ret i1 %val
6868 }
7171 ; CHECK: test_setcc_double
7272 %val = fcmp oeq double %lhs, %rhs
7373 ; CHECK: fcmp d0, d1
74 ; CHECK: csinc w0, wzr, wzr, ne
74 ; CHECK: cset w0, eq
7575 ; CHECK-NOFP-NOT: fcmp
7676 ret i1 %val
7777 }
8080 ; CHECK: test_setcc_i32
8181 %val = icmp ugt i32 %lhs, %rhs
8282 ; CHECK: cmp w0, w1
83 ; CHECK: csinc w0, wzr, wzr, ls
83 ; CHECK: cset w0, hi
8484 ret i1 %val
8585 }
8686
8888 ; CHECK: test_setcc_i64
8989 %val = icmp ne i64 %lhs, %rhs
9090 ; CHECK: cmp x0, x1
91 ; CHECK: csinc w0, wzr, wzr, eq
91 ; CHECK: cset w0, ne
9292 ret i1 %val
9393 }
55 %left = shl i64 %in, 19
66 %right = lshr i64 %in, 45
77 %val5 = or i64 %left, %right
8 ; CHECK: extr {{x[0-9]+}}, x0, x0, #45
8 ; CHECK: ror {{x[0-9]+}}, x0, #45
99 ret i64 %val5
1010 }
1111
1414 %left = shl i32 %in, 9
1515 %right = lshr i32 %in, 23
1616 %val5 = or i32 %left, %right
17 ; CHECK: extr {{w[0-9]+}}, w0, w0, #23
17 ; CHECK: ror {{w[0-9]+}}, w0, #23
1818 ret i32 %val5
1919 }
2020
1515 ; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
1616
1717 %val = zext i1 %test to i32
18 ; CHECK: csinc {{[xw][0-9]+}}, {{xzr|wzr}}, {{xzr|wzr}}, eq
18 ; CHECK: cset {{[xw][0-9]+}}, ne
1919
2020 store i32 %val, i32* @var
2121
132132 %val = fcmp ole fp128 %lhs, %rhs
133133 ; CHECK: bl __letf2
134134 ; CHECK: cmp w0, #0
135 ; CHECK: csinc w0, wzr, wzr, gt
135 ; CHECK: cset w0, le
136136
137137 ret i1 %val
138138 ; CHECK: ret
151151 %val = fcmp ugt fp128 %lhs, %rhs
152152 ; CHECK: bl __gttf2
153153 ; CHECK: cmp w0, #0
154 ; CHECK: csinc [[GT:w[0-9]+]], wzr, wzr, le
154 ; CHECK: cset [[GT:w[0-9]+]], gt
155155
156156 ; CHECK: bl __unordtf2
157157 ; CHECK: cmp w0, #0
158 ; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
158 ; CHECK: cset [[UNORDERED:w[0-9]+]], ne
159159
160160 ; CHECK: orr w0, [[UNORDERED]], [[GT]]
161161
175175 %cond = fcmp olt fp128 %lhs, %rhs
176176 ; CHECK: bl __getf2
177177 ; CHECK: cmp w0, #0
178 ; CHECK: csinc [[OGE:w[0-9]+]], wzr, wzr, lt
178 ; CHECK: cset [[OGE:w[0-9]+]], ge
179179
180180 ; CHECK: bl __unordtf2
181181 ; CHECK: cmp w0, #0
182 ; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
182 ; CHECK: cset [[UNORDERED:w[0-9]+]], ne
183183
184184 ; CHECK: orr [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]]
185185 ; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]]
33 ; CHECK-LABEL: test_select_cc_v8i8_i8:
44 ; CHECK: and w0, w0, #0xff
55 ; CHECK-NEXT: cmp w0, w1, uxtb
6 ; CHECK-NEXT: csinv w0, wzr, wzr, ne
6 ; CHECK-NEXT: csetm w0, eq
77 ; CHECK-NEXT: dup v{{[0-9]+}}.8b, w0
88 ; CHECK-NEXT: bsl v{{[0-9]+}}.8b, v0.8b, v1.8b
99 %cmp31 = icmp eq i8 %a, %b
3434 ; CHECK-LABEL: test_select_cc_v16i8_i8:
3535 ; CHECK: and w0, w0, #0xff
3636 ; CHECK-NEXT: cmp w0, w1, uxtb
37 ; CHECK-NEXT: csinv w0, wzr, wzr, ne
37 ; CHECK-NEXT: csetm w0, eq
3838 ; CHECK-NEXT: dup v{{[0-9]+}}.16b, w0
3939 ; CHECK-NEXT: bsl v{{[0-9]+}}.16b, v0.16b, v1.16b
4040 %cmp31 = icmp eq i8 %a, %b
6666 ; CHECK-LABEL: test_select_cc_v4i16:
6767 ; CHECK: and w0, w0, #0xffff
6868 ; CHECK-NEXT: cmp w0, w1, uxth
69 ; CHECK-NEXT: csinv w0, wzr, wzr, ne
69 ; CHECK-NEXT: csetm w0, eq
7070 ; CHECK-NEXT: dup v{{[0-9]+}}.4h, w0
7171 ; CHECK-NEXT: bsl v{{[0-9]+}}.8b, v0.8b, v1.8b
7272 %cmp31 = icmp eq i16 %a, %b
7878 ; CHECK-LABEL: test_select_cc_v8i16:
7979 ; CHECK: and w0, w0, #0xffff
8080 ; CHECK-NEXT: cmp w0, w1, uxth
81 ; CHECK-NEXT: csinv w0, wzr, wzr, ne
81 ; CHECK-NEXT: csetm w0, eq
8282 ; CHECK-NEXT: dup v{{[0-9]+}}.8h, w0
8383 ; CHECK-NEXT: bsl v{{[0-9]+}}.16b, v0.16b, v1.16b
8484 %cmp31 = icmp eq i16 %a, %b
8989 define <2x i32> @test_select_cc_v2i32(i32 %a, i32 %b, <2x i32> %c, <2x i32> %d ) {
9090 ; CHECK-LABEL: test_select_cc_v2i32:
9191 ; CHECK: cmp w0, w1, uxtw
92 ; CHECK-NEXT: csinv w0, wzr, wzr, ne
92 ; CHECK-NEXT: csetm w0, eq
9393 ; CHECK-NEXT: dup v{{[0-9]+}}.2s, w0
9494 ; CHECK-NEXT: bsl v{{[0-9]+}}.8b, v0.8b, v1.8b
9595 %cmp31 = icmp eq i32 %a, %b
100100 define <4x i32> @test_select_cc_v4i32(i32 %a, i32 %b, <4x i32> %c, <4x i32> %d ) {
101101 ; CHECK-LABEL: test_select_cc_v4i32:
102102 ; CHECK: cmp w0, w1, uxtw
103 ; CHECK-NEXT: csinv w0, wzr, wzr, ne
103 ; CHECK-NEXT: csetm w0, eq
104104 ; CHECK-NEXT: dup v{{[0-9]+}}.4s, w0
105105 ; CHECK-NEXT: bsl v{{[0-9]+}}.16b, v0.16b, v1.16b
106106 %cmp31 = icmp eq i32 %a, %b
111111 define <1x i64> @test_select_cc_v1i64(i64 %a, i64 %b, <1x i64> %c, <1x i64> %d ) {
112112 ; CHECK-LABEL: test_select_cc_v1i64:
113113 ; CHECK: cmp x0, x1
114 ; CHECK-NEXT: csinv x0, xzr, xzr, ne
114 ; CHECK-NEXT: csetm x0, eq
115115 ; CHECK-NEXT: fmov d{{[0-9]+}}, x0
116116 ; CHECK-NEXT: bsl v{{[0-9]+}}.8b, v0.8b, v1.8b
117117 %cmp31 = icmp eq i64 %a, %b
122122 define <2x i64> @test_select_cc_v2i64(i64 %a, i64 %b, <2x i64> %c, <2x i64> %d ) {
123123 ; CHECK-LABEL: test_select_cc_v2i64:
124124 ; CHECK: cmp x0, x1
125 ; CHECK-NEXT: csinv x0, xzr, xzr, ne
125 ; CHECK-NEXT: csetm x0, eq
126126 ; CHECK-NEXT: dup v{{[0-9]+}}.2d, x0
127127 ; CHECK-NEXT: bsl v{{[0-9]+}}.16b, v0.16b, v1.16b
128128 %cmp31 = icmp eq i64 %a, %b
162162 define <4x float> @test_select_cc_v4f32_icmp(i32 %a, i32 %b, <4x float> %c, <4x float> %d ) {
163163 ; CHECK-LABEL: test_select_cc_v4f32_icmp:
164164 ; CHECK: cmp w0, w1, uxtw
165 ; CHECK: csinv w0, wzr, wzr, ne
165 ; CHECK: csetm w0, eq
166166 ; CHECK-NEXT: dup v{{[0-9]+}}.4s, w0
167167 ; CHECK-NEXT: bsl v{{[0-9]+}}.16b, v0.16b, v1.16b
168168 %cmp31 = icmp eq i32 %a, %b
182182 define <1 x double> @test_select_cc_v1f64_icmp(i64 %a, i64 %b, <1 x double> %c, <1 x double> %d ) {
183183 ; CHECK-LABEL: test_select_cc_v1f64_icmp:
184184 ; CHECK: cmp x0, x1
185 ; CHECK-NEXT: csinv x0, xzr, xzr, ne
185 ; CHECK-NEXT: csetm x0, eq
186186 ; CHECK-NEXT: fmov d{{[0-9]+}}, x0
187187 ; CHECK-NEXT: bsl v{{[0-9]+}}.8b, v0.8b, v1.8b
188188 %cmp31 = icmp eq i64 %a, %b
8585 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
8686 ; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
8787 ; CHECK: cmp [[DEST_REGLO]], x2
88 ; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, hi
89 ; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
90 ; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, gt
88 ; CHECK: cset [[LOCMP:w[0-9]+]], ls
89 ; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
90 ; CHECK: cset [[HICMP:w[0-9]+]], le
9191 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
9292 ; CHECK: cmp [[CMP]], #0
9393 ; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
107107 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
108108 ; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
109109 ; CHECK: cmp [[DEST_REGLO]], x2
110 ; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, ls
111 ; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
112 ; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, le
110 ; CHECK: cset [[LOCMP:w[0-9]+]], hi
111 ; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
112 ; CHECK: cset [[HICMP:w[0-9]+]], gt
113113 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
114114 ; CHECK: cmp [[CMP]], #0
115115 ; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
129129 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
130130 ; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
131131 ; CHECK: cmp [[DEST_REGLO]], x2
132 ; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, hi
133 ; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
134 ; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, hi
132 ; CHECK: cset [[LOCMP:w[0-9]+]], ls
133 ; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
134 ; CHECK: cset [[HICMP:w[0-9]+]], ls
135135 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
136136 ; CHECK: cmp [[CMP]], #0
137137 ; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
151151 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
152152 ; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
153153 ; CHECK: cmp [[DEST_REGLO]], x2
154 ; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, ls
155 ; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
156 ; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, ls
154 ; CHECK: cset [[LOCMP:w[0-9]+]], hi
155 ; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
156 ; CHECK: cset [[HICMP:w[0-9]+]], hi
157157 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
158158 ; CHECK: cmp [[CMP]], #0
159159 ; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
66
77 define zeroext i8 @foo(i32 %i1, i32 %i2) {
88 ; CHECK-LABEL: foo:
9 ; CHECK: csinc
9 ; CHECK: cset
1010 ; CHECK-NOT: and
1111 entry:
1212 %idxprom = sext i32 %i1 to i64
11 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64"
22 target triple = "arm64-unknown-unknown"
33
4 ; CHECK: foo1
5 ; CHECK: csinc w{{[0-9]+}}, w[[REG:[0-9]+]],
6 ; CHECK: w[[REG]], eq
4 ; CHECK-LABEL: foo1
5 ; CHECK: cinc w{{[0-9]+}}, w{{[0-9]+}}, ne
76 define i32 @foo1(i32 %b, i32 %c) nounwind readnone ssp {
87 entry:
98 %not.tobool = icmp ne i32 %c, 0
1312 ret i32 %add1
1413 }
1514
16 ; CHECK: foo2
17 ; CHECK: csneg w{{[0-9]+}}, w[[REG:[0-9]+]],
18 ; CHECK: w[[REG]], eq
15 ; CHECK-LABEL: foo2
16 ; CHECK: cneg w{{[0-9]+}}, w{{[0-9]+}}, ne
1917 define i32 @foo2(i32 %b, i32 %c) nounwind readnone ssp {
2018 entry:
2119 %mul = sub i32 0, %b
2523 ret i32 %add
2624 }
2725
28 ; CHECK: foo3
29 ; CHECK: csinv w{{[0-9]+}}, w[[REG:[0-9]+]],
30 ; CHECK: w[[REG]], eq
26 ; CHECK-LABEL: foo3
27 ; CHECK: cinv w{{[0-9]+}}, w{{[0-9]+}}, ne
3128 define i32 @foo3(i32 %b, i32 %c) nounwind readnone ssp {
3229 entry:
3330 %not.tobool = icmp ne i32 %c, 0
3936
4037 ; rdar://11632325
4138 define i32@foo4(i32 %a) nounwind ssp {
42 ; CHECK: foo4
43 ; CHECK: csneg
39 ; CHECK-LABEL: foo4
40 ; CHECK: cneg
4441 ; CHECK-NEXT: ret
4542 %cmp = icmp sgt i32 %a, -1
4643 %neg = sub nsw i32 0, %a
5047
5148 define i32@foo5(i32 %a, i32 %b) nounwind ssp {
5249 entry:
53 ; CHECK: foo5
50 ; CHECK-LABEL: foo5
5451 ; CHECK: subs
55 ; CHECK-NEXT: csneg
52 ; CHECK-NEXT: cneg
5653 ; CHECK-NEXT: ret
5754 %sub = sub nsw i32 %a, %b
5855 %cmp = icmp sgt i32 %sub, -1
6360
6461 ; make sure we can handle branch instruction in optimizeCompare.
6562 define i32@foo6(i32 %a, i32 %b) nounwind ssp {
66 ; CHECK: foo6
63 ; CHECK-LABEL: foo6
6764 ; CHECK: b
6865 %sub = sub nsw i32 %a, %b
6966 %cmp = icmp sgt i32 %sub, 0
115112 ; CHECK-LABEL: foo9:
116113 ; CHECK: cmp w0, #0
117114 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
118 ; CHECK: csinv w0, w[[REG]], w[[REG]], ne
115 ; CHECK: cinv w0, w[[REG]], eq
119116 %tobool = icmp ne i32 %v, 0
120117 %cond = select i1 %tobool, i32 4, i32 -5
121118 ret i32 %cond
126123 ; CHECK-LABEL: foo10:
127124 ; CHECK: cmp x0, #0
128125 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
129 ; CHECK: csinv x0, x[[REG]], x[[REG]], ne
126 ; CHECK: cinv x0, x[[REG]], eq
130127 %tobool = icmp ne i64 %v, 0
131128 %cond = select i1 %tobool, i64 4, i64 -5
132129 ret i64 %cond
137134 ; CHECK-LABEL: foo11:
138135 ; CHECK: cmp w0, #0
139136 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
140 ; CHECK: csneg w0, w[[REG]], w[[REG]], ne
137 ; CHECK: cneg w0, w[[REG]], eq
141138 %tobool = icmp ne i32 %v, 0
142139 %cond = select i1 %tobool, i32 4, i32 -4
143140 ret i32 %cond
148145 ; CHECK-LABEL: foo12:
149146 ; CHECK: cmp x0, #0
150147 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
151 ; CHECK: csneg x0, x[[REG]], x[[REG]], ne
148 ; CHECK: cneg x0, x[[REG]], eq
152149 %tobool = icmp ne i64 %v, 0
153150 %cond = select i1 %tobool, i64 4, i64 -4
154151 ret i64 %cond
181178 ; CHECK-LABEL: foo15:
182179 ; CHECK: cmp w0, w1
183180 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
184 ; CHECK: csinc w0, w[[REG]], w[[REG]], le
181 ; CHECK: cinc w0, w[[REG]], gt
185182 %cmp = icmp sgt i32 %a, %b
186183 %. = select i1 %cmp, i32 2, i32 1
187184 ret i32 %.
192189 ; CHECK-LABEL: foo16:
193190 ; CHECK: cmp w0, w1
194191 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
195 ; CHECK: csinc w0, w[[REG]], w[[REG]], gt
192 ; CHECK: cinc w0, w[[REG]], le
196193 %cmp = icmp sgt i32 %a, %b
197194 %. = select i1 %cmp, i32 1, i32 2
198195 ret i32 %.
203200 ; CHECK-LABEL: foo17:
204201 ; CHECK: cmp x0, x1
205202 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
206 ; CHECK: csinc x0, x[[REG]], x[[REG]], le
203 ; CHECK: cinc x0, x[[REG]], gt
207204 %cmp = icmp sgt i64 %a, %b
208205 %. = select i1 %cmp, i64 2, i64 1
209206 ret i64 %.
214211 ; CHECK-LABEL: foo18:
215212 ; CHECK: cmp x0, x1
216213 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
217 ; CHECK: csinc x0, x[[REG]], x[[REG]], gt
214 ; CHECK: cinc x0, x[[REG]], le
218215 %cmp = icmp sgt i64 %a, %b
219216 %. = select i1 %cmp, i64 1, i64 2
220217 ret i64 %.
55 %left = shl i64 %in, 19
66 %right = lshr i64 %in, 45
77 %val5 = or i64 %left, %right
8 ; CHECK: extr {{x[0-9]+}}, x0, x0, #45
8 ; CHECK: ror {{x[0-9]+}}, x0, #45
99 ret i64 %val5
1010 }
1111
1414 %left = shl i32 %in, 9
1515 %right = lshr i32 %in, 23
1616 %val5 = or i32 %left, %right
17 ; CHECK: extr {{w[0-9]+}}, w0, w0, #23
17 ; CHECK: ror {{w[0-9]+}}, w0, #23
1818 ret i32 %val5
1919 }
2020
11
22 define zeroext i1 @fcmp_float1(float %a) nounwind ssp {
33 entry:
4 ; CHECK: @fcmp_float1
4 ; CHECK-LABEL: @fcmp_float1
55 ; CHECK: fcmp s0, #0.0
6 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
6 ; CHECK: cset w{{[0-9]+}}, ne
77 %cmp = fcmp une float %a, 0.000000e+00
88 ret i1 %cmp
99 }
1010
1111 define zeroext i1 @fcmp_float2(float %a, float %b) nounwind ssp {
1212 entry:
13 ; CHECK: @fcmp_float2
13 ; CHECK-LABEL: @fcmp_float2
1414 ; CHECK: fcmp s0, s1
15 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
15 ; CHECK: cset w{{[0-9]+}}, ne
1616 %cmp = fcmp une float %a, %b
1717 ret i1 %cmp
1818 }
1919
2020 define zeroext i1 @fcmp_double1(double %a) nounwind ssp {
2121 entry:
22 ; CHECK: @fcmp_double1
22 ; CHECK-LABEL: @fcmp_double1
2323 ; CHECK: fcmp d0, #0.0
24 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
24 ; CHECK: cset w{{[0-9]+}}, ne
2525 %cmp = fcmp une double %a, 0.000000e+00
2626 ret i1 %cmp
2727 }
2828
2929 define zeroext i1 @fcmp_double2(double %a, double %b) nounwind ssp {
3030 entry:
31 ; CHECK: @fcmp_double2
31 ; CHECK-LABEL: @fcmp_double2
3232 ; CHECK: fcmp d0, d1
33 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
33 ; CHECK: cset w{{[0-9]+}}, ne
3434 %cmp = fcmp une double %a, %b
3535 ret i1 %cmp
3636 }
3737
3838 ; Check each fcmp condition
3939 define float @fcmp_oeq(float %a, float %b) nounwind ssp {
40 ; CHECK: @fcmp_oeq
40 ; CHECK-LABEL: @fcmp_oeq
4141 ; CHECK: fcmp s0, s1
42 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ne
42 ; CHECK: cset w{{[0-9]+}}, eq
4343 %cmp = fcmp oeq float %a, %b
4444 %conv = uitofp i1 %cmp to float
4545 ret float %conv
4646 }
4747
4848 define float @fcmp_ogt(float %a, float %b) nounwind ssp {
49 ; CHECK: @fcmp_ogt
49 ; CHECK-LABEL: @fcmp_ogt
5050 ; CHECK: fcmp s0, s1
51 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, le
51 ; CHECK: cset w{{[0-9]+}}, gt
5252 %cmp = fcmp ogt float %a, %b
5353 %conv = uitofp i1 %cmp to float
5454 ret float %conv
5555 }
5656
5757 define float @fcmp_oge(float %a, float %b) nounwind ssp {
58 ; CHECK: @fcmp_oge
58 ; CHECK-LABEL: @fcmp_oge
5959 ; CHECK: fcmp s0, s1
60 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, lt
60 ; CHECK: cset w{{[0-9]+}}, ge
6161 %cmp = fcmp oge float %a, %b
6262 %conv = uitofp i1 %cmp to float
6363 ret float %conv
6464 }
6565
6666 define float @fcmp_olt(float %a, float %b) nounwind ssp {
67 ; CHECK: @fcmp_olt
67 ; CHECK-LABEL: @fcmp_olt
6868 ; CHECK: fcmp s0, s1
69 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, pl
69 ; CHECK: cset w{{[0-9]+}}, mi
7070 %cmp = fcmp olt float %a, %b
7171 %conv = uitofp i1 %cmp to float
7272 ret float %conv
7373 }
7474
7575 define float @fcmp_ole(float %a, float %b) nounwind ssp {
76 ; CHECK: @fcmp_ole
76 ; CHECK-LABEL: @fcmp_ole
7777 ; CHECK: fcmp s0, s1
78 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, hi
78 ; CHECK: cset w{{[0-9]+}}, ls
7979 %cmp = fcmp ole float %a, %b
8080 %conv = uitofp i1 %cmp to float
8181 ret float %conv
8282 }
8383
8484 define float @fcmp_ord(float %a, float %b) nounwind ssp {
85 ; CHECK: @fcmp_ord
85 ; CHECK-LABEL: @fcmp_ord
8686 ; CHECK: fcmp s0, s1
87 ; CHECK: csinc {{w[0-9]+}}, wzr, wzr, vs
87 ; CHECK: cset {{w[0-9]+}}, vc
8888 %cmp = fcmp ord float %a, %b
8989 %conv = uitofp i1 %cmp to float
9090 ret float %conv
9191 }
9292
9393 define float @fcmp_uno(float %a, float %b) nounwind ssp {
94 ; CHECK: @fcmp_uno
94 ; CHECK-LABEL: @fcmp_uno
9595 ; CHECK: fcmp s0, s1
96 ; CHECK: csinc {{w[0-9]+}}, wzr, wzr, vc
96 ; CHECK: cset {{w[0-9]+}}, vs
9797 %cmp = fcmp uno float %a, %b
9898 %conv = uitofp i1 %cmp to float
9999 ret float %conv
100100 }
101101
102102 define float @fcmp_ugt(float %a, float %b) nounwind ssp {
103 ; CHECK: @fcmp_ugt
103 ; CHECK-LABEL: @fcmp_ugt
104104 ; CHECK: fcmp s0, s1
105 ; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ls
105 ; CHECK: cset {{w[0-9]+}}, hi
106106 %cmp = fcmp ugt float %a, %b
107107 %conv = uitofp i1 %cmp to float
108108 ret float %conv
109109 }
110110
111111 define float @fcmp_uge(float %a, float %b) nounwind ssp {
112 ; CHECK: @fcmp_uge
112 ; CHECK-LABEL: @fcmp_uge
113113 ; CHECK: fcmp s0, s1
114 ; CHECK: csinc {{w[0-9]+}}, wzr, wzr, mi
114 ; CHECK: cset {{w[0-9]+}}, pl
115115 %cmp = fcmp uge float %a, %b
116116 %conv = uitofp i1 %cmp to float
117117 ret float %conv
118118 }
119119
120120 define float @fcmp_ult(float %a, float %b) nounwind ssp {
121 ; CHECK: @fcmp_ult
121 ; CHECK-LABEL: @fcmp_ult
122122 ; CHECK: fcmp s0, s1
123 ; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ge
123 ; CHECK: cset {{w[0-9]+}}, lt
124124 %cmp = fcmp ult float %a, %b
125125 %conv = uitofp i1 %cmp to float
126126 ret float %conv
127127 }
128128
129129 define float @fcmp_ule(float %a, float %b) nounwind ssp {
130 ; CHECK: @fcmp_ule
130 ; CHECK-LABEL: @fcmp_ule
131131 ; CHECK: fcmp s0, s1
132 ; CHECK: csinc {{w[0-9]+}}, wzr, wzr, gt
132 ; CHECK: cset {{w[0-9]+}}, le
133133 %cmp = fcmp ule float %a, %b
134134 %conv = uitofp i1 %cmp to float
135135 ret float %conv
136136 }
137137
138138 define float @fcmp_une(float %a, float %b) nounwind ssp {
139 ; CHECK: @fcmp_une
139 ; CHECK-LABEL: @fcmp_une
140140 ; CHECK: fcmp s0, s1
141 ; CHECK: csinc {{w[0-9]+}}, wzr, wzr, eq
141 ; CHECK: cset {{w[0-9]+}}, ne
142142 %cmp = fcmp une float %a, %b
143143 %conv = uitofp i1 %cmp to float
144144 ret float %conv
33 entry:
44 ; CHECK: icmp_eq_imm
55 ; CHECK: cmp w0, #31
6 ; CHECK: csinc w0, wzr, wzr, ne
6 ; CHECK: cset w0, eq
77 %cmp = icmp eq i32 %a, 31
88 %conv = zext i1 %cmp to i32
99 ret i32 %conv
1313 entry:
1414 ; CHECK: icmp_eq_neg_imm
1515 ; CHECK: cmn w0, #7
16 ; CHECK: csinc w0, wzr, wzr, ne
16 ; CHECK: cset w0, eq
1717 %cmp = icmp eq i32 %a, -7
1818 %conv = zext i1 %cmp to i32
1919 ret i32 %conv
2323 entry:
2424 ; CHECK: icmp_eq
2525 ; CHECK: cmp w0, w1
26 ; CHECK: csinc w0, wzr, wzr, ne
26 ; CHECK: cset w0, eq
2727 %cmp = icmp eq i32 %a, %b
2828 %conv = zext i1 %cmp to i32
2929 ret i32 %conv
3333 entry:
3434 ; CHECK: icmp_ne
3535 ; CHECK: cmp w0, w1
36 ; CHECK: csinc w0, wzr, wzr, eq
36 ; CHECK: cset w0, ne
3737 %cmp = icmp ne i32 %a, %b
3838 %conv = zext i1 %cmp to i32
3939 ret i32 %conv
4343 entry:
4444 ; CHECK: icmp_ugt
4545 ; CHECK: cmp w0, w1
46 ; CHECK: csinc w0, wzr, wzr, ls
46 ; CHECK: cset w0, hi
4747 %cmp = icmp ugt i32 %a, %b
4848 %conv = zext i1 %cmp to i32
4949 ret i32 %conv
5353 entry:
5454 ; CHECK: icmp_uge
5555 ; CHECK: cmp w0, w1
56 ; CHECK: csinc w0, wzr, wzr, lo
56 ; CHECK: cset w0, hs
5757 %cmp = icmp uge i32 %a, %b
5858 %conv = zext i1 %cmp to i32
5959 ret i32 %conv
6363 entry:
6464 ; CHECK: icmp_ult
6565 ; CHECK: cmp w0, w1
66 ; CHECK: csinc w0, wzr, wzr, hs
66 ; CHECK: cset w0, lo
6767 %cmp = icmp ult i32 %a, %b
6868 %conv = zext i1 %cmp to i32
6969 ret i32 %conv
7373 entry:
7474 ; CHECK: icmp_ule
7575 ; CHECK: cmp w0, w1
76 ; CHECK: csinc w0, wzr, wzr, hi
76 ; CHECK: cset w0, ls
7777 %cmp = icmp ule i32 %a, %b
7878 %conv = zext i1 %cmp to i32
7979 ret i32 %conv
8383 entry:
8484 ; CHECK: icmp_sgt
8585 ; CHECK: cmp w0, w1
86 ; CHECK: csinc w0, wzr, wzr, le
86 ; CHECK: cset w0, gt
8787 %cmp = icmp sgt i32 %a, %b
8888 %conv = zext i1 %cmp to i32
8989 ret i32 %conv
9393 entry:
9494 ; CHECK: icmp_sge
9595 ; CHECK: cmp w0, w1
96 ; CHECK: csinc w0, wzr, wzr, lt
96 ; CHECK: cset w0, ge
9797 %cmp = icmp sge i32 %a, %b
9898 %conv = zext i1 %cmp to i32
9999 ret i32 %conv
103103 entry:
104104 ; CHECK: icmp_slt
105105 ; CHECK: cmp w0, w1
106 ; CHECK: csinc w0, wzr, wzr, ge
106 ; CHECK: cset w0, lt
107107 %cmp = icmp slt i32 %a, %b
108108 %conv = zext i1 %cmp to i32
109109 ret i32 %conv
113113 entry:
114114 ; CHECK: icmp_sle
115115 ; CHECK: cmp w0, w1
116 ; CHECK: csinc w0, wzr, wzr, gt
116 ; CHECK: cset w0, le
117117 %cmp = icmp sle i32 %a, %b
118118 %conv = zext i1 %cmp to i32
119119 ret i32 %conv
123123 entry:
124124 ; CHECK: icmp_i64
125125 ; CHECK: cmp x0, x1
126 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, gt
126 ; CHECK: cset w{{[0-9]+}}, le
127127 %cmp = icmp sle i64 %a, %b
128128 %conv = zext i1 %cmp to i32
129129 ret i32 %conv
135135 ; CHECK: sxth w0, w0
136136 ; CHECK: sxth w1, w1
137137 ; CHECK: cmp w0, w1
138 ; CHECK: csinc w0, wzr, wzr, ne
138 ; CHECK: cset w0, eq
139139 %cmp = icmp eq i16 %a, %b
140140 ret i1 %cmp
141141 }
146146 ; CHECK: sxtb w0, w0
147147 ; CHECK: sxtb w1, w1
148148 ; CHECK: cmp w0, w1
149 ; CHECK: csinc w0, wzr, wzr, ne
149 ; CHECK: cset w0, eq
150150 %cmp = icmp eq i8 %a, %b
151151 ret i1 %cmp
152152 }
157157 ; CHECK: uxth w0, w0
158158 ; CHECK: uxth w1, w1
159159 ; CHECK: cmp w0, w1
160 ; CHECK: csinc w0, wzr, wzr, hs
160 ; CHECK: cset w0, lo
161161 %cmp = icmp ult i16 %a, %b
162162 %conv2 = zext i1 %cmp to i32
163163 ret i32 %conv2
169169 ; CHECK: sxtb w0, w0
170170 ; CHECK: sxtb w1, w1
171171 ; CHECK: cmp w0, w1
172 ; CHECK: csinc w0, wzr, wzr, le
172 ; CHECK: cset w0, gt
173173 %cmp = icmp sgt i8 %a, %b
174174 %conv2 = zext i1 %cmp to i32
175175 ret i32 %conv2
181181 ; CHECK: icmp_i16_signed_const
182182 ; CHECK: sxth w0, w0
183183 ; CHECK: cmn w0, #233
184 ; CHECK: csinc w0, wzr, wzr, ge
184 ; CHECK: cset w0, lt
185185 ; CHECK: and w0, w0, #0x1
186186 %cmp = icmp slt i16 %a, -233
187187 %conv2 = zext i1 %cmp to i32
193193 ; CHECK: icmp_i8_signed_const
194194 ; CHECK: sxtb w0, w0
195195 ; CHECK: cmp w0, #124
196 ; CHECK: csinc w0, wzr, wzr, le
196 ; CHECK: cset w0, gt
197197 ; CHECK: and w0, w0, #0x1
198198 %cmp = icmp sgt i8 %a, 124
199199 %conv2 = zext i1 %cmp to i32
205205 ; CHECK: icmp_i1_unsigned_const
206206 ; CHECK: and w0, w0, #0x1
207207 ; CHECK: cmp w0, #0
208 ; CHECK: csinc w0, wzr, wzr, hs
208 ; CHECK: cset w0, lo
209209 ; CHECK: and w0, w0, #0x1
210210 %cmp = icmp ult i1 %a, 0
211211 %conv2 = zext i1 %cmp to i32
44 entry:
55 ; CHECK-LABEL: @fcmp_float1
66 ; CHECK: fcmp s0, #0.0
7 ; CHECK: csinc w0, wzr, wzr, eq
7 ; CHECK: cset w0, ne
88 %cmp = fcmp une float %a, 0.000000e+00
99 ret i1 %cmp
1010 }
1313 entry:
1414 ; CHECK-LABEL: @fcmp_float2
1515 ; CHECK: fcmp s0, s1
16 ; CHECK: csinc w0, wzr, wzr, eq
16 ; CHECK: cset w0, ne
1717 %cmp = fcmp une float %a, %b
1818 ret i1 %cmp
1919 }
2222 entry:
2323 ; CHECK-LABEL: @fcmp_double1
2424 ; CHECK: fcmp d0, #0.0
25 ; CHECK: csinc w0, wzr, wzr, eq
25 ; CHECK: cset w0, ne
2626 %cmp = fcmp une double %a, 0.000000e+00
2727 ret i1 %cmp
2828 }
3131 entry:
3232 ; CHECK-LABEL: @fcmp_double2
3333 ; CHECK: fcmp d0, d1
34 ; CHECK: csinc w0, wzr, wzr, eq
34 ; CHECK: cset w0, ne
3535 %cmp = fcmp une double %a, %b
3636 ret i1 %cmp
3737 }
132132 %val = fcmp ole fp128 %lhs, %rhs
133133 ; CHECK: bl __letf2
134134 ; CHECK: cmp w0, #0
135 ; CHECK: csinc w0, wzr, wzr, gt
135 ; CHECK: cset w0, le
136136
137137 ret i1 %val
138138 ; CHECK: ret
149149 %val = fcmp ugt fp128 %lhs, %rhs
150150 ; CHECK: bl __gttf2
151151 ; CHECK: cmp w0, #0
152 ; CHECK: csinc [[GT:w[0-9]+]], wzr, wzr, le
152 ; CHECK: cset [[GT:w[0-9]+]], gt
153153
154154 ; CHECK: bl __unordtf2
155155 ; CHECK: cmp w0, #0
156 ; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
156 ; CHECK: cset [[UNORDERED:w[0-9]+]], ne
157157 ; CHECK: orr w0, [[UNORDERED]], [[GT]]
158158
159159 ret i1 %val
172172 %cond = fcmp olt fp128 %lhs, %rhs
173173 ; CHECK: bl __getf2
174174 ; CHECK: cmp w0, #0
175 ; CHECK: csinc [[OGE:w[0-9]+]], wzr, wzr, lt
175 ; CHECK: cset [[OGE:w[0-9]+]], ge
176176
177177 ; CHECK: bl __unordtf2
178178 ; CHECK: cmp w0, #0
179 ; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
179 ; CHECK: cset [[UNORDERED:w[0-9]+]], ne
180180
181181 ; CHECK: orr [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]]
182182 ; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]]
99 ; CHECK-LABEL: t1:
1010 ; CHECK-NOT: movn
1111 ; CHECK: cmp x0, #0
12 ; CHECK: csinc w0, wzr, wzr, lt
12 ; CHECK: cset w0, ge
1313 %cmp = icmp sgt i64 %a, -1
1414 %conv = zext i1 %cmp to i32
1515 ret i32 %conv
66 define i64 @test_sext_extr_cmp_0(<1 x i64> %v1, <1 x i64> %v2) {
77 ; CHECK-LABEL: test_sext_extr_cmp_0:
88 ; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
9 ; CHECK: csinc
9 ; CHECK: cset
1010 %1 = icmp sge <1 x i64> %v1, %v2
1111 %2 = extractelement <1 x i1> %1, i32 0
1212 %vget_lane = sext i1 %2 to i64
66 entry:
77 ; CHECK-LABEL: saddo.i32
88 ; CHECK: adds w8, w0, w1
9 ; CHECK-NEXT: csinc w0, wzr, wzr, vc
9 ; CHECK-NEXT: cset w0, vs
1010 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
1111 %val = extractvalue {i32, i1} %t, 0
1212 %obit = extractvalue {i32, i1} %t, 1
1818 entry:
1919 ; CHECK-LABEL: saddo.i64
2020 ; CHECK: adds x8, x0, x1
21 ; CHECK-NEXT: csinc w0, wzr, wzr, vc
21 ; CHECK-NEXT: cset w0, vs
2222 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
2323 %val = extractvalue {i64, i1} %t, 0
2424 %obit = extractvalue {i64, i1} %t, 1
3030 entry:
3131 ; CHECK-LABEL: uaddo.i32
3232 ; CHECK: adds w8, w0, w1
33 ; CHECK-NEXT: csinc w0, wzr, wzr, lo
33 ; CHECK-NEXT: cset w0, hs
3434 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
3535 %val = extractvalue {i32, i1} %t, 0
3636 %obit = extractvalue {i32, i1} %t, 1
4242 entry:
4343 ; CHECK-LABEL: uaddo.i64
4444 ; CHECK: adds x8, x0, x1
45 ; CHECK-NEXT: csinc w0, wzr, wzr, lo
45 ; CHECK-NEXT: cset w0, hs
4646 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
4747 %val = extractvalue {i64, i1} %t, 0
4848 %obit = extractvalue {i64, i1} %t, 1
5454 entry:
5555 ; CHECK-LABEL: ssubo.i32
5656 ; CHECK: subs w8, w0, w1
57 ; CHECK-NEXT: csinc w0, wzr, wzr, vc
57 ; CHECK-NEXT: cset w0, vs
5858 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
5959 %val = extractvalue {i32, i1} %t, 0
6060 %obit = extractvalue {i32, i1} %t, 1
6666 entry:
6767 ; CHECK-LABEL: ssubo.i64
6868 ; CHECK: subs x8, x0, x1
69 ; CHECK-NEXT: csinc w0, wzr, wzr, vc
69 ; CHECK-NEXT: cset w0, vs
7070 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
7171 %val = extractvalue {i64, i1} %t, 0
7272 %obit = extractvalue {i64, i1} %t, 1
7878 entry:
7979 ; CHECK-LABEL: usubo.i32
8080 ; CHECK: subs w8, w0, w1
81 ; CHECK-NEXT: csinc w0, wzr, wzr, hs
81 ; CHECK-NEXT: cset w0, lo
8282 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
8383 %val = extractvalue {i32, i1} %t, 0
8484 %obit = extractvalue {i32, i1} %t, 1
9090 entry:
9191 ; CHECK-LABEL: usubo.i64
9292 ; CHECK: subs x8, x0, x1
93 ; CHECK-NEXT: csinc w0, wzr, wzr, hs
93 ; CHECK-NEXT: cset w0, lo
9494 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
9595 %val = extractvalue {i64, i1} %t, 0
9696 %obit = extractvalue {i64, i1} %t, 1
104104 ; CHECK: smull x8, w0, w1
105105 ; CHECK-NEXT: lsr x9, x8, #32
106106 ; CHECK-NEXT: cmp w9, w8, asr #31
107 ; CHECK-NEXT: csinc w0, wzr, wzr, eq
107 ; CHECK-NEXT: cset w0, ne
108108 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
109109 %val = extractvalue {i32, i1} %t, 0
110110 %obit = extractvalue {i32, i1} %t, 1
118118 ; CHECK: mul x8, x0, x1
119119 ; CHECK-NEXT: smulh x9, x0, x1
120120 ; CHECK-NEXT: cmp x9, x8, asr #63
121 ; CHECK-NEXT: csinc w0, wzr, wzr, eq
121 ; CHECK-NEXT: cset w0, ne
122122 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
123123 %val = extractvalue {i64, i1} %t, 0
124124 %obit = extractvalue {i64, i1} %t, 1
131131 ; CHECK-LABEL: umulo.i32
132132 ; CHECK: umull x8, w0, w1
133133 ; CHECK-NEXT: cmp xzr, x8, lsr #32
134 ; CHECK-NEXT: csinc w0, wzr, wzr, eq
134 ; CHECK-NEXT: cset w0, ne
135135 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
136136 %val = extractvalue {i32, i1} %t, 0
137137 %obit = extractvalue {i32, i1} %t, 1
144144 ; CHECK-LABEL: umulo.i64
145145 ; CHECK: umulh x8, x0, x1
146146 ; CHECK-NEXT: cmp xzr, x8
147 ; CHECK-NEXT: csinc w8, wzr, wzr, eq
147 ; CHECK-NEXT: cset w8, ne
148148 ; CHECK-NEXT: mul x9, x0, x1
149149 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
150150 %val = extractvalue {i64, i1} %t, 0
66 %div = udiv i16 %x, 33
77 ret i16 %div
88 ; CHECK-LABEL: test1:
9 ; CHECK: imull $63551, %eax, %eax
9 ; CHECK: imull $63551, %eax
1010 ; CHECK-NEXT: shrl $21, %eax
1111 ; CHECK-NEXT: ret
1212 }
1717 ret i16 %div
1818
1919 ; CHECK-LABEL: test2:
20 ; CHECK: imull $43691, %eax, %eax
20 ; CHECK: imull $43691, %eax
2121 ; CHECK-NEXT: shrl $17, %eax
2222 ; CHECK-NEXT: ret
2323 }
2929
3030 ; CHECK-LABEL: test3:
3131 ; CHECK: movzbl 8(%esp), %eax
32 ; CHECK-NEXT: imull $171, %eax, %eax
32 ; CHECK-NEXT: imull $171, %eax
3333 ; CHECK-NEXT: shrl $9, %eax
3434 ; CHECK-NEXT: ret
3535 }
3939 %div = sdiv i16 %x, 33 ; [#uses=1]
4040 ret i16 %div
4141 ; CHECK-LABEL: test4:
42 ; CHECK: imull $1986, %eax, %
42 ; CHECK: imull $1986, %eax
4343 }
4444
4545 define i32 @test5(i32 %A) nounwind {
730730 neg w26, w25, lsl #29
731731 neg w24, w23, lsl #31
732732 // CHECK-AARCH64: sub w28, wzr, w27 // encoding: [0xfc,0x03,0x1b,0x4b]
733 // CHECK-AARCH64: neg w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b]
734 // CHECK-AARCH64: neg w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
735
733736 // CHECK-ARM64: neg w28, w27 // encoding: [0xfc,0x03,0x1b,0x4b]
734 // CHECK: sub w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b]
735 // CHECK: sub w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
737 // CHECK-ARM64: sub w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b]
738 // CHECK-ARM64: sub w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
736739
737740 neg w22, w21, lsr #0
738741 neg w20, w19, lsr #1
739742 neg w18, w17, lsr #31
740 // CHECK: sub w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b]
741 // CHECK: sub w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b]
742 // CHECK: sub w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b]
743 // CHECK-AARCH64: neg w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b]
744 // CHECK-AARCH64: neg w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b]
745 // CHECK-AARCH64: neg w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b]
746
747 // CHECK-ARM64: sub w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b]
748 // CHECK-ARM64: sub w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b]
749 // CHECK-ARM64: sub w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b]
743750
744751 neg w16, w15, asr #0
745752 neg w14, w13, asr #12
746753 neg w12, w11, asr #31
747 // CHECK: sub w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b]
748 // CHECK: sub w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b]
749 // CHECK: sub w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b]
754 // CHECK-AARCH64: neg w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b]
755 // CHECK-AARCH64: neg w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b]
756 // CHECK-AARCH64: neg w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b]
757
758 // CHECK-ARM64: sub w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b]
759 // CHECK-ARM64: sub w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b]
760 // CHECK-ARM64: sub w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b]
750761
751762 neg x29, x30
752763 neg x30, xzr
762773 neg x26, x25, lsl #29
763774 neg x24, x23, lsl #31
764775 // CHECK-AARCH64: sub x28, xzr, x27 // encoding: [0xfc,0x03,0x1b,0xcb]
776 // CHECK-AARCH64: neg x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb]
777 // CHECK-AARCH64: neg x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
778
765779 // CHECK-ARM64: neg x28, x27 // encoding: [0xfc,0x03,0x1b,0xcb]
766 // CHECK: sub x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb]
767 // CHECK: sub x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
780 // CHECK-ARM64: sub x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb]
781 // CHECK-ARM64: sub x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
768782
769783 neg x22, x21, lsr #0
770784 neg x20, x19, lsr #1
771785 neg x18, x17, lsr #31
772 // CHECK: sub x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb]
773 // CHECK: sub x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb]
774 // CHECK: sub x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb]
786 // CHECK-AARCH64: neg x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb]
787 // CHECK-AARCH64: neg x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb]
788 // CHECK-AARCH64: neg x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb]
789
790 // CHECK-ARM64: sub x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb]
791 // CHECK-ARM64: sub x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb]
792 // CHECK-ARM64: sub x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb]
775793
776794 neg x16, x15, asr #0
777795 neg x14, x13, asr #12
778796 neg x12, x11, asr #31
779 // CHECK: sub x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb]
780 // CHECK: sub x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb]
781 // CHECK: sub x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb]
797 // CHECK-AARCH64: neg x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb]
798 // CHECK-AARCH64: neg x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb]
799 // CHECK-AARCH64: neg x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb]
800
801 // CHECK-ARM64: sub x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb]
802 // CHECK-ARM64: sub x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb]
803 // CHECK-ARM64: sub x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb]
782804
783805 negs w29, w30
784806 negs w30, wzr
794816 negs w26, w25, lsl #29
795817 negs w24, w23, lsl #31
796818 // CHECK-AARCH64: subs w28, wzr, w27 // encoding: [0xfc,0x03,0x1b,0x6b]
819 // CHECK-AARCH64: negs w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b]
820 // CHECK-AARCH64: negs w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
821
797822 // CHECK-ARM64: negs w28, w27 // encoding: [0xfc,0x03,0x1b,0x6b]
798 // CHECK: subs w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b]
799 // CHECK: subs w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
823 // CHECK-ARM64: subs w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b]
824 // CHECK-ARM64: subs w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
800825
801826 negs w22, w21, lsr #0
802827 negs w20, w19, lsr #1
803828 negs w18, w17, lsr #31
804 // CHECK: subs w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b]
805 // CHECK: subs w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b]
806 // CHECK: subs w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b]
829 // CHECK-AARCH64: negs w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b]
830 // CHECK-AARCH64: negs w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b]
831 // CHECK-AARCH64: negs w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b]
832
833 // CHECK-ARM64: subs w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b]
834 // CHECK-ARM64: subs w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b]
835 // CHECK-ARM64: subs w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b]
807836
808837 negs w16, w15, asr #0
809838 negs w14, w13, asr #12
810839 negs w12, w11, asr #31
811 // CHECK: subs w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b]
812 // CHECK: subs w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b]
813 // CHECK: subs w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b]
840 // CHECK-AARCH64: negs w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b]
841 // CHECK-AARCH64: negs w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b]
842 // CHECK-AARCH64: negs w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b]
843
844 // CHECK-ARM64: subs w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b]
845 // CHECK-ARM64: subs w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b]
846 // CHECK-ARM64: subs w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b]
814847
815848 negs x29, x30
816849 negs x30, xzr
826859 negs x26, x25, lsl #29
827860 negs x24, x23, lsl #31
828861 // CHECK-AARCH64: subs x28, xzr, x27 // encoding: [0xfc,0x03,0x1b,0xeb]
862 // CHECK-AARCH64: negs x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb]
863 // CHECK-AARCH64: negs x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
864
829865 // CHECK-ARM64: negs x28, x27 // encoding: [0xfc,0x03,0x1b,0xeb]
830 // CHECK: subs x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb]
831 // CHECK: subs x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
866 // CHECK-ARM64: subs x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb]
867 // CHECK-ARM64: subs x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
832868
833869 negs x22, x21, lsr #0
834870 negs x20, x19, lsr #1
835871 negs x18, x17, lsr #31
836 // CHECK: subs x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb]
837 // CHECK: subs x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb]
838 // CHECK: subs x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb]
872 // CHECK-AARCH64: negs x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb]
873 // CHECK-AARCH64: negs x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb]
874 // CHECK-AARCH64: negs x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb]
875
876 // CHECK-ARM64: subs x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb]
877 // CHECK-ARM64: subs x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb]
878 // CHECK-ARM64: subs x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb]
839879
840880 negs x16, x15, asr #0
841881 negs x14, x13, asr #12
842882 negs x12, x11, asr #31
843 // CHECK: subs x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb]
844 // CHECK: subs x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb]
845 // CHECK: subs x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb]
883 // CHECK-AARCH64: negs x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb]
884 // CHECK-AARCH64: negs x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb]
885 // CHECK-AARCH64: negs x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb]
886
887 // CHECK-ARM64: subs x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb]
888 // CHECK-ARM64: subs x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb]
889 // CHECK-ARM64: subs x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb]
846890
847891 //------------------------------------------------------------------------------
848892 // Add-sub (shifted register)
15121556
15131557 cset w3, eq
15141558 cset x9, pl
1515 // CHECK: csinc w3, wzr, wzr, ne // encoding: [0xe3,0x17,0x9f,0x1a]
1516 // CHECK: csinc x9, xzr, xzr, mi // encoding: [0xe9,0x47,0x9f,0x9a]
1559 // CHECK: cset w3, eq // encoding: [0xe3,0x17,0x9f,0x1a]
1560 // CHECK: cset x9, pl // encoding: [0xe9,0x47,0x9f,0x9a]
15171561
15181562 csetm w20, ne
15191563 csetm x30, ge
1520 // CHECK: csinv w20, wzr, wzr, eq // encoding: [0xf4,0x03,0x9f,0x5a]
1521 // CHECK: csinv x30, xzr, xzr, lt // encoding: [0xfe,0xb3,0x9f,0xda]
1564 // CHECK: csetm w20, ne // encoding: [0xf4,0x03,0x9f,0x5a]
1565 // CHECK: csetm x30, ge // encoding: [0xfe,0xb3,0x9f,0xda]
15221566
15231567 cinc w3, w5, gt
15241568 cinc wzr, w4, le
15251569 cinc w9, wzr, lt
1526 // CHECK: csinc w3, w5, w5, le // encoding: [0xa3,0xd4,0x85,0x1a]
1527 // CHECK: csinc wzr, w4, w4, gt // encoding: [0x9f,0xc4,0x84,0x1a]
1528 // CHECK: csinc w9, wzr, wzr, ge // encoding: [0xe9,0xa7,0x9f,0x1a]
1570 // CHECK: cinc w3, w5, gt // encoding: [0xa3,0xd4,0x85,0x1a]
1571 // CHECK: cinc wzr, w4, le // encoding: [0x9f,0xc4,0x84,0x1a]
1572 // CHECK: cset w9, lt // encoding: [0xe9,0xa7,0x9f,0x1a]
15291573
15301574 cinc x3, x5, gt
15311575 cinc xzr, x4, le
15321576 cinc x9, xzr, lt
1533 // CHECK: csinc x3, x5, x5, le // encoding: [0xa3,0xd4,0x85,0x9a]
1534 // CHECK: csinc xzr, x4, x4, gt // encoding: [0x9f,0xc4,0x84,0x9a]
1535 // CHECK: csinc x9, xzr, xzr, ge // encoding: [0xe9,0xa7,0x9f,0x9a]
1577 // CHECK: cinc x3, x5, gt // encoding: [0xa3,0xd4,0x85,0x9a]
1578 // CHECK: cinc xzr, x4, le // encoding: [0x9f,0xc4,0x84,0x9a]
1579 // CHECK: cset x9, lt // encoding: [0xe9,0xa7,0x9f,0x9a]
15361580
15371581 cinv w3, w5, gt
15381582 cinv wzr, w4, le
15391583 cinv w9, wzr, lt
1540 // CHECK: csinv w3, w5, w5, le // encoding: [0xa3,0xd0,0x85,0x5a]
1541 // CHECK: csinv wzr, w4, w4, gt // encoding: [0x9f,0xc0,0x84,0x5a]
1542 // CHECK: csinv w9, wzr, wzr, ge // encoding: [0xe9,0xa3,0x9f,0x5a]
1584 // CHECK: cinv w3, w5, gt // encoding: [0xa3,0xd0,0x85,0x5a]
1585 // CHECK: cinv wzr, w4, le // encoding: [0x9f,0xc0,0x84,0x5a]
1586 // CHECK: csetm w9, lt // encoding: [0xe9,0xa3,0x9f,0x5a]
15431587
15441588 cinv x3, x5, gt
15451589 cinv xzr, x4, le
15461590 cinv x9, xzr, lt
1547 // CHECK: csinv x3, x5, x5, le // encoding: [0xa3,0xd0,0x85,0xda]
1548 // CHECK: csinv xzr, x4, x4, gt // encoding: [0x9f,0xc0,0x84,0xda]
1549 // CHECK: csinv x9, xzr, xzr, ge // encoding: [0xe9,0xa3,0x9f,0xda]
1591 // CHECK: cinv x3, x5, gt // encoding: [0xa3,0xd0,0x85,0xda]
1592 // CHECK: cinv xzr, x4, le // encoding: [0x9f,0xc0,0x84,0xda]
1593 // CHECK: csetm x9, lt // encoding: [0xe9,0xa3,0x9f,0xda]
15501594
15511595 cneg w3, w5, gt
15521596 cneg wzr, w4, le
15531597 cneg w9, wzr, lt
1554 // CHECK: csneg w3, w5, w5, le // encoding: [0xa3,0xd4,0x85,0x5a]
1555 // CHECK: csneg wzr, w4, w4, gt // encoding: [0x9f,0xc4,0x84,0x5a]
1556 // CHECK: csneg w9, wzr, wzr, ge // encoding: [0xe9,0xa7,0x9f,0x5a]
1598 // CHECK: cneg w3, w5, gt // encoding: [0xa3,0xd4,0x85,0x5a]
1599 // CHECK: cneg wzr, w4, le // encoding: [0x9f,0xc4,0x84,0x5a]
1600 // CHECK: cneg w9, wzr, lt // encoding: [0xe9,0xa7,0x9f,0x5a]
15571601
15581602 cneg x3, x5, gt
15591603 cneg xzr, x4, le
15601604 cneg x9, xzr, lt
1561 // CHECK: csneg x3, x5, x5, le // encoding: [0xa3,0xd4,0x85,0xda]
1562 // CHECK: csneg xzr, x4, x4, gt // encoding: [0x9f,0xc4,0x84,0xda]
1563 // CHECK: csneg x9, xzr, xzr, ge // encoding: [0xe9,0xa7,0x9f,0xda]
1605 // CHECK: cneg x3, x5, gt // encoding: [0xa3,0xd4,0x85,0xda]
1606 // CHECK: cneg xzr, x4, le // encoding: [0x9f,0xc4,0x84,0xda]
1607 // CHECK: cneg x9, xzr, lt // encoding: [0xe9,0xa7,0x9f,0xda]
15641608
15651609 //------------------------------------------------------------------------------
15661610 // Data-processing (1 source)
18581902
18591903 ror x19, x23, #24
18601904 ror x29, xzr, #63
1861 // CHECK: extr x19, x23, x23, #24 // encoding: [0xf3,0x62,0xd7,0x93]
1862 // CHECK: extr x29, xzr, xzr, #63 // encoding: [0xfd,0xff,0xdf,0x93]
1905 // CHECK: ror x19, x23, #24 // encoding: [0xf3,0x62,0xd7,0x93]
1906 // CHECK: ror x29, xzr, #63 // encoding: [0xfd,0xff,0xdf,0x93]
18631907
18641908 ror w9, w13, #31
1865 // CHECK: extr w9, w13, w13, #31 // encoding: [0xa9,0x7d,0x8d,0x13]
1909 // CHECK: ror w9, w13, #31 // encoding: [0xa9,0x7d,0x8d,0x13]
18661910
18671911 //------------------------------------------------------------------------------
18681912 // Floating-point compare
34053449 mov w3, #0xf000f
34063450 mov x10, #0xaaaaaaaaaaaaaaaa
34073451 // CHECK: orr w3, wzr, #0xf000f // encoding: [0xe3,0x8f,0x00,0x32]
3408 // CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2]
3452 // CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2]
34093453
34103454 //------------------------------------------------------------------------------
34113455 // Logical (shifted register)
37463790 sys #7, c5, c9, #7, x5
37473791 sys #0, c15, c15, #2
37483792 // CHECK: sys #7, c5, c9, #7, x5 // encoding: [0xe5,0x59,0x0f,0xd5]
3749 // CHECK: sys #0, c15, c15, #2, xzr // encoding: [0x5f,0xff,0x08,0xd5]
3793 // CHECK: sys #0, c15, c15, #2 // encoding: [0x5f,0xff,0x08,0xd5]
37503794
37513795 sysl x9, #7, c5, c9, #7
37523796 sysl x1, #0, c15, c15, #2
217217 ubfm x0, x0, #63, #62
218218 ubfm w0, w0, #4, #31
219219 ubfm x0, x0, #4, #63
220 ; CHECK: extr w1, w3, w3, #5
221 ; CHECK: extr x1, x3, x3, #5
220 ; CHECK: ror w1, w3, #5
221 ; CHECK: ror x1, x3, #5
222222 ror w1, w3, #5
223223 ror x1, x3, #5
224224 ; CHECK: lsl w1, wzr, #3
301301 cinv w1, w2, mi
302302 cinv x1, x2, mi
303303
304 ; CHECK: csinc w1, wzr, wzr, ne
305 ; CHECK: csinc x1, xzr, xzr, ne
306 ; CHECK: csinv w1, wzr, wzr, eq
307 ; CHECK: csinv x1, xzr, xzr, eq
308 ; CHECK: csinc w1, w2, w2, ge
309 ; CHECK: csinc x1, x2, x2, ge
310 ; CHECK: csinv w1, w2, w2, pl
311 ; CHECK: csinv x1, x2, x2, pl
304 ; CHECK: cset w1, eq
305 ; CHECK: cset x1, eq
306 ; CHECK: csetm w1, ne
307 ; CHECK: csetm x1, ne
308 ; CHECK: cinc w1, w2, lt
309 ; CHECK: cinc x1, x2, lt
310 ; CHECK: cinv w1, w2, mi
311 ; CHECK: cinv x1, x2, mi
312312
313313 ;-----------------------------------------------------------------------------
314314 ; SYS aliases
940940 0xe5 0x27 0x86 0xda
941941 0x7 0x35 0x9f 0xda
942942
943 # CHECK: csinc w3, wzr, wzr, ne
944 # CHECK: csinc x9, xzr, xzr, mi
945 # CHECK: csinv w20, wzr, wzr, eq
946 # CHECK: csinv x30, xzr, xzr, lt
943 # CHECK: cset w3, eq
944 # CHECK: cset x9, pl
945 # CHECK: csetm w20, ne
946 # CHECK: csetm x30, ge
947947 0xe3 0x17 0x9f 0x1a
948948 0xe9 0x47 0x9f 0x9a
949949 0xf4 0x3 0x9f 0x5a
950950 0xfe 0xb3 0x9f 0xda
951951
952 # CHECK: csinc w3, w5, w5, le
953 # CHECK: csinc wzr, w4, w4, gt
954 # CHECK: csinc w9, wzr, wzr, ge
955 # CHECK: csinc x3, x5, x5, le
956 # CHECK: csinc xzr, x4, x4, gt
957 # CHECK: csinc x9, xzr, xzr, ge
952 # CHECK: cinc w3, w5, gt
953 # CHECK: cinc wzr, w4, le
954 # CHECK: cset w9, lt
955 # CHECK: cinc x3, x5, gt
956 # CHECK: cinc xzr, x4, le
957 # CHECK: cset x9, lt
958958 0xa3 0xd4 0x85 0x1a
959959 0x9f 0xc4 0x84 0x1a
960960 0xe9 0xa7 0x9f 0x1a
962962 0x9f 0xc4 0x84 0x9a
963963 0xe9 0xa7 0x9f 0x9a
964964
965 # CHECK: csinv w3, w5, w5, le
966 # CHECK: csinv wzr, w4, w4, gt
967 # CHECK: csinv w9, wzr, wzr, ge
968 # CHECK: csinv x3, x5, x5, le
969 # CHECK: csinv xzr, x4, x4, gt
970 # CHECK: csinv x9, xzr, xzr, ge
965 # CHECK: cinv w3, w5, gt
966 # CHECK: cinv wzr, w4, le
967 # CHECK: csetm w9, lt
968 # CHECK: cinv x3, x5, gt
969 # CHECK: cinv xzr, x4, le
970 # CHECK: csetm x9, lt
971971 0xa3 0xd0 0x85 0x5a
972972 0x9f 0xc0 0x84 0x5a
973973 0xe9 0xa3 0x9f 0x5a
975975 0x9f 0xc0 0x84 0xda
976976 0xe9 0xa3 0x9f 0xda
977977
978 # CHECK: csneg w3, w5, w5, le
979 # CHECK: csneg wzr, w4, w4, gt
980 # CHECK: csneg w9, wzr, wzr, ge
981 # CHECK: csneg x3, x5, x5, le
982 # CHECK: csneg xzr, x4, x4, gt
983 # CHECK: csneg x9, xzr, xzr, ge
978 # CHECK: cneg w3, w5, gt
979 # CHECK: cneg wzr, w4, le
980 # CHECK: cneg w9, wzr, lt
981 # CHECK: cneg x3, x5, gt
982 # CHECK: cneg xzr, x4, le
983 # CHECK: cneg x9, xzr, lt
984984 0xa3 0xd4 0x85 0x5a
985985 0x9f 0xc4 0x84 0x5a
986986 0xe9 0xa7 0x9f 0x5a
12841284 0xa3 0x3c 0xc7 0x93
12851285 0xab 0xfd 0xd1 0x93
12861286
1287 # CHECK: extr x19, x23, x23, #24
1288 # CHECK: extr x29, xzr, xzr, #63
1289 # CHECK: extr w9, w13, w13, #31
1287 # CHECK: ror x19, x23, #24
1288 # CHECK: ror x29, xzr, #63
1289 # CHECK: ror w9, w13, #31
12901290 0xf3 0x62 0xd7 0x93
12911291 0xfd 0xff 0xdf 0x93
12921292 0xa9 0x7d 0x8d 0x13
30143014 0xe9 0x59 0x2f 0xd5
30153015 0x41 0xff 0x28 0xd5
30163016
3017 # CHECK: {{sys #0, c7, c1, #0, xzr|ic ialluis}}
3018 # CHECK: {{sys #0, c7, c5, #0, xzr|ic iallu}}
3017 # CHECK: {{sys #0, c7, c1, #0|ic ialluis}}
3018 # CHECK: {{sys #0, c7, c5, #0|ic iallu}}
30193019 # CHECK: {{sys #3, c7, c5, #1|ic ivau}}, x9
30203020 0x1f 0x71 0x8 0xd5
30213021 0x1f 0x75 0x8 0xd5
30223022 0x29 0x75 0xb 0xd5
30233023
30243024 # CHECK: {{sys #3, c7, c4, #1|dc zva}}, x12
3025 # CHECK: {{sys #0, c7, c6, #1|dc ivac}}, xzr
3025 # CHECK: {{sys #0, c7, c6, #1|dc ivac}}
30263026 # CHECK: {{sys #0, c7, c6, #2|dc isw}}, x2
30273027 # CHECK: {{sys #3, c7, c10, #1|dc cvac}}, x9
30283028 # CHECK: {{sys #0, c7, c10, #2|dc csw}}, x10
99 # Little endian
1010 #------------------------------------------------------------------------------
1111 # CHECK-EL: break # encoding: [0x00,0x00,0x07,0x00]
12 # CHECK-EL: break 7, 0 # encoding: [0x07,0x00,0x07,0x00]
12 # CHECK-EL: break 7 # encoding: [0x07,0x00,0x07,0x00]
1313 # CHECK-EL: break 7, 5 # encoding: [0x07,0x00,0x47,0x01]
1414 # CHECK-EL: syscall # encoding: [0x00,0x00,0x7c,0x8b]
1515 # CHECK-EL: syscall 396 # encoding: [0x8c,0x01,0x7c,0x8b]
2727 # Big endian
2828 #------------------------------------------------------------------------------
2929 # CHECK-EB: break # encoding: [0x00,0x00,0x00,0x07]
30 # CHECK-EB: break 7, 0 # encoding: [0x00,0x07,0x00,0x07]
30 # CHECK-EB: break 7 # encoding: [0x00,0x07,0x00,0x07]
3131 # CHECK-EB: break 7, 5 # encoding: [0x00,0x07,0x01,0x47]
3232 # CHECK-EB: syscall # encoding: [0x00,0x00,0x8b,0x7c]
3333 # CHECK-EB: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
33 # RUN: | FileCheck -check-prefix=CHECK64 %s
44
55 # CHECK32: break # encoding: [0x00,0x00,0x00,0x0d]
6 # CHECK32: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d]
6 # CHECK32: break 7 # encoding: [0x00,0x07,0x00,0x0d]
77 # CHECK32: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
88 # CHECK32: syscall # encoding: [0x00,0x00,0x00,0x0c]
99 # CHECK32: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c]
3636 # CHECK32: tnei $3, 1023 # encoding: [0x04,0x6e,0x03,0xff]
3737
3838 # CHECK64: break # encoding: [0x00,0x00,0x00,0x0d]
39 # CHECK64: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d]
39 # CHECK64: break 7 # encoding: [0x00,0x07,0x00,0x0d]
4040 # CHECK64: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
4141 # CHECK64: syscall # encoding: [0x00,0x00,0x00,0x0c]
4242 # CHECK64: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c]
202202 // CHECK-STDERR: warning: scale factor without index register is ignored
203203 movaps %xmm3, (%esi, 2)
204204
205 // CHECK: imull $12, %eax, %eax
205 // CHECK: imull $12, %eax
206206 imul $12, %eax
207207
208208 // CHECK: imull %ecx, %eax
3838 std::map CGIAWIMap;
3939 const std::vector *NumberedInstructions;
4040 std::vector Instructions;
41 std::vector PrintMethods;
4142 public:
4243 AsmWriterEmitter(RecordKeeper &R);
4344
628629 // alias for that pattern.
629630 class IAPrinter {
630631 std::vector Conds;
631 std::mapunsigned> OpMap;
632 std::mapstd::pair> OpMap;
633 SmallVector ReqFeatures;
634
632635 std::string Result;
633636 std::string AsmString;
634 SmallVector ReqFeatures;
635637 public:
636 IAPrinter(std::string R, std::string AS)
637 : Result(R), AsmString(AS) {}
638 IAPrinter(std::string R, std::string AS) : Result(R), AsmString(AS) {}
638639
639640 void addCond(const std::string &C) { Conds.push_back(C); }
640641
641 void addOperand(StringRef Op, unsigned Idx) {
642 assert(Idx < 0xFF && "Index too large!");
643 OpMap[Op] = Idx;
644 }
645 unsigned getOpIndex(StringRef Op) { return OpMap[Op]; }
642 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) {
643 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
644 assert(PrintMethodIdx == -1 || PrintMethodIdx < 0xFF && "Idx out of range");
645 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx);
646 }
647
646648 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
649 int getOpIndex(StringRef Op) { return OpMap[Op].first; }
650 std::pair &getOpData(StringRef Op) { return OpMap[Op]; }
647651
648652 void print(raw_ostream &O) {
649653 if (Conds.empty() && ReqFeatures.empty()) {
685689 ++I;
686690 StringRef Name(Start, I - Start);
687691 assert(isOpMapped(Name) && "Unmapped operand!");
688 OS << format("\\x%02X", (unsigned char)getOpIndex(Name) + 1);
692
693 int OpIndex, PrintIndex;
694 std::tie(OpIndex, PrintIndex) = getOpData(Name);
695 if (PrintIndex == -1) {
696 // Can use the default printOperand route.
697 OS << format("\\x%02X", (unsigned char)OpIndex + 1);
698 } else
699 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand
700 // number, and which of our pre-detected Methods to call.
701 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
689702 } else {
690703 ++I;
691704 }
753766
754767 O << "\n#ifdef PRINT_ALIAS_INSTR\n";
755768 O << "#undef PRINT_ALIAS_INSTR\n\n";
769
770 //////////////////////////////
771 // Gather information about aliases we need to print
772 //////////////////////////////
756773
757774 // Emit the method that prints the alias instruction.
758775 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
808825 case CodeGenInstAlias::ResultOperand::K_Record: {
809826 const Record *Rec = RO.getRecord();
810827 StringRef ROName = RO.getName();
811
828 int PrintMethodIdx = -1;
829
830 // These two may have a PrintMethod, which we want to record (if it's
831 // the first time we've seen it) and provide an index for the aliasing
832 // code to use.
833 if (Rec->isSubClassOf("RegisterOperand") ||
834 Rec->isSubClassOf("Operand")) {
835 std::string PrintMethod = Rec->getValueAsString("PrintMethod");
836 if (PrintMethod != "" && PrintMethod != "printOperand") {
837 PrintMethodIdx = std::find(PrintMethods.begin(),
838 PrintMethods.end(), PrintMethod) -
839 PrintMethods.begin();
840 if (static_cast(PrintMethodIdx) == PrintMethods.size())
841 PrintMethods.push_back(PrintMethod);
842 }
843 }
812844
813845 if (Rec->isSubClassOf("RegisterOperand"))
814846 Rec = Rec->getValueAsDef("RegClass");
817849 IAP->addCond(Cond);
818850
819851 if (!IAP->isOpMapped(ROName)) {
820 IAP->addOperand(ROName, i);
852 IAP->addOperand(ROName, i, PrintMethodIdx);
821853 Record *R = CGA->ResultOperands[i].getRecord();
822854 if (R->isSubClassOf("RegisterOperand"))
823855 R = R->getValueAsDef("RegClass");
832864 IAP->addCond(Cond);
833865 }
834866 } else {
835 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
836 // FIXME: We may need to handle these situations.
837 delete IAP;
838 IAP = nullptr;
839 CantHandle = true;
840 break;
867 // Assume all printable operands are desired for now. This can be
868 // overridden in the InstAlias instantiation if neccessary.
869 IAP->addOperand(ROName, i, PrintMethodIdx);
841870 }
842871
843872 break;
877906 }
878907 }
879908
909 //////////////////////////////
910 // Write out the printAliasInstr function
911 //////////////////////////////
912
880913 std::string Header;
881914 raw_string_ostream HeaderO(Header);
882915
950983 O << " do {\n";
951984 O << " if (AsmString[I] == '$') {\n";
952985 O << " ++I;\n";
953 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n";
986 O << " if (AsmString[I] == (char)0xff) {\n";
987 O << " ++I;\n";
988 O << " int OpIdx = AsmString[I++] - 1;\n";
989 O << " int PrintMethodIdx = AsmString[I++] - 1;\n";
990 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);\n";
991 O << " } else\n";
992 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n";
954993 O << " } else {\n";
955994 O << " OS << AsmString[I++];\n";
956995 O << " }\n";
959998
960999 O << " return true;\n";
9611000 O << "}\n\n";
1001
1002 //////////////////////////////
1003 // Write out the printCustomAliasOperand function
1004 //////////////////////////////
1005
1006 O << "void " << Target.getName() << ClassName << "::"
1007 << "printCustomAliasOperand(\n"
1008 << " const MCInst *MI, unsigned OpIdx,\n"
1009 << " unsigned PrintMethodIdx, raw_ostream &OS) {\n"
1010 << " switch (PrintMethodIdx) {\n"
1011 << " default:\n"
1012 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"
1013 << " break;\n";
1014
1015 for (unsigned i = 0; i < PrintMethods.size(); ++i) {
1016 O << " case " << i << ":\n"
1017 << " " << PrintMethods[i] << "(MI, OpIdx, OS);\n"
1018 << " break;\n";
1019 }
1020
1021 O << " }\n"
1022 << "}\n\n";
9621023
9631024 O << "#endif // PRINT_ALIAS_INSTR\n";
9641025 }