llvm.org GIT mirror llvm / d6b4632
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
3 changed file(s) with 42 addition(s) and 38 deletion(s). Raw diff Collapse all Expand all
1919 // ARM Subtarget features.
2020 //
2121
22 def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
23 "ARM v4T">;
24 def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
25 "ARM v5T">;
26 def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
27 "ARM v5TE, v5TEj, v5TExp">;
28 def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
29 "ARM v6">;
30 def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
31 "ARM v6t2">;
32 def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
33 "ARM v7A">;
34 def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
35 "ARM v7M">;
3622 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
3723 "Enable VFP2 instructions">;
3824 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
4531 "Enable half-precision floating point">;
4632 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
4733 "Enable divide instructions">;
48 def FeatureT2ExtractPack: SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
34 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
4935 "Enable Thumb2 extract and pack instructions">;
50 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
51 "Has data barrier (dmb / dsb) instructions">;
36 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
37 "Has data barrier (dmb / dsb) instructions">;
5238 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
5339 "FP compare + branch is slow">;
5440
5844 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
5945 // others as well. We should do more benchmarking and confirm one way or
6046 // the other.
61 def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
62 "Disable VFP MAC instructions">;
47 def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
48 "Disable VFP MAC instructions">;
6349 // Some processors benefit from using NEON instructions for scalar
6450 // single-precision FP operations.
65 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
66 "true",
67 "Use NEON for single precision FP">;
51 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
52 "true",
53 "Use NEON for single precision FP">;
6854
6955 // Disable 32-bit to 16-bit narrowing for experimentation.
7056 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
7157 "Prefer 32-bit Thumb instrs">;
58
59
60 // ARM architectures.
61 def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
62 "ARM v4T">;
63 def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
64 "ARM v5T">;
65 def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
66 "ARM v5TE, v5TEj, v5TExp">;
67 def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
68 "ARM v6">;
69 def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
70 "ARM v6m",
71 [FeatureDB]>;
72 def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
73 "ARM v6t2">;
74 def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
75 "ARM v7A",
76 [FeatureDB]>;
77 def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
78 "ARM v7M",
79 [FeatureDB]>;
7280
7381 //===----------------------------------------------------------------------===//
7482 // ARM Processors supported.
127135 def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
128136
129137 // V6M Processors.
130 def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6, FeatureDB]>;
138 def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
131139
132140 // V6T2 Processors.
133141 def : Processor<"arm1156t2-s", ARMV6Itineraries,
138146 // V7 Processors.
139147 def : Processor<"cortex-a8", CortexA8Itineraries,
140148 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
141 FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2ExtractPack,
142 FeatureDB]>;
149 FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2XtPk]>;
143150 def : Processor<"cortex-a9", CortexA9Itineraries,
144 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2ExtractPack,
145 FeatureDB]>;
151 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2XtPk]>;
146152
147153 // V7M Processors.
148 def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv,
149 FeatureDB]>;
150 def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureThumb2, FeatureHWDiv,
151 FeatureDB]>;
154 def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
155 def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
152156
153157 //===----------------------------------------------------------------------===//
154158 // Register File Description
2525 class ARMSubtarget : public TargetSubtarget {
2626 protected:
2727 enum ARMArchEnum {
28 V4, V4T, V5T, V5TE, V6, V6T2, V7A, V7M
28 V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
2929 };
3030
3131 enum ARMFPEnum {
None ; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6
1 ; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=M0
0 ; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6
1 ; RUN: llc < %s -march=thumb -mattr=+v6m | FileCheck %s -check-prefix=V6M
22
33 declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1 )
44
66 ; V6: t1:
77 ; V6: blx {{_*}}sync_synchronize
88
9 ; M0: t1:
10 ; M0: dsb
9 ; V6M: t1:
10 ; V6M: dsb
1111 call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true )
1212 ret void
1313 }
1616 ; V6: t2:
1717 ; V6: blx {{_*}}sync_synchronize
1818
19 ; M0: t2:
20 ; M0: dmb
19 ; V6M: t2:
20 ; V6M: dmb
2121 call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false )
2222 ret void
2323 }