llvm.org GIT mirror llvm / d67fc42
[Hexagon] Adding basic Hexagon ELF object emitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221465 91177308-0d34-0410-b5e6-96231b3b80d8 Colin LeMahieu 5 years ago
7 changed file(s) with 192 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
0 add_llvm_library(LLVMHexagonDesc
1 HexagonAsmBackend.cpp
2 HexagonELFObjectWriter.cpp
13 HexagonMCAsmInfo.cpp
24 HexagonMCCodeEmitter.cpp
35 HexagonMCInst.cpp
46 HexagonMCTargetDesc.cpp
57 )
68
7 add_dependencies(LLVMHexagonDesc HexagonCommonTableGen)
9 add_dependencies(LLVMHexagonDesc HexagonCommonTableGen)
0 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "HexagonMCTargetDesc.h"
10 #include "llvm/MC/MCAsmBackend.h"
11 #include "llvm/MC/MCELFObjectWriter.h"
12
13 using namespace llvm;
14
15 namespace {
16
17 class HexagonAsmBackend : public MCAsmBackend {
18 public:
19 HexagonAsmBackend(Target const & /*T*/) {}
20
21 unsigned getNumFixupKinds() const override { return 0; }
22
23 void applyFixup(MCFixup const & /*Fixup*/, char * /*Data*/,
24 unsigned /*DataSize*/, uint64_t /*Value*/,
25 bool /*IsPCRel*/) const override {
26 return;
27 }
28
29 bool mayNeedRelaxation(MCInst const & /*Inst*/) const override {
30 return false;
31 }
32
33 bool fixupNeedsRelaxation(MCFixup const & /*Fixup*/, uint64_t /*Value*/,
34 MCRelaxableFragment const * /*DF*/,
35 MCAsmLayout const & /*Layout*/) const override {
36 llvm_unreachable("fixupNeedsRelaxation() unimplemented");
37 }
38
39 void relaxInstruction(MCInst const & /*Inst*/,
40 MCInst & /*Res*/) const override {
41 llvm_unreachable("relaxInstruction() unimplemented");
42 }
43
44 bool writeNopData(uint64_t /*Count*/,
45 MCObjectWriter * /*OW*/) const override {
46 return true;
47 }
48 };
49 } // end anonymous namespace
50
51 namespace {
52 class ELFHexagonAsmBackend : public HexagonAsmBackend {
53 uint8_t OSABI;
54
55 public:
56 ELFHexagonAsmBackend(Target const &T, uint8_t OSABI)
57 : HexagonAsmBackend(T), OSABI(OSABI) {}
58
59 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
60 StringRef CPU("HexagonV4");
61 return createHexagonELFObjectWriter(OS, OSABI, CPU);
62 }
63 };
64 } // end anonymous namespace
65
66 namespace llvm {
67 MCAsmBackend *createHexagonAsmBackend(Target const &T,
68 MCRegisterInfo const & /*MRI*/,
69 StringRef TT, StringRef /*CPU*/) {
70 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
71 return new ELFHexagonAsmBackend(T, OSABI);
72 }
73 }
0 //===-- HexagonELFObjectWriter.cpp - Hexagon Target Descriptions ----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "Hexagon.h"
10 #include "llvm/MC/MCAssembler.h"
11 #include "llvm/MC/MCELFObjectWriter.h"
12 #include "llvm/Support/Debug.h"
13
14 #define DEBUG_TYPE "hexagon-elf-writer"
15
16 using namespace llvm;
17 using namespace Hexagon;
18
19 namespace {
20
21 class HexagonELFObjectWriter : public MCELFObjectTargetWriter {
22 private:
23 StringRef _CPU;
24
25 public:
26 HexagonELFObjectWriter(uint8_t OSABI, StringRef CPU);
27
28 virtual unsigned GetRelocType(MCValue const &Target, MCFixup const &Fixup,
29 bool IsPCRel) const override;
30 };
31 }
32
33 HexagonELFObjectWriter::HexagonELFObjectWriter(uint8_t OSABI, StringRef CPU)
34 : MCELFObjectTargetWriter(/*Is64bit*/ false, OSABI, ELF::EM_HEXAGON,
35 /*HasRelocationAddend*/ true),
36 _CPU(CPU) {}
37
38 unsigned HexagonELFObjectWriter::GetRelocType(MCValue const &/*Target*/,
39 MCFixup const &Fixup,
40 bool IsPCRel) const {
41 unsigned Type = (unsigned)ELF::R_HEX_NONE;
42 llvm::MCFixupKind Kind = Fixup.getKind();
43
44 switch (Kind) {
45 default:
46 DEBUG(dbgs() << "unrecognized relocation " << Fixup.getKind() << "\n");
47 llvm_unreachable("Unimplemented Fixup kind!");
48 break;
49 case FK_Data_4:
50 Type = (IsPCRel) ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32;
51 break;
52 }
53 return Type;
54 }
55
56 MCObjectWriter *llvm::createHexagonELFObjectWriter(raw_ostream &OS,
57 uint8_t OSABI,
58 StringRef CPU) {
59 MCELFObjectTargetWriter *MOTW = new HexagonELFObjectWriter(OSABI, CPU);
60 return createELFObjectWriter(MOTW, OS, /*IsLittleEndian*/ true);
61 }
1414 #include "HexagonMCAsmInfo.h"
1515 #include "InstPrinter/HexagonInstPrinter.h"
1616 #include "llvm/MC/MCCodeGenInfo.h"
17 #include "llvm/MC/MCELFStreamer.h"
1718 #include "llvm/MC/MCInstrInfo.h"
1819 #include "llvm/MC/MCRegisterInfo.h"
1920 #include "llvm/MC/MCStreamer.h"
4546 return X;
4647 }
4748
49 static MCStreamer *
50 createHexagonELFStreamer(MCContext &Context, MCAsmBackend &MAB,
51 raw_ostream &OS, MCCodeEmitter *CE,
52 bool RelaxAll) {
53 MCELFStreamer *ES = new MCELFStreamer(Context, MAB, OS, CE);
54 return ES;
55 }
56
57
4858 static MCSubtargetInfo *
4959 createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) {
5060 MCSubtargetInfo *X = new MCSubtargetInfo();
6373
6474 return MAI;
6575 }
76
77 static MCStreamer *createMCStreamer(Target const &T, StringRef TT,
78 MCContext &Context, MCAsmBackend &MAB,
79 raw_ostream &OS, MCCodeEmitter *Emitter,
80 MCSubtargetInfo const &STI, bool RelaxAll) {
81 MCStreamer *ES = createHexagonELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
82 new MCTargetStreamer(*ES);
83 return ES;
84 }
85
6686
6787 static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM,
6888 CodeModel::Model CM,
110130 // Register the MC Inst Printer
111131 TargetRegistry::RegisterMCInstPrinter(TheHexagonTarget,
112132 createHexagonMCInstPrinter);
133
134 // Register the asm backend
135 TargetRegistry::RegisterMCAsmBackend(TheHexagonTarget,
136 createHexagonAsmBackend);
137
138 // Register the obj streamer
139 TargetRegistry::RegisterMCObjectStreamer(TheHexagonTarget, createMCStreamer);
113140 }
1313 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
1414 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
1515
16 #include
17
1618 namespace llvm {
19 class MCAsmBackend;
1720 class MCCodeEmitter;
1821 class MCContext;
1922 class MCInstrInfo;
23 class MCObjectWriter;
2024 class MCRegisterInfo;
2125 class MCSubtargetInfo;
2226 class Target;
27 class StringRef;
28 class raw_ostream;
2329
2430 extern Target TheHexagonTarget;
2531
26 MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
27 const MCRegisterInfo &MRI,
28 const MCSubtargetInfo &MST,
32 MCCodeEmitter *createHexagonMCCodeEmitter(MCInstrInfo const &MCII,
33 MCRegisterInfo const &MRI,
34 MCSubtargetInfo const &MST,
2935 MCContext &MCT);
36
37 MCAsmBackend *createHexagonAsmBackend(Target const &T,
38 MCRegisterInfo const &MRI, StringRef TT,
39 StringRef CPU);
40
41 MCObjectWriter *createHexagonELFObjectWriter(raw_ostream &OS, uint8_t OSABI,
42 StringRef CPU);
3043
3144 } // End llvm namespace
3245
0 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
1 ;; RUN: | llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s
2
3 ; OBJ: Format: ELF32-hexagon
4 ; OBJ: Arch: hexagon
5 ; OBJ: AddressSize: 32bit
6 ; OBJ: Machine: EM_HEXAGON
0 if not 'Hexagon' in config.root.targets:
1 config.unsupported = True
2