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[PowerPC] 32-bit ELF PIC support This adds initial support for PPC32 ELF PIC (Position Independent Code; the -fPIC variety), thus rectifying a long-standing deficiency in the PowerPC backend. Patch by Justin Hibbits! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213427 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 5 years ago
20 changed file(s) with 396 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
457457 R_PPC_GOT16_LO = 15,
458458 R_PPC_GOT16_HI = 16,
459459 R_PPC_GOT16_HA = 17,
460 R_PPC_PLTREL24 = 18,
460461 R_PPC_REL32 = 26,
461462 R_PPC_TLS = 67,
462463 R_PPC_DTPMOD32 = 68,
518518 LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_LO);
519519 LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_HI);
520520 LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_HA);
521 LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_PLTREL24);
521522 LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL32);
522523 LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_TLS);
523524 LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_DTPMOD32);
8282 llvm_unreachable("Unimplemented");
8383 case PPC::fixup_ppc_br24:
8484 case PPC::fixup_ppc_br24abs:
85 Type = ELF::R_PPC_REL24;
85 switch (Modifier) {
86 default: llvm_unreachable("Unsupported Modifier");
87 case MCSymbolRefExpr::VK_None:
88 Type = ELF::R_PPC_REL24;
89 break;
90 case MCSymbolRefExpr::VK_PLT:
91 Type = ELF::R_PPC_PLTREL24;
92 break;
93 }
8694 break;
8795 case PPC::fixup_ppc_brcond14:
8896 case PPC::fixup_ppc_brcond14abs:
5959 // PPC Specific MachineOperand flags.
6060 MO_NO_FLAG,
6161
62 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
63 /// reference is actually to the "FOO$stub" symbol. This is used for calls
64 /// and jumps to external functions on Tiger and earlier.
65 MO_DARWIN_STUB = 1,
62 /// MO_PLT_OR_STUB - On a symbol operand "FOO", this indicates that the
63 /// reference is actually to the "FOO$stub" or "FOO@plt" symbol. This is
64 /// used for calls and jumps to external functions on Tiger and earlier, and
65 /// for PIC calls on Linux and ELF systems.
66 MO_PLT_OR_STUB = 1,
6667
6768 /// MO_PIC_FLAG - If this bit is set, the symbol reference is relative to
6869 /// the function's picbase, e.g. lo16(symbol-picbase).
1717
1818 #include "PPC.h"
1919 #include "InstPrinter/PPCInstPrinter.h"
20 #include "PPCMachineFunctionInfo.h"
2021 #include "MCTargetDesc/PPCMCExpr.h"
2122 #include "MCTargetDesc/PPCPredicates.h"
2223 #include "PPCSubtarget.h"
2627 #include "llvm/ADT/SmallString.h"
2728 #include "llvm/ADT/StringExtras.h"
2829 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
2931 #include "llvm/CodeGen/MachineFunctionPass.h"
3032 #include "llvm/CodeGen/MachineInstr.h"
3133 #include "llvm/CodeGen/MachineInstrBuilder.h"
99101 }
100102
101103 bool doFinalization(Module &M) override;
104 void EmitStartOfAsmFile(Module &M) override;
102105
103106 void EmitFunctionEntryLabel() override;
104107
329332 OutStreamer.EmitLabel(PICBase);
330333 return;
331334 }
335 case PPC::GetGBRO: {
336 // Get the offset from the GOT Base Register to the GOT
337 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
338 MCSymbol *PICOffset = MF->getInfo()->getPICOffsetSymbol();
339 TmpInst.setOpcode(PPC::LWZ);
340 const MCExpr *Exp =
341 MCSymbolRefExpr::Create(PICOffset, MCSymbolRefExpr::VK_None, OutContext);
342 const MCExpr *PB =
343 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(),
344 MCSymbolRefExpr::VK_None,
345 OutContext);
346 const MCOperand MO = TmpInst.getOperand(1);
347 TmpInst.getOperand(1) = MCOperand::CreateExpr(MCBinaryExpr::CreateSub(Exp,
348 PB,
349 OutContext));
350 TmpInst.addOperand(MO);
351 EmitToStreamer(OutStreamer, TmpInst);
352 return;
353 }
354 case PPC::UpdateGBR: {
355 // Update the GOT Base Register to point to the GOT. It may be possible to
356 // merge this with the PPC::GetGBRO, doing it all in one step.
357 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
358 TmpInst.setOpcode(PPC::ADD4);
359 TmpInst.addOperand(TmpInst.getOperand(0));
360 EmitToStreamer(OutStreamer, TmpInst);
361 return;
362 }
363 case PPC::LWZtoc: {
364 // Transform %X3 = LWZtoc , %X2
365 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
366
367 // Change the opcode to LWZ, and the global address operand to be a
368 // reference to the GOT entry we will synthesize later.
369 TmpInst.setOpcode(PPC::LWZ);
370 const MachineOperand &MO = MI->getOperand(1);
371
372 // Map symbol -> label of TOC entry
373 assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
374 MCSymbol *MOSymbol = nullptr;
375 if (MO.isGlobal())
376 MOSymbol = getSymbol(MO.getGlobal());
377 else if (MO.isCPI())
378 MOSymbol = GetCPISymbol(MO.getIndex());
379 else if (MO.isJTI())
380 MOSymbol = GetJTISymbol(MO.getIndex());
381
382 MCSymbol *TOCEntry = lookUpOrCreateTOCEntry(MOSymbol);
383
384 const MCExpr *Exp =
385 MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_None,
386 OutContext);
387 const MCExpr *PB =
388 MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".L.TOC.")),
389 OutContext);
390 Exp = MCBinaryExpr::CreateSub(Exp, PB, OutContext);
391 TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
392 EmitToStreamer(OutStreamer, TmpInst);
393 return;
394 }
332395 case PPC::LDtocJTI:
333396 case PPC::LDtocCPT:
334397 case PPC::LDtoc: {
716779 EmitToStreamer(OutStreamer, TmpInst);
717780 }
718781
782 void PPCLinuxAsmPrinter::EmitStartOfAsmFile(Module &M) {
783 if (Subtarget.isPPC64() || TM.getRelocationModel() != Reloc::PIC_)
784 return AsmPrinter::EmitStartOfAsmFile(M);
785
786 // FIXME: The use of .got2 assumes large GOT model (-fPIC), which is not
787 // optimal for some cases. We should consider supporting small model (-fpic)
788 // as well in the future.
789 assert(TM.getCodeModel() != CodeModel::Small &&
790 "Small code model PIC is currently unsupported.");
791 OutStreamer.SwitchSection(OutContext.getELFSection(".got2",
792 ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC,
793 SectionKind::getReadOnly()));
794
795 MCSymbol *TOCSym = OutContext.GetOrCreateSymbol(Twine(".L.TOC."));
796 MCSymbol *CurrentPos = OutContext.CreateTempSymbol();
797
798 OutStreamer.EmitLabel(CurrentPos);
799
800 // The GOT pointer points to the middle of the GOT, in order to reference the
801 // entire 64kB range. 0x8000 is the midpoint.
802 const MCExpr *tocExpr =
803 MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(CurrentPos, OutContext),
804 MCConstantExpr::Create(0x8000, OutContext),
805 OutContext);
806
807 OutStreamer.EmitAssignment(TOCSym, tocExpr);
808
809 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
810 }
811
719812 void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() {
720 if (!Subtarget.isPPC64()) // linux/ppc32 - Normal entry label.
813 // linux/ppc32 - Normal entry label.
814 if (!Subtarget.isPPC64() && TM.getRelocationModel() != Reloc::PIC_)
721815 return AsmPrinter::EmitFunctionEntryLabel();
816
817 if (!Subtarget.isPPC64()) {
818 const PPCFunctionInfo *PPCFI = MF->getInfo();
819 if (PPCFI->usesPICBase()) {
820 MCSymbol *RelocSymbol = PPCFI->getPICOffsetSymbol();
821 MCSymbol *PICBase = MF->getPICBaseSymbol();
822 OutStreamer.EmitLabel(RelocSymbol);
823
824 const MCExpr *OffsExpr =
825 MCBinaryExpr::CreateSub(
826 MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".L.TOC.")),
827 OutContext),
828 MCSymbolRefExpr::Create(PICBase, OutContext),
829 OutContext);
830 OutStreamer.EmitValue(OffsExpr, 4);
831 OutStreamer.EmitLabel(CurrentFnSym);
832 return;
833 } else
834 return AsmPrinter::EmitFunctionEntryLabel();
835 }
722836
723837 // Emit an official procedure descriptor.
724838 MCSectionSubPair Current = OutStreamer.getCurrentSection();
758872 PPCTargetStreamer &TS =
759873 static_cast(*OutStreamer.getTargetStreamer());
760874
761 if (isPPC64 && !TOC.empty()) {
762 const MCSectionELF *Section = OutStreamer.getContext().getELFSection(".toc",
875 if (!TOC.empty()) {
876 const MCSectionELF *Section;
877
878 if (isPPC64)
879 Section = OutStreamer.getContext().getELFSection(".toc",
880 ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC,
881 SectionKind::getReadOnly());
882 else
883 Section = OutStreamer.getContext().getELFSection(".got2",
763884 ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC,
764885 SectionKind::getReadOnly());
765886 OutStreamer.SwitchSection(Section);
768889 E = TOC.end(); I != E; ++I) {
769890 OutStreamer.EmitLabel(I->second);
770891 MCSymbol *S = OutContext.GetOrCreateSymbol(I->first->getName());
771 TS.emitTCEntry(*S);
892 if (isPPC64)
893 TS.emitTCEntry(*S);
894 else
895 OutStreamer.EmitSymbolValue(S, 4);
772896 }
773897 }
774898
460460 const PPCRegisterInfo *RegInfo =
461461 static_cast(MF.getTarget().getRegisterInfo());
462462 bool HasBP = RegInfo->hasBasePointer(MF);
463 unsigned BPReg = HasBP ? (unsigned) PPC::R30 : FPReg;
463 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
464464 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
465465
466466 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
505505 DebugLoc dl;
506506 bool needsFrameMoves = MMI.hasDebugInfo() ||
507507 MF.getFunction()->needsUnwindTableEntry();
508 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
508509
509510 // Get processor type.
510511 bool isPPC64 = Subtarget.isPPC64();
545546 bool HasBP = RegInfo->hasBasePointer(MF);
546547
547548 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
548 unsigned BPReg = isPPC64 ? PPC::X30 : PPC::R30;
549 unsigned BPReg = RegInfo->getBaseRegister(MF);
549550 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
550551 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
551552 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
601602 BPOffset = FFI->getObjectOffset(BPIndex);
602603 } else {
603604 BPOffset =
604 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
605 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
606 isDarwinABI,
607 isPIC);
605608 }
606609 }
607610
838841 // Get the ABI.
839842 bool isDarwinABI = Subtarget.isDarwinABI();
840843 bool isSVR4ABI = Subtarget.isSVR4ABI();
844 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
841845
842846 // Check if the link register (LR) has been saved.
843847 PPCFunctionInfo *FI = MF.getInfo();
848852 bool HasBP = RegInfo->hasBasePointer(MF);
849853
850854 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
851 unsigned BPReg = isPPC64 ? PPC::X30 : PPC::R30;
855 unsigned BPReg = RegInfo->getBaseRegister(MF);
852856 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
853857 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
854858 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
889893 BPOffset = FFI->getObjectOffset(BPIndex);
890894 } else {
891895 BPOffset =
892 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
896 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
897 isDarwinABI,
898 isPIC);
893899 }
894900 }
895901
10661072 int FPSI = FI->getFramePointerSaveIndex();
10671073 bool isPPC64 = Subtarget.isPPC64();
10681074 bool isDarwinABI = Subtarget.isDarwinABI();
1075 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
10691076 MachineFrameInfo *MFI = MF.getFrameInfo();
10701077
10711078 // If the frame pointer save index hasn't been defined yet.
10801087
10811088 int BPSI = FI->getBasePointerSaveIndex();
10821089 if (!BPSI && RegInfo->hasBasePointer(MF)) {
1083 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI);
1090 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
10841091 // Allocate the frame index for the base pointer save area.
10851092 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
10861093 // Save the result.
9696
9797 /// getBasePointerSaveOffset - Return the previous frame offset to save the
9898 /// base pointer.
99 static unsigned getBasePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
99 static unsigned getBasePointerSaveOffset(bool isPPC64,
100 bool isDarwinABI,
101 bool isPIC) {
100102 if (isDarwinABI)
101103 return isPPC64 ? -16U : -8U;
102104
103105 // SVR4 ABI: First slot in the general register save area.
104 return isPPC64 ? -16U : -8U;
106 return isPPC64 ? -16U : isPIC ? -12U : -8U;
105107 }
106108
107109 /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
1313
1414 #include "PPC.h"
1515 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
1617 #include "PPCTargetMachine.h"
1718 #include "llvm/CodeGen/MachineFunction.h"
1819 #include "llvm/CodeGen/MachineInstrBuilder.h"
274275 DebugLoc dl;
275276
276277 if (PPCLowering->getPointerTy() == MVT::i32) {
277 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
278 if (PPCSubTarget->isTargetELF())
279 GlobalBaseReg = PPC::R30;
280 else
281 GlobalBaseReg =
282 RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
278283 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
279284 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
285 if (PPCSubTarget->isTargetELF()) {
286 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
287 BuildMI(FirstMBB, MBBI, dl,
288 TII.get(PPC::GetGBRO), TempReg).addReg(GlobalBaseReg);
289 BuildMI(FirstMBB, MBBI, dl,
290 TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg).addReg(TempReg);
291 MF->getInfo()->setUsesPICBase(true);
292 }
280293 } else {
281294 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
282295 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
14441457 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
14451458 }
14461459 case PPCISD::TOC_ENTRY: {
1447 assert (PPCSubTarget->isPPC64() && "Only supported for 64-bit ABI");
1460 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
1461 SDValue GA = N->getOperand(0);
1462 return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
1463 N->getOperand(1));
1464 }
1465 assert (PPCSubTarget->isPPC64() &&
1466 "Only supported for 64-bit ABI and 32-bit SVR4");
14481467
14491468 // For medium and large code model, we generate two instructions as
14501469 // described below. Otherwise we allow SelectCodeCommon to handle this,
14901490 HiOpFlags = PPCII::MO_HA;
14911491 LoOpFlags = PPCII::MO_LO;
14921492
1493 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1494 // non-darwin platform. We don't support PIC on other platforms yet.
1495 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1496 TM.getSubtarget().isDarwin();
1493 // Don't use the pic base if not in PIC relocation model.
1494 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1495
14971496 if (isPIC) {
14981497 HiOpFlags |= PPCII::MO_PIC_FLAG;
14991498 LoOpFlags |= PPCII::MO_PIC_FLAG;
15491548
15501549 unsigned MOHiFlag, MOLoFlag;
15511550 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1551
1552 if (isPIC && Subtarget.isSVR4ABI()) {
1553 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1554 PPCII::MO_PIC_FLAG);
1555 SDLoc DL(CP);
1556 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1557 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1558 }
1559
15521560 SDValue CPIHi =
15531561 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
15541562 SDValue CPILo =
15701578
15711579 unsigned MOHiFlag, MOLoFlag;
15721580 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1581
1582 if (isPIC && Subtarget.isSVR4ABI()) {
1583 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1584 PPCII::MO_PIC_FLAG);
1585 SDLoc DL(GA);
1586 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1587 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1588 }
1589
15731590 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
15741591 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
15751592 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
16981715
16991716 unsigned MOHiFlag, MOLoFlag;
17001717 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1718
1719 if (isPIC && Subtarget.isSVR4ABI()) {
1720 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1721 GSDN->getOffset(),
1722 PPCII::MO_PIC_FLAG);
1723 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1724 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1725 }
17011726
17021727 SDValue GAHi =
17031728 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
33563381 // far-call stubs may be outside relocation limits for a BL instruction.
33573382 if (!DAG.getTarget().getSubtarget().isJITCodeModel()) {
33583383 unsigned OpFlags = 0;
3359 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3384 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
33603385 (Subtarget.getTargetTriple().isMacOSX() &&
33613386 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
33623387 (G->getGlobal()->isDeclaration() ||
3363 G->getGlobal()->isWeakForLinker())) {
3388 G->getGlobal()->isWeakForLinker())) ||
3389 (Subtarget.isTargetELF() && !isPPC64 &&
3390 !G->getGlobal()->hasLocalLinkage() &&
3391 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
33643392 // PC-relative references to external symbols should go through $stub,
33653393 // unless we're building with the leopard linker or later, which
33663394 // automatically synthesizes these stubs.
3367 OpFlags = PPCII::MO_DARWIN_STUB;
3395 OpFlags = PPCII::MO_PLT_OR_STUB;
33683396 }
33693397
33703398 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
33803408 if (ExternalSymbolSDNode *S = dyn_cast(Callee)) {
33813409 unsigned char OpFlags = 0;
33823410
3383 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3384 (Subtarget.getTargetTriple().isMacOSX() &&
3385 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3411 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3412 (Subtarget.getTargetTriple().isMacOSX() &&
3413 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3414 (Subtarget.isTargetELF() && !isPPC64 &&
3415 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
33863416 // PC-relative references to external symbols should go through $stub,
33873417 // unless we're building with the leopard linker or later, which
33883418 // automatically synthesizes these stubs.
3389 OpFlags = PPCII::MO_DARWIN_STUB;
3419 OpFlags = PPCII::MO_PLT_OR_STUB;
33903420 }
33913421
33923422 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
66126642 // Since FP is only updated here but NOT referenced, it's treated as GPR.
66136643 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
66146644 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6615 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6645 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6646 (Subtarget.isSVR4ABI() &&
6647 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6648 PPC::R29 : PPC::R30);
66166649
66176650 MachineInstrBuilder MIB;
66186651
5656 SDTCisPtrTy<0>, SDTCisVT<1, i32>
5757 ]>;
5858
59 def tocentry32 : Operand {
60 let MIOperandInfo = (ops i32imm:$imm);
61 }
5962
6063 //===----------------------------------------------------------------------===//
6164 // PowerPC specific DAG Nodes.
23992402 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
24002403 (ADD4TLS $in, tglobaltlsaddr:$g)>;
24012404
2405 // Support for Position-independent code
2406 def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2407 "#LWZtoc",
2408 [(set i32:$rD,
2409 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2410 // Get Global (GOT) Base Register offset, from the word immediately preceding
2411 // the function label.
2412 def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
2413 // Update the Global(GOT) Base Register with the above offset.
2414 def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2415
2416
24022417 // Standard shifts. These are represented separately from the real shifts above
24032418 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
24042419 // amounts.
1212 //===----------------------------------------------------------------------===//
1313
1414 #include "PPC.h"
15 #include "PPCSubtarget.h"
1516 #include "MCTargetDesc/PPCMCExpr.h"
1617 #include "llvm/ADT/SmallString.h"
1718 #include "llvm/ADT/Twine.h"
3839 Mangler *Mang = AP.Mang;
3940 const DataLayout *DL = TM.getDataLayout();
4041 MCContext &Ctx = AP.OutContext;
42 bool isDarwin = TM.getSubtarget().isDarwin();
4143
4244 SmallString<128> Name;
4345 StringRef Suffix;
44 if (MO.getTargetFlags() == PPCII::MO_DARWIN_STUB)
45 Suffix = "$stub";
46 else if (MO.getTargetFlags() & PPCII::MO_NLP_FLAG)
46 if (MO.getTargetFlags() == PPCII::MO_PLT_OR_STUB) {
47 if (isDarwin)
48 Suffix = "$stub";
49 } else if (MO.getTargetFlags() & PPCII::MO_NLP_FLAG)
4750 Suffix = "$non_lazy_ptr";
4851
4952 if (!Suffix.empty())
6770
6871 // If the target flags on the operand changes the name of the symbol, do that
6972 // before we return the symbol.
70 if (MO.getTargetFlags() == PPCII::MO_DARWIN_STUB) {
73 if (MO.getTargetFlags() == PPCII::MO_PLT_OR_STUB && isDarwin) {
7174 MachineModuleInfoImpl::StubValueTy &StubSym =
7275 getMachOMMI(AP).getFnStubEntry(Sym);
7376 if (StubSym.getPointer())
135138 break;
136139 }
137140
141 if (MO.getTargetFlags() == PPCII::MO_PLT_OR_STUB && !isDarwin)
142 RefKind = MCSymbolRefExpr::VK_PLT;
143
138144 const MCExpr *Expr = MCSymbolRefExpr::Create(Symbol, RefKind, Ctx);
139145
140146 if (!MO.isJTI() && MO.getOffset())
77 //===----------------------------------------------------------------------===//
88
99 #include "PPCMachineFunctionInfo.h"
10 #include "llvm/IR/DataLayout.h"
11 #include "llvm/MC/MCContext.h"
12 #include "llvm/Target/TargetMachine.h"
1013
1114 using namespace llvm;
1215
1316 void PPCFunctionInfo::anchor() { }
1417
18 MCSymbol *PPCFunctionInfo::getPICOffsetSymbol() const {
19 const DataLayout *DL = MF.getTarget().getDataLayout();
20 return MF.getContext().GetOrCreateSymbol(Twine(DL->getPrivateGlobalPrefix())+
21 Twine(MF.getFunctionNumber())+"$poff");
22 }
9191 /// 64-bit SVR4 ABI.
9292 SmallVector MustSaveCRs;
9393
94 /// Hold onto our MachineFunction context.
95 MachineFunction &MF;
96
97 /// Whether this uses the PIC Base register or not.
98 bool UsesPICBase;
99
94100 public:
95101 explicit PPCFunctionInfo(MachineFunction &MF)
96102 : FramePointerSaveIndex(0),
108114 VarArgsStackOffset(0),
109115 VarArgsNumGPR(0),
110116 VarArgsNumFPR(0),
111 CRSpillFrameIndex(0) {}
117 CRSpillFrameIndex(0),
118 MF(MF),
119 UsesPICBase(0) {}
112120
113121 int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
114122 void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
169177 const SmallVectorImpl &
170178 getMustSaveCRs() const { return MustSaveCRs; }
171179 void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); }
180
181 void setUsesPICBase(bool uses) { UsesPICBase = uses; }
182 bool usesPICBase() const { return UsesPICBase; }
183
184 MCSymbol *getPICOffsetSymbol() const;
172185 };
173186
174187 } // end of namespace llvm
198198 if (PPCFI->needsFP(MF))
199199 Reserved.set(PPC::R31);
200200
201 if (hasBasePointer(MF))
201 if (hasBasePointer(MF)) {
202 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() &&
203 MF.getTarget().getRelocationModel() == Reloc::PIC_)
204 Reserved.set(PPC::R29);
205 else
206 Reserved.set(PPC::R30);
207 }
208
209 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() &&
210 MF.getTarget().getRelocationModel() == Reloc::PIC_)
202211 Reserved.set(PPC::R30);
203212
204213 // Reserve Altivec registers when Altivec is unavailable.
842851 if (!hasBasePointer(MF))
843852 return getFrameRegister(MF);
844853
845 return Subtarget.isPPC64() ? PPC::X30 : PPC::R30;
854 if (Subtarget.isPPC64())
855 return PPC::X30;
856
857 if (Subtarget.isSVR4ABI() &&
858 MF.getTarget().getRelocationModel() == Reloc::PIC_)
859 return PPC::R29;
860
861 return PPC::R30;
846862 }
847863
848864 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
221221 /// isBGQ - True if this is a BG/Q platform.
222222 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
223223
224 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
225 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
226
224227 bool isDarwinABI() const { return isDarwin(); }
225228 bool isSVR4ABI() const { return !isDarwin(); }
226229
0 ; RUN: llc < %s -relocation-model=static | FileCheck %s -check-prefix=STATIC
1 ; RUN: llc < %s -relocation-model=pic | FileCheck %s -check-prefix=PIC
1 ; RUN: llc < %s -relocation-model=pic -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PIC
2 ; RUN: llc < %s -relocation-model=pic -mtriple=powerpc-unknown-linux | FileCheck %s -check-prefix=PICELF
23 ; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-apple-darwin8 | FileCheck %s -check-prefix=PIC64
3 ; RUN: llc < %s -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC
4 ; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=DYNAMIC
45 ; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=powerpc64-apple-darwin8 | FileCheck %s -check-prefix=DYNAMIC64
56 ; PR4482
67 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
1617 ; PIC: _foo:
1718 ; PIC: bl L_exact_log2$stub
1819 ; PIC: blr
20
21 ; PICELF: foo:
22 ; PICELF: bl exact_log2@PLT
23 ; PICELF: blr
1924
2025 ; PIC64: _foo:
2126 ; PIC64: bl L_exact_log2$stub
0 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck %s
1 @foobar = common global i32 0, align 4
2
3 define i32 @foo() {
4 entry:
5 %0 = load i32* @foobar, align 4
6 ret i32 %0
7 }
8
9 ; CHECK: [[POFF:\.L[0-9]+\$poff]]:
10 ; CHECK-NEXT: .long .L.TOC.-[[PB:\.L[0-9]+\$pb]]
11 ; CHECK-NEXT: foo:
12 ; CHECK: bl [[PB]]
13 ; CHECK-NEXT: [[PB]]:
14 ; CHECK: mflr 30
15 ; CHECK: lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30)
16 ; CHECK-NEXT: add 30, [[REG]], 30
17 ; CHECK: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.L.TOC.(30)
18 ; CHECK: lwz {{[0-9]+}}, 0([[VREG]])
19 ; CHECK: [[VREF]]:
20 ; CHECK-NEXT: .long foobar
0 ; Test to make sure that bss sections are printed with '.section' directive.
11 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
2 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=PIC
23
34 @A = global i32 0
45
56 ; CHECK: .section .bss,"aw",@nobits
67 ; CHECK: .globl A
78
9 ; PIC: .section .got2,"aw",@progbits
10 ; PIC: .section .bss,"aw",@nobits
11 ; PIC: .globl A
0 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
11 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-FP %s
2 ; RUN: llc -mtriple=powerpc-unknown-linux-gnu -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-32 %s
3 ; RUN: llc -mtriple=powerpc-unknown-linux-gnu -disable-fp-elim -relocation-model=pic < %s | FileCheck -check-prefix=CHECK-32-PIC %s
24 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
35 target triple = "powerpc64-unknown-linux-gnu"
46
57 %struct.s = type { i32, i32 }
68
79 declare void @bar(i32*)
10
11 @barbaz = external global i32
812
913 define void @goo(%struct.s* byval nocapture readonly %a) {
1014 entry:
1519 store i32 %0, i32* %arrayidx, align 32
1620 %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
1721 %1 = load i32* %b, align 4
22 %2 = load i32* @barbaz, align 4
1823 %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
19 store i32 %1, i32* %arrayidx2, align 4
24 store i32 %2, i32* %arrayidx2, align 4
2025 call void @bar(i32* %arrayidx)
2126 ret void
2227 }
6873 ; CHECK-FP-DAG: mtlr 0
6974 ; CHECK-FP: blr
7075
76 ; CHECK-32-LABEL: @goo
77 ; CHECK-32-DAG: mflr 0
78 ; CHECK-32-DAG: rlwinm [[REG:[0-9]+]], 1, 0, 27, 31
79 ; CHECK-32-DAG: stw 30, -8(1)
80 ; CHECK-32-DAG: mr 30, 1
81 ; CHECK-32-DAG: stw 0, 4(1)
82 ; CHECK-32-DAG: subfic 0, [[REG]], -64
83 ; CHECK-32: stwux 1, 1, 0
84
85 ; CHECK-32-PIC-LABEL: @goo
86 ; CHECK-32-PIC-DAG: mflr 0
87 ; CHECK-32-PIC-DAG: rlwinm [[REG:[0-9]+]], 1, 0, 27, 31
88 ; CHECK-32-PIC-DAG: stw 29, -12(1)
89 ; CHECK-32-PIC-DAG: mr 29, 1
90 ; CHECK-32-PIC-DAG: stw 0, 4(1)
91 ; CHECK-32-PIC-DAG: subfic 0, [[REG]], -64
92 ; CHECK-32-PIC: stwux 1, 1, 0
93
7194 ; The large-frame-size case.
7295 define void @hoo(%struct.s* byval nocapture readonly %a) {
7396 entry:
97120 ; CHECK: stdux 1, 1, 0
98121
99122 ; CHECK: blr
123
124 ; CHECK-32-LABEL: @hoo
125
126 ; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13
127 ; CHECK-32-DAG: rlwinm [[REG3:[0-9]+]], 1, 0, 27, 31
128 ; CHECK-32-DAG: mflr 0
129 ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
130 ; CHECK-32-DAG: stw 30, -8(1)
131 ; CHECK-32-DAG: mr 30, 1
132 ; CHECK-32-DAG: stw 0, 4(1)
133 ; CHECK-32-DAG: subfc 0, [[REG3]], [[REG2]]
134 ; CHECK-32: stwux 1, 1, 0
135
136 ; CHECK-32: blr
137
138 ; CHECK-32-PIC-LABEL: @hoo
139
140 ; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13
141 ; CHECK-32-PIC-DAG: rlwinm [[REG3:[0-9]+]], 1, 0, 27, 31
142 ; CHECK-32-PIC-DAG: mflr 0
143 ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
144 ; CHECK-32-PIC-DAG: stw 29, -12(1)
145 ; CHECK-32-PIC-DAG: mr 29, 1
146 ; CHECK-32-PIC-DAG: stw 0, 4(1)
147 ; CHECK-32-PIC-DAG: subfc 0, [[REG3]], [[REG2]]
148 ; CHECK-32: stwux 1, 1, 0
149
150 ; CHECK-32: blr
100151
101152 ; Make sure that the FP save area is still allocated correctly relative to
102153 ; where r30 is saved.
0 # RUN: llvm-mc -triple=powerpc-unknown-linux-gnu -filetype=obj %s | \
1 # RUN: llvm-readobj -r | FileCheck %s
2 .section .text
3
4 .globl foo
5 .type foo,@function
6 .align 2
7 foo:
8 bl printf@plt
9 .LC1:
10 .size foo, . - foo
11
12 # CHECK: Relocations [
13 # CHECK-NEXT: Section (2) .rela.text {
14 # CHECK-NEXT: 0x0 R_PPC_PLTREL24 printf 0x0
15 # CHECK-NEXT: }
16 # CHECK-NEXT: ]