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Merging r236099: ------------------------------------------------------------------------ r236099 | dsanders | 2015-04-29 13:28:58 +0100 (Wed, 29 Apr 2015) | 13 lines [mips] Correct 128-bit shifts on 64-bit targets. Summary: The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now accounts for both cases. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, mohit.bhakkad, sagar Differential Revision: http://reviews.llvm.org/D9337 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236215 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 5 years ago
4 changed file(s) with 17 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
20682068 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
20692069 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
20702070 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2071 DAG.getConstant(0x20, MVT::i32));
2071 DAG.getConstant(VT.getSizeInBits(), MVT::i32));
20722072 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
20732073 DAG.getConstant(0, VT), ShiftLeftLo);
20742074 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
21072107 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
21082108 DL, VT, Hi, Shamt);
21092109 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2110 DAG.getConstant(0x20, MVT::i32));
2111 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
2110 DAG.getConstant(VT.getSizeInBits(), MVT::i32));
2111 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2112 DAG.getConstant(VT.getSizeInBits() - 1, VT));
21122113 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
21132114 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2114 IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
2115 IsSRA ? Ext : DAG.getConstant(0, VT), ShiftRightHi);
21152116
21162117 SDValue Ops[2] = {Lo, Hi};
21172118 return DAG.getMergeValues(Ops, DL);
134134
135135 ; M3: sll $[[T0:[0-9]+]], $7, 0
136136 ; M3: dsrav $[[T1:[0-9]+]], $4, $[[T0]]
137 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
137 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
138138 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
139139 ; M3: move $3, $[[T1]]
140140 ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]]
145145 ; M3: $[[BB0]]:
146146 ; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]]
147147 ; M3: nop
148 ; M3: dsra $2, $4, 31
148 ; M3: dsra $2, $4, 63
149149 ; M3: $[[BB1]]:
150150 ; M3: jr $ra
151151 ; M3: nop
157157 ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
158158 ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]]
159159 ; GP64-NOT-R6: dsrav $2, $4, $[[T0]]
160 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32
160 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 64
161161
162162 ; GP64-NOT-R6: movn $3, $2, $[[T5]]
163 ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31
163 ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 63
164164 ; GP64-NOT-R6: jr $ra
165165 ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]]
166166
167167 ; 64R6: sll $[[T0:[0-9]+]], $7, 0
168168 ; 64R6: dsrav $[[T1:[0-9]+]], $4, $[[T0]]
169 ; 64R6: andi $[[T2:[0-9]+]], $[[T0]], 32
169 ; 64R6: andi $[[T2:[0-9]+]], $[[T0]], 64
170170 ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0
171171 ; 64R6: seleqz $[[T4:[0-9]+]], $[[T1]], $[[T3]]
172 ; 64R6: dsra $[[T5:[0-9]+]], $4, 31
172 ; 64R6: dsra $[[T5:[0-9]+]], $4, 63
173173 ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]]
174174 ; 64R6: or $2, $[[T6]], $[[T4]]
175175 ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $[[T0]]
127127
128128 ; M3: sll $[[T0:[0-9]+]], $7, 0
129129 ; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]]
130 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
130 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
131131 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
132132 ; M3: move $3, $[[T1]]
133133 ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]]
150150 ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
151151 ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]]
152152 ; GP64-NOT-R6: dsrlv $2, $4, $[[T0]]
153 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32
153 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 64
154154 ; GP64-NOT-R6: movn $3, $2, $[[T5]]
155155 ; GP64-NOT-R6: jr $ra
156156 ; GP64-NOT-R6: movn $2, $zero, $1
161161 ; 64R6: not $[[T3:[0-9]+]], $[[T0]]
162162 ; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
163163 ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]]
164 ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32
164 ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 64
165165 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
166166 ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
167167 ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]]
139139
140140 ; M3: sll $[[T0:[0-9]+]], $7, 0
141141 ; M3: dsllv $[[T1:[0-9]+]], $5, $[[T0]]
142 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
142 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
143143 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
144144 ; M3: move $2, $[[T1]]
145145 ; M3: dsllv $[[T4:[0-9]+]], $4, $[[T0]]
162162 ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
163163 ; GP64-NOT-R6: or $2, $[[T1]], $[[T4]]
164164 ; GP64-NOT-R6: dsllv $3, $5, $[[T0]]
165 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32
165 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 64
166166 ; GP64-NOT-R6: movn $2, $3, $[[T5]]
167167 ; GP64-NOT-R6: jr $ra
168168 ; GP64-NOT-R6: movn $3, $zero, $1
173173 ; 64R6: not $[[T3:[0-9]+]], $[[T0]]
174174 ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
175175 ; 64R6: or $[[T5:[0-9]+]], $[[T1]], $[[T4]]
176 ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32
176 ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 64
177177 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
178178 ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
179179 ; 64R6: dsllv $[[T9:[0-9]+]], $5, $[[T0]]