llvm.org GIT mirror llvm / d62e7ad
[X86][Disassembler] Clamp index to 4-bits when decoding GPR registers. A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333725 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 2 years ago
2 changed file(s) with 5 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
14581458 case TYPE_Rv: \
14591459 return base + index; \
14601460 case TYPE_R8: \
1461 index &= 0xf; \
14611462 if (insn->rexPrefix && \
14621463 index >= 4 && index <= 7) { \
14631464 return prefix##_SPL + (index - 4); \
14651466 return prefix##_AL + index; \
14661467 } \
14671468 case TYPE_R16: \
1468 return prefix##_AX + index; \
1469 return prefix##_AX + (index & 0xf); \
14691470 case TYPE_R32: \
1470 return prefix##_EAX + index; \
1471 return prefix##_EAX + (index & 0xf); \
14711472 case TYPE_R64: \
1472 return prefix##_RAX + index; \
1473 return prefix##_RAX + (index & 0xf); \
14731474 case TYPE_ZMM: \
14741475 return prefix##_ZMM0 + index; \
14751476 case TYPE_YMM: \
580580 #CHECK: vaddps (%rax), %xmm16, %xmm1
581581 0x62 0xb1 0x7c 0x00 0x58 0x08
582582
583 #CHECK: vcvtusi2sdq %mm0, %xmm1, %xmm1
583 #CHECK: vcvtusi2sdq %rax, %xmm1, %xmm1
584584 0x62 0xb1 0xf7 0x08 0x7b 0xc8