llvm.org GIT mirror llvm / d628f19
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev. Remove the old functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202636 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 5 years ago
136 changed file(s) with 484 addition(s) and 552 deletion(s). Raw diff Collapse all Expand all
1616 #ifndef LLVM_ADT_MAPVECTOR_H
1717 #define LLVM_ADT_MAPVECTOR_H
1818
19 #include "llvm/ADT/ArrayRef.h"
2019 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/STLExtras.h"
2220 #include
2321
2422 namespace llvm {
9694 if (Result.second) {
9795 Vector.push_back(std::make_pair(KV.first, KV.second));
9896 I = Vector.size() - 1;
99 return std::make_pair(llvm::prior(end()), true);
97 return std::make_pair(std::prev(end()), true);
10098 }
10199 return std::make_pair(begin() + I, false);
102100 }
138138 template
139139 inline mapped_iterator map_iterator(const ItTy &I, FuncTy F) {
140140 return mapped_iterator(I, F);
141 }
142
143
144 // next/prior - These functions unlike std::advance do not modify the
145 // passed iterator but return a copy.
146 //
147 // next(myIt) returns copy of myIt incremented once
148 // next(myIt, n) returns copy of myIt incremented n times
149 // prior(myIt) returns copy of myIt decremented once
150 // prior(myIt, n) returns copy of myIt decremented n times
151
152 template
153 inline ItTy next(ItTy it, Dist n)
154 {
155 std::advance(it, n);
156 return it;
157 }
158
159 template
160 inline ItTy next(ItTy it)
161 {
162 return ++it;
163 }
164
165 template
166 inline ItTy prior(ItTy it, Dist n)
167 {
168 std::advance(it, -n);
169 return it;
170 }
171
172 template
173 inline ItTy prior(ItTy it)
174 {
175 return --it;
176141 }
177142
178143 //===----------------------------------------------------------------------===//
1111
1212 #include "llvm/ADT/ArrayRef.h"
1313 #include "llvm/ADT/PointerUnion.h"
14 #include "llvm/ADT/STLExtras.h"
1514 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/Support/Compiler.h"
1715
1816 namespace llvm {
1917
247245 assert(I <= this->end() && "Inserting past the end of the vector.");
248246 if (I == end()) {
249247 push_back(Elt);
250 return llvm::prior(end());
248 return std::prev(end());
251249 }
252250 assert(!Val.isNull() && "Null value with non-end insert iterator.");
253251 if (EltTy V = Val.template dyn_cast()) {
270268 // If we have a single value, convert to a vector.
271269 ptrdiff_t Offset = I - begin();
272270 if (Val.isNull()) {
273 if (llvm::next(From) == To) {
271 if (std::next(From) == To) {
274272 Val = *From;
275273 return begin();
276274 }
502502 ///
503503 /// If I points to a bundle of instructions, they are all erased.
504504 iterator erase(iterator I) {
505 return erase(I, llvm::next(I));
505 return erase(I, std::next(I));
506506 }
507507
508508 /// Remove an instruction from the instruction list and delete it.
541541 void splice(iterator Where, MachineBasicBlock *Other, iterator From) {
542542 // The range splice() doesn't allow noop moves, but this one does.
543543 if (Where != From)
544 splice(Where, Other, From, llvm::next(From));
544 splice(Where, Other, From, std::next(From));
545545 }
546546
547547 /// Take a block of instructions from MBB 'Other' in the range [From, To),
749749 MachineInstrSpan(MachineBasicBlock::iterator I)
750750 : MBB(*I->getParent()),
751751 I(I),
752 B(I == MBB.begin() ? MBB.end() : llvm::prior(I)),
753 E(llvm::next(I)) {}
752 B(I == MBB.begin() ? MBB.end() : std::prev(I)),
753 E(std::next(I)) {}
754754
755755 MachineBasicBlock::iterator begin() {
756 return B == MBB.end() ? MBB.begin() : llvm::next(B);
756 return B == MBB.end() ? MBB.begin() : std::next(B);
757757 }
758758 MachineBasicBlock::iterator end() { return E; }
759759 bool empty() { return begin() == end(); }
407407 /// hasOneUse - Return true if there is exactly one use of this node.
408408 ///
409409 bool hasOneUse() const {
410 return !use_empty() && llvm::next(use_begin()) == use_end();
410 return !use_empty() && std::next(use_begin()) == use_end();
411411 }
412412
413413 /// use_size - Return the number of uses of this node. This method takes
544544 std::lower_bound(idx2MBBMap.begin(), idx2MBBMap.end(), start);
545545
546546 if (itr == idx2MBBMap.end()) {
547 itr = prior(itr);
547 itr = std::prev(itr);
548548 return itr->second;
549549 }
550550
552552 if (itr->first < end)
553553 return 0;
554554
555 itr = prior(itr);
555 itr = std::prev(itr);
556556
557557 if (itr->first <= start)
558558 return itr->second;
580580 if (Late) {
581581 // Insert mi's index immediately before the following instruction.
582582 nextItr = getIndexAfter(mi).listEntry();
583 prevItr = prior(nextItr);
583 prevItr = std::prev(nextItr);
584584 } else {
585585 // Insert mi's index immediately after the preceding instruction.
586586 prevItr = getIndexBefore(mi).listEntry();
587 nextItr = llvm::next(prevItr);
587 nextItr = std::next(prevItr);
588588 }
589589
590590 // Get a number for the new instr, or 0 if there's no room currently.
637637 /// Add the given MachineBasicBlock into the maps.
638638 void insertMBBInMaps(MachineBasicBlock *mbb) {
639639 MachineFunction::iterator nextMBB =
640 llvm::next(MachineFunction::iterator(mbb));
640 std::next(MachineFunction::iterator(mbb));
641641
642642 IndexListEntry *startEntry = 0;
643643 IndexListEntry *endEntry = 0;
602602 void Lint::visitUnreachableInst(UnreachableInst &I) {
603603 // This isn't undefined behavior, it's merely suspicious.
604604 Assert1(&I == I.getParent()->begin() ||
605 prior(BasicBlock::iterator(&I))->mayHaveSideEffects(),
605 std::prev(BasicBlock::iterator(&I))->mayHaveSideEffects(),
606606 "Unusual: unreachable immediately preceded by instruction without "
607607 "side effects", &I);
608608 }
526526 /// nested within unloop.
527527 void UnloopUpdater::updateSubloopParents() {
528528 while (!Unloop->empty()) {
529 Loop *Subloop = *llvm::prior(Unloop->end());
530 Unloop->removeChildLoop(llvm::prior(Unloop->end()));
529 Loop *Subloop = *std::prev(Unloop->end());
530 Unloop->removeChildLoop(std::prev(Unloop->end()));
531531
532532 assert(SubloopParents.count(Subloop) && "DFS failed to visit subloop");
533533 if (Loop *Parent = SubloopParents[Subloop])
651651
652652 // Move all of the subloops to the top-level.
653653 while (!Unloop->empty())
654 LI.addTopLevelLoop(Unloop->removeChildLoop(llvm::prior(Unloop->end())));
654 LI.addTopLevelLoop(Unloop->removeChildLoop(std::prev(Unloop->end())));
655655
656656 return;
657657 }
692692 NonLocalDepInfo::iterator Entry =
693693 std::upper_bound(Cache.begin(), Cache.begin()+NumSortedEntries,
694694 NonLocalDepEntry(DirtyBB));
695 if (Entry != Cache.begin() && prior(Entry)->getBB() == DirtyBB)
695 if (Entry != Cache.begin() && std::prev(Entry)->getBB() == DirtyBB)
696696 --Entry;
697697
698698 NonLocalDepEntry *ExistingResult = 0;
192192 for (SCEVNAryExpr::op_iterator I = NAry->op_begin(), E = NAry->op_end();
193193 I != E; ++I) {
194194 OS << **I;
195 if (llvm::next(I) != E)
195 if (std::next(I) != E)
196196 OS << OpStr;
197197 }
198198 OS << ")";
32573257
32583258 const SCEV *TotalOffset = getConstant(IntPtrTy, 0);
32593259 gep_type_iterator GTI = gep_type_begin(GEP);
3260 for (GetElementPtrInst::op_iterator I = llvm::next(GEP->op_begin()),
3260 for (GetElementPtrInst::op_iterator I = std::next(GEP->op_begin()),
32613261 E = GEP->op_end();
32623262 I != E; ++I) {
32633263 Value *Index = *I;
13901390 Value *V = expand(SE.getAddRecExpr(NewOps, S->getLoop(),
13911391 S->getNoWrapFlags(SCEV::FlagNW)));
13921392 BasicBlock::iterator NewInsertPt =
1393 llvm::next(BasicBlock::iterator(cast(V)));
1393 std::next(BasicBlock::iterator(cast(V)));
13941394 BuilderType::InsertPointGuard Guard(Builder);
13951395 while (isa(NewInsertPt) || isa(NewInsertPt) ||
13961396 isa(NewInsertPt))
16181618 while (InsertPt != Builder.GetInsertPoint()
16191619 && (isInsertedInstruction(InsertPt)
16201620 || isa(InsertPt))) {
1621 InsertPt = llvm::next(BasicBlock::iterator(InsertPt));
1621 InsertPt = std::next(BasicBlock::iterator(InsertPt));
16221622 }
16231623 break;
16241624 }
497497 // chain interposes between I and the return.
498498 if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
499499 !isSafeToSpeculativelyExecute(I))
500 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
501 --BBI) {
500 for (BasicBlock::const_iterator BBI = std::prev(ExitBB->end(), 2);; --BBI) {
502501 if (&*BBI == I)
503502 break;
504503 // Debug info intrinsics do not get in the way of tail call optimization.
15911591
15921592 // Terminate old register assignments that don't reach MI;
15931593 MachineFunction::const_iterator PrevMBB = Prev->getParent();
1594 if (PrevMBB != I && (!AtBlockEntry || llvm::next(PrevMBB) != I) &&
1594 if (PrevMBB != I && (!AtBlockEntry || std::next(PrevMBB) != I) &&
15951595 isDbgValueInDefinedReg(Prev)) {
15961596 // Previous register assignment needs to terminate at the end of
15971597 // its basic block.
16021602 DEBUG(dbgs() << "Dropping DBG_VALUE for empty range:\n"
16031603 << "\t" << *Prev << "\n");
16041604 History.pop_back();
1605 } else if (llvm::next(PrevMBB) != PrevMBB->getParent()->end())
1605 } else if (std::next(PrevMBB) != PrevMBB->getParent()->end())
16061606 // Terminate after LastMI.
16071607 History.push_back(LastMI);
16081608 }
382382 if (RS) {
383383 RS->enterBasicBlock(CurMBB);
384384 if (!CurMBB->empty())
385 RS->forward(prior(CurMBB->end()));
385 RS->forward(std::prev(CurMBB->end()));
386386 BitVector RegsLiveAtExit(TRI->getNumRegs());
387387 RS->getRegsUsed(RegsLiveAtExit, false);
388388 for (unsigned int i = 0, e = TRI->getNumRegs(); i != e; i++)
461461 static void FixTail(MachineBasicBlock *CurMBB, MachineBasicBlock *SuccBB,
462462 const TargetInstrInfo *TII) {
463463 MachineFunction *MF = CurMBB->getParent();
464 MachineFunction::iterator I = llvm::next(MachineFunction::iterator(CurMBB));
464 MachineFunction::iterator I = std::next(MachineFunction::iterator(CurMBB));
465465 MachineBasicBlock *TBB = 0, *FBB = 0;
466466 SmallVector Cond;
467467 DebugLoc dl; // FIXME: this is nowhere
599599 unsigned maxCommonTailLength = 0U;
600600 SameTails.clear();
601601 MachineBasicBlock::iterator TrialBBI1, TrialBBI2;
602 MPIterator HighestMPIter = prior(MergePotentials.end());
603 for (MPIterator CurMPIter = prior(MergePotentials.end()),
602 MPIterator HighestMPIter = std::prev(MergePotentials.end());
603 for (MPIterator CurMPIter = std::prev(MergePotentials.end()),
604604 B = MergePotentials.begin();
605 CurMPIter != B && CurMPIter->getHash() == CurHash;
606 --CurMPIter) {
607 for (MPIterator I = prior(CurMPIter); I->getHash() == CurHash ; --I) {
605 CurMPIter != B && CurMPIter->getHash() == CurHash; --CurMPIter) {
606 for (MPIterator I = std::prev(CurMPIter); I->getHash() == CurHash; --I) {
608607 unsigned CommonTailLen;
609608 if (ProfitableToMerge(CurMPIter->getBlock(), I->getBlock(),
610609 minCommonTailLength,
633632 MachineBasicBlock *SuccBB,
634633 MachineBasicBlock *PredBB) {
635634 MPIterator CurMPIter, B;
636 for (CurMPIter = prior(MergePotentials.end()), B = MergePotentials.begin();
637 CurMPIter->getHash() == CurHash;
638 --CurMPIter) {
635 for (CurMPIter = std::prev(MergePotentials.end()),
636 B = MergePotentials.begin();
637 CurMPIter->getHash() == CurHash; --CurMPIter) {
639638 // Put the unconditional branch back, if we need one.
640639 MachineBasicBlock *CurMBB = CurMPIter->getBlock();
641640 if (SuccBB && CurMBB != PredBB)
867866 // a compile-time infinite loop repeatedly doing and undoing the same
868867 // transformations.)
869868
870 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
869 for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
871870 I != E; ++I) {
872871 if (I->pred_size() < 2) continue;
873872 SmallPtrSet UniquePreds;
874873 MachineBasicBlock *IBB = I;
875 MachineBasicBlock *PredBB = prior(I);
874 MachineBasicBlock *PredBB = std::prev(I);
876875 MergePotentials.clear();
877876 for (MachineBasicBlock::pred_iterator P = I->pred_begin(),
878877 E2 = I->pred_end();
904903 continue;
905904 // This is the QBB case described above
906905 if (!FBB)
907 FBB = llvm::next(MachineFunction::iterator(PBB));
906 FBB = std::next(MachineFunction::iterator(PBB));
908907 }
909908
910909 // Failing case: the only way IBB can be reached from PBB is via
954953
955954 // Reinsert an unconditional branch if needed. The 1 below can occur as a
956955 // result of removing blocks in TryTailMergeBlocks.
957 PredBB = prior(I); // this may have been changed in TryTailMergeBlocks
956 PredBB = std::prev(I); // this may have been changed in TryTailMergeBlocks
958957 if (MergePotentials.size() == 1 &&
959958 MergePotentials.begin()->getBlock() != PredBB)
960959 FixTail(MergePotentials.begin()->getBlock(), IBB, TII);
973972 // Make sure blocks are numbered in order
974973 MF.RenumberBlocks();
975974
976 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
975 for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
977976 I != E; ) {
978977 MachineBasicBlock *MBB = I++;
979978 MadeChange |= OptimizeBlock(MBB);
10941093
10951094 // Check to see if we can simplify the terminator of the block before this
10961095 // one.
1097 MachineBasicBlock &PrevBB = *prior(MachineFunction::iterator(MBB));
1096 MachineBasicBlock &PrevBB = *std::prev(MachineFunction::iterator(MBB));
10981097
10991098 MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0;
11001099 SmallVector PriorCond;
13931392 // B elsewhere
13941393 // next:
13951394 if (CurFallsThru) {
1396 MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
1395 MachineBasicBlock *NextBB =
1396 std::next(MachineFunction::iterator(MBB));
13971397 CurCond.clear();
13981398 TII->InsertBranch(*MBB, NextBB, 0, CurCond, DebugLoc());
13991399 }
252252 bool CodeGenPrepare::EliminateFallThrough(Function &F) {
253253 bool Changed = false;
254254 // Scan all of the blocks in the function, except for the entry block.
255 for (Function::iterator I = llvm::next(F.begin()), E = F.end(); I != E; ) {
255 for (Function::iterator I = std::next(F.begin()), E = F.end(); I != E;) {
256256 BasicBlock *BB = I++;
257257 // If the destination block has a single pred, then this is a trivial
258258 // edge, just collapse it.
288288 bool CodeGenPrepare::EliminateMostlyEmptyBlocks(Function &F) {
289289 bool MadeChange = false;
290290 // Note that this intentionally skips the entry block.
291 for (Function::iterator I = llvm::next(F.begin()), E = F.end(); I != E; ) {
291 for (Function::iterator I = std::next(F.begin()), E = F.end(); I != E;) {
292292 BasicBlock *BB = I++;
293293
294294 // If this block doesn't end with an uncond branch, ignore it.
129129 MachineRegisterInfo::use_iterator nextI;
130130 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
131131 E = MRI->use_end(); I!=E; I=nextI) {
132 nextI = llvm::next(I); // I is invalidated by the setReg
132 nextI = std::next(I); // I is invalidated by the setReg
133133 MachineOperand& Use = I.getOperand();
134134 MachineInstr *UseMI = Use.getParent();
135135 if (UseMI==MI)
460460 DEBUG(dbgs() << "If-converting " << *PI.PHI);
461461 unsigned DstReg = PI.PHI->getOperand(0).getReg();
462462 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
463 DEBUG(dbgs() << " --> " << *llvm::prior(FirstTerm));
463 DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
464464 PI.PHI->eraseFromParent();
465465 PI.PHI = 0;
466466 }
481481 unsigned PHIDst = PI.PHI->getOperand(0).getReg();
482482 unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
483483 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
484 DEBUG(dbgs() << " --> " << *llvm::prior(FirstTerm));
484 DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
485485
486486 // Rewrite PHI operands TPred -> (DstReg, Head), remove FPred.
487487 for (unsigned i = PI.PHI->getNumOperands(); i != 1; i -= 2) {
920920 /// next block).
921921 static bool canFallThroughTo(MachineBasicBlock *BB, MachineBasicBlock *ToBB) {
922922 MachineFunction::iterator PI = BB;
923 MachineFunction::iterator I = llvm::next(PI);
923 MachineFunction::iterator I = std::next(PI);
924924 MachineFunction::iterator TI = ToBB;
925925 MachineFunction::iterator E = BB->getParent()->end();
926926 while (I != TI) {
10131013 char NextLine = '\n';
10141014 char SlotIndent = '\t';
10151015
1016 if (llvm::next(B) == E) {
1016 if (std::next(B) == E) {
10171017 NextLine = ' ';
10181018 SlotIndent = ' ';
10191019 }
11701170 MachineBasicBlock &MBB = *MI->getParent();
11711171
11721172 MachineInstrSpan MIS(MI);
1173 TII.storeRegToStackSlot(MBB, llvm::next(MI), NewVReg, isKill, StackSlot,
1173 TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot,
11741174 MRI.getRegClass(NewVReg), &TRI);
11751175
1176 LIS.InsertMachineInstrRangeInMaps(llvm::next(MI), MIS.end());
1177
1178 DEBUG(dumpMachineInstrRangeWithSlotIndex(llvm::next(MI), MIS.end(), LIS,
1176 LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end());
1177
1178 DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,
11791179 "spill"));
11801180 ++NumSpills;
11811181 }
118118 SUnit *LatencyPriorityQueue::pop() {
119119 if (empty()) return NULL;
120120 std::vector::iterator Best = Queue.begin();
121 for (std::vector::iterator I = llvm::next(Queue.begin()),
121 for (std::vector::iterator I = std::next(Queue.begin()),
122122 E = Queue.end(); I != E; ++I)
123123 if (Picker(*Best, *I))
124124 Best = I;
125125 SUnit *V = *Best;
126 if (Best != prior(Queue.end()))
126 if (Best != std::prev(Queue.end()))
127127 std::swap(*Best, Queue.back());
128128 Queue.pop_back();
129129 return V;
132132 void LatencyPriorityQueue::remove(SUnit *SU) {
133133 assert(!Queue.empty() && "Queue is empty!");
134134 std::vector::iterator I = std::find(Queue.begin(), Queue.end(), SU);
135 if (I != prior(Queue.end()))
135 if (I != std::prev(Queue.end()))
136136 std::swap(*I, Queue.back());
137137 Queue.pop_back();
138138 }
479479 // DBG_VALUE has no slot index, use the previous instruction instead.
480480 SlotIndex Idx = MBBI == MBB->begin() ?
481481 LIS->getMBBStartIdx(MBB) :
482 LIS->getInstructionIndex(llvm::prior(MBBI)).getRegSlot();
482 LIS->getInstructionIndex(std::prev(MBBI)).getRegSlot();
483483 // Handle consecutive DBG_VALUE instructions with the same slot index.
484484 do {
485485 if (handleDebugValue(MBBI, Idx)) {
913913
914914 // Don't insert anything after the first terminator, though.
915915 return MI->isTerminator() ? MBB->getFirstTerminator() :
916 llvm::next(MachineBasicBlock::iterator(MI));
916 std::next(MachineBasicBlock::iterator(MI));
917917 }
918918
919919 DebugLoc UserValue::findDebugLoc() {
221221 VNInfo *ValNo = I->valno;
222222
223223 // Search for the first segment that we can't merge with.
224 iterator MergeTo = llvm::next(I);
224 iterator MergeTo = std::next(I);
225225 for (; MergeTo != end() && NewEnd >= MergeTo->end; ++MergeTo) {
226226 assert(MergeTo->valno == ValNo && "Cannot merge with differing values!");
227227 }
228228
229229 // If NewEnd was in the middle of a segment, make sure to get its endpoint.
230 I->end = std::max(NewEnd, prior(MergeTo)->end);
230 I->end = std::max(NewEnd, std::prev(MergeTo)->end);
231231
232232 // If the newly formed segment now touches the segment after it and if they
233233 // have the same value number, merge the two segments into one segment.
238238 }
239239
240240 // Erase any dead segments.
241 segments.erase(llvm::next(I), MergeTo);
241 segments.erase(std::next(I), MergeTo);
242242 }
243243
244244
273273 MergeTo->end = I->end;
274274 }
275275
276 segments.erase(llvm::next(MergeTo), llvm::next(I));
276 segments.erase(std::next(MergeTo), std::next(I));
277277 return MergeTo;
278278 }
279279
284284 // If the inserted segment starts in the middle or right at the end of
285285 // another segment, just extend that segment to contain the segment of S.
286286 if (it != begin()) {
287 iterator B = prior(it);
287 iterator B = std::prev(it);
288288 if (S.valno == B->valno) {
289289 if (B->start <= Start && B->end >= Start) {
290290 extendSegmentEndTo(B, End);
388388 I->end = Start; // Trim the old segment.
389389
390390 // Insert the new one.
391 segments.insert(llvm::next(I), Segment(End, OldEnd, ValNo));
391 segments.insert(std::next(I), Segment(End, OldEnd, ValNo));
392392 }
393393
394394 /// removeValNo - Remove all the segments defined by the specified value#.
432432
433433 iterator OutIt = begin();
434434 OutIt->valno = NewVNInfo[LHSValNoAssignments[OutIt->valno->id]];
435 for (iterator I = llvm::next(OutIt), E = end(); I != E; ++I) {
435 for (iterator I = std::next(OutIt), E = end(); I != E; ++I) {
436436 VNInfo* nextValNo = NewVNInfo[LHSValNoAssignments[I->valno->id]];
437437 assert(nextValNo != 0 && "Huh?");
438438
640640 assert(I->valno != 0);
641641 assert(I->valno->id < valnos.size());
642642 assert(I->valno == valnos[I->valno->id]);
643 if (llvm::next(I) != E) {
644 assert(I->end <= llvm::next(I)->start);
645 if (I->end == llvm::next(I)->start)
646 assert(I->valno != llvm::next(I)->valno);
643 if (std::next(I) != E) {
644 assert(I->end <= std::next(I)->start);
645 if (I->end == std::next(I)->start)
646 assert(I->valno != std::next(I)->valno);
647647 }
648648 }
649649 }
873873 // values. The new range should be placed immediately before NewI, move any
874874 // intermediate ranges up.
875875 assert(NewI != I && "Inconsistent iterators");
876 std::copy(llvm::next(I), NewI, I);
877 *llvm::prior(NewI)
876 std::copy(std::next(I), NewI, I);
877 *std::prev(NewI)
878878 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
879879 }
880880
919919 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
920920 // No def, search for the new kill.
921921 // This can never be an early clobber kill since there is no def.
922 llvm::prior(I)->end = findLastUseBefore(Reg).getRegSlot();
922 std::prev(I)->end = findLastUseBefore(Reg).getRegSlot();
923923 return;
924924 }
925925 }
955955
956956 // DefVNI is a dead def. It may have been moved across other values in LR,
957957 // so move I up to NewI. Slide [NewI;I) down one position.
958 std::copy_backward(NewI, I, llvm::next(I));
958 std::copy_backward(NewI, I, std::next(I));
959959 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
960960 }
961961
967967 "No RegMask at OldIdx.");
968968 *RI = NewIdx.getRegSlot();
969969 assert((RI == LIS.RegMaskSlots.begin() ||
970 SlotIndex::isEarlierInstr(*llvm::prior(RI), *RI)) &&
971 "Cannot move regmask instruction above another call");
972 assert((llvm::next(RI) == LIS.RegMaskSlots.end() ||
973 SlotIndex::isEarlierInstr(*RI, *llvm::next(RI))) &&
974 "Cannot move regmask instruction below another call");
970 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
971 "Cannot move regmask instruction above another call");
972 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
973 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
974 "Cannot move regmask instruction below another call");
975975 }
976976
977977 // Return the last use of reg between NewIdx and OldIdx.
11241124 if (LII->end.isDead()) {
11251125 SlotIndex prevStart;
11261126 if (LII != LI.begin())
1127 prevStart = llvm::prior(LII)->start;
1127 prevStart = std::prev(LII)->start;
11281128
11291129 // FIXME: This could be more efficient if there was a
11301130 // removeSegment method that returned an iterator.
625625
626626 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
627627 MachineFunction::const_iterator I(this);
628 return llvm::next(I) == MachineFunction::const_iterator(MBB);
628 return std::next(I) == MachineFunction::const_iterator(MBB);
629629 }
630630
631631 bool MachineBasicBlock::canFallThrough() {
704704 }
705705
706706 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
707 MF->insert(llvm::next(MachineFunction::iterator(this)), NMBB);
707 MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
708708 DEBUG(dbgs() << "Splitting critical edge:"
709709 " BB#" << getNumber()
710710 << " -- BB#" << NMBB->getNumber()
847847 // extend to the end of the new split block.
848848
849849 bool isLastMBB =
850 llvm::next(MachineFunction::iterator(NMBB)) == getParent()->end();
850 std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
851851
852852 SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
853853 SlotIndex PrevIndex = StartIndex.getPrevSlot();
10621062 bool Changed = false;
10631063
10641064 MachineFunction::iterator FallThru =
1065 llvm::next(MachineFunction::iterator(this));
1065 std::next(MachineFunction::iterator(this));
10661066
10671067 if (DestA == 0 && DestB == 0) {
10681068 // Block falls through to successor.
493493
494494 MachineBasicBlock *LoopHeaderBB = BB;
495495 markChainSuccessors(Chain, LoopHeaderBB, BlockWorkList, BlockFilter);
496 BB = *llvm::prior(Chain.end());
496 BB = *std::prev(Chain.end());
497497 for (;;) {
498498 assert(BB);
499499 assert(BlockToChain[BB] == &Chain);
500 assert(*llvm::prior(Chain.end()) == BB);
500 assert(*std::prev(Chain.end()) == BB);
501501
502502 // Look for the best viable successor if there is one to place immediately
503503 // after this block.
528528 << " to " << getBlockNum(BestSucc) << "\n");
529529 markChainSuccessors(SuccChain, LoopHeaderBB, BlockWorkList, BlockFilter);
530530 Chain.merge(BestSucc, &SuccChain);
531 BB = *llvm::prior(Chain.end());
531 BB = *std::prev(Chain.end());
532532 }
533533
534534 DEBUG(dbgs() << "Finished forming chain for header block "
633633 BlockChain &Chain = *BlockToChain[*I];
634634 // Ensure that this block is at the end of a chain; otherwise it could be
635635 // mid-way through an inner loop or a successor of an analyzable branch.
636 if (*I != *llvm::prior(Chain.end()))
636 if (*I != *std::prev(Chain.end()))
637637 continue;
638638
639639 // Now walk the successors. We need to establish whether this has a viable
740740 PI != PE; ++PI) {
741741 BlockChain *PredChain = BlockToChain[*PI];
742742 if (!LoopBlockSet.count(*PI) &&
743 (!PredChain || *PI == *llvm::prior(PredChain->end()))) {
743 (!PredChain || *PI == *std::prev(PredChain->end()))) {
744744 ViableTopFallthrough = true;
745745 break;
746746 }
750750 // bottom is a viable exiting block. If so, bail out as rotating will
751751 // introduce an unnecessary branch.
752752 if (ViableTopFallthrough) {
753 MachineBasicBlock *Bottom = *llvm::prior(LoopChain.end());
753 MachineBasicBlock *Bottom = *std::prev(LoopChain.end());
754754 for (MachineBasicBlock::succ_iterator SI = Bottom->succ_begin(),
755755 SE = Bottom->succ_end();
756756 SI != SE; ++SI) {
766766 if (ExitIt == LoopChain.end())
767767 return;
768768
769 std::rotate(LoopChain.begin(), llvm::next(ExitIt), LoopChain.end());
769 std::rotate(LoopChain.begin(), std::next(ExitIt), LoopChain.end());
770770 }
771771
772772 /// \brief Forms basic block chains from the natural loop structures.
886886 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough())
887887 break;
888888
889 MachineFunction::iterator NextFI(llvm::next(FI));
889 MachineFunction::iterator NextFI(std::next(FI));
890890 MachineBasicBlock *NextBB = NextFI;
891891 // Ensure that the layout successor is a viable block, as we know that
892892 // fallthrough is a possibility.
980980 // Update the terminator of the previous block.
981981 if (BI == FunctionChain.begin())
982982 continue;
983 MachineBasicBlock *PrevBB = llvm::prior(MachineFunction::iterator(*BI));
983 MachineBasicBlock *PrevBB = std::prev(MachineFunction::iterator(*BI));
984984
985985 // FIXME: It would be awesome of updateTerminator would just return rather
986986 // than assert when the branch cannot be analyzed in order to remove this
10521052 const BranchProbability ColdProb(1, 5); // 20%
10531053 BlockFrequency EntryFreq = MBFI->getBlockFreq(F.begin());
10541054 BlockFrequency WeightedEntryFreq = EntryFreq * ColdProb;
1055 for (BlockChain::iterator BI = llvm::next(FunctionChain.begin()),
1055 for (BlockChain::iterator BI = std::next(FunctionChain.begin()),
10561056 BE = FunctionChain.end();
10571057 BI != BE; ++BI) {
10581058 // Don't align non-looping basic blocks. These are unlikely to execute
10781078
10791079 // Check for the existence of a non-layout predecessor which would benefit
10801080 // from aligning this block.
1081 MachineBasicBlock *LayoutPred = *llvm::prior(BI);
1081 MachineBasicBlock *LayoutPred = *std::prev(BI);
10821082
10831083 // Force alignment if all the predecessors are jumps. We already checked
10841084 // that the block isn't cold above.
11001100
11011101 bool MachineBlockPlacement::runOnMachineFunction(MachineFunction &F) {
11021102 // Check for single-block functions and skip them.
1103 if (llvm::next(F.begin()) == F.end())
1103 if (std::next(F.begin()) == F.end())
11041104 return false;
11051105
11061106 MBPI = &getAnalysis();
11681168
11691169 bool MachineBlockPlacementStats::runOnMachineFunction(MachineFunction &F) {
11701170 // Check for single-block functions and skip them.
1171 if (llvm::next(F.begin()) == F.end())
1171 if (std::next(F.begin()) == F.end())
11721172 return false;
11731173
11741174 MBPI = &getAnalysis();
228228 // Next, collect all defs into PhysDefs. If any is already in PhysRefs
229229 // (which currently contains only uses), set the PhysUseDef flag.
230230 PhysUseDef = false;
231 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
231 MachineBasicBlock::const_iterator I = MI; I = std::next(I);
232232 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
233233 const MachineOperand &MO = MI->getOperand(i);
234234 if (!MO.isReg() || !MO.isDef())
279279 }
280280 CrossMBB = true;
281281 }
282 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
282 MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
283283 MachineBasicBlock::const_iterator E = MI;
284284 MachineBasicBlock::const_iterator EE = CSMBB->end();
285285 unsigned LookAheadLeft = LookAheadLimit;
138138 // Figure out the block number this should have.
139139 unsigned BlockNo = 0;
140140 if (MBBI != begin())
141 BlockNo = prior(MBBI)->getNumber()+1;
141 BlockNo = std::prev(MBBI)->getNumber() + 1;
142142
143143 for (; MBBI != E; ++MBBI, ++BlockNo) {
144144 if (MBBI->getNumber() != (int)BlockNo) {
345345 OS << PrintReg(I->first, TRI);
346346 if (I->second)
347347 OS << " in " << PrintReg(I->second, TRI);
348 if (llvm::next(I) != E)
348 if (std::next(I) != E)
349349 OS << ", ";
350350 }
351351 OS << '\n';
16421642 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
16431643 i != e; ++i) {
16441644 OS << **i;
1645 if (llvm::next(i) != e)
1645 if (std::next(i) != e)
16461646 OS << " ";
16471647 }
16481648 }
210210 llvm::finalizeBundle(MachineBasicBlock &MBB,
211211 MachineBasicBlock::instr_iterator FirstMI) {
212212 MachineBasicBlock::instr_iterator E = MBB.instr_end();
213 MachineBasicBlock::instr_iterator LastMI = llvm::next(FirstMI);
213 MachineBasicBlock::instr_iterator LastMI = std::next(FirstMI);
214214 while (LastMI != E && LastMI->isInsideBundle())
215215 ++LastMI;
216216 finalizeBundle(MBB, FirstMI, LastMI);
234234 if (!MII->isInsideBundle())
235235 ++MII;
236236 else {
237 MII = finalizeBundle(MBB, llvm::prior(MII));
237 MII = finalizeBundle(MBB, std::prev(MII));
238238 Changed = true;
239239 }
240240 }
4949 MachineBasicBlock *TopMBB = getHeader();
5050 MachineFunction::iterator Begin = TopMBB->getParent()->begin();
5151 if (TopMBB != Begin) {
52 MachineBasicBlock *PriorMBB = prior(MachineFunction::iterator(TopMBB));
52 MachineBasicBlock *PriorMBB = std::prev(MachineFunction::iterator(TopMBB));
5353 while (contains(PriorMBB)) {
5454 TopMBB = PriorMBB;
5555 if (TopMBB == Begin) break;
56 PriorMBB = prior(MachineFunction::iterator(TopMBB));
56 PriorMBB = std::prev(MachineFunction::iterator(TopMBB));
5757 }
5858 }
5959 return TopMBB;
6262 MachineBasicBlock *MachineLoop::getBottomBlock() {
6363 MachineBasicBlock *BotMBB = getHeader();
6464 MachineFunction::iterator End = BotMBB->getParent()->end();
65 if (BotMBB != prior(End)) {
66 MachineBasicBlock *NextMBB = llvm::next(MachineFunction::iterator(BotMBB));
65 if (BotMBB != std::prev(End)) {
66 MachineBasicBlock *NextMBB = std::next(MachineFunction::iterator(BotMBB));
6767 while (contains(NextMBB)) {
6868 BotMBB = NextMBB;
69 if (BotMBB == llvm::next(MachineFunction::iterator(BotMBB))) break;
70 NextMBB = llvm::next(MachineFunction::iterator(BotMBB));
69 if (BotMBB == std::next(MachineFunction::iterator(BotMBB))) break;
70 NextMBB = std::next(MachineFunction::iterator(BotMBB));
7171 }
7272 }
7373 return BotMBB;
299299 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
300300 // Since we are in SSA form, we can use the first definition.
301301 def_iterator I = def_begin(Reg);
302 assert((I.atEnd() || llvm::next(I) == def_end()) &&
302 assert((I.atEnd() || std::next(I) == def_end()) &&
303303 "getVRegDef assumes a single definition or no definition");
304304 return !I.atEnd() ? &*I : 0;
305305 }
310310 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
311311 if (def_empty(Reg)) return 0;
312312 def_iterator I = def_begin(Reg);
313 if (llvm::next(I) != def_end())
313 if (std::next(I) != def_end())
314314 return 0;
315315 return &*I;
316316 }
407407 RegionEnd != MBB->begin(); RegionEnd = Scheduler.begin()) {
408408
409409 // Avoid decrementing RegionEnd for blocks with no terminator.
410 if (RegionEnd != MBB->end()
411 || isSchedBoundary(llvm::prior(RegionEnd), MBB, MF, TII, IsPostRA)) {
410 if (RegionEnd != MBB->end() ||
411 isSchedBoundary(std::prev(RegionEnd), MBB, MF, TII, IsPostRA)) {
412412 --RegionEnd;
413413 // Count the boundary instruction.
414414 --RemainingInstrs;
419419 unsigned NumRegionInstrs = 0;
420420 MachineBasicBlock::iterator I = RegionEnd;
421421 for(;I != MBB->begin(); --I, --RemainingInstrs, ++NumRegionInstrs) {
422 if (isSchedBoundary(llvm::prior(I), MBB, MF, TII, IsPostRA))
422 if (isSchedBoundary(std::prev(I), MBB, MF, TII, IsPostRA))
423423 break;
424424 }
425425 // Notify the scheduler of the region, even if we may skip scheduling
427427 Scheduler.enterRegion(MBB, I, RegionEnd, NumRegionInstrs);
428428
429429 // Skip empty scheduling regions (0 or 1 schedulable instructions).
430 if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
430 if (I == RegionEnd || I == std::prev(RegionEnd)) {
431431 // Close the current region. Bundle the terminator if needed.
432432 // This invalidates 'RegionEnd' and 'I'.
433433 Scheduler.exitRegion();
769769
770770 for (std::vector >::iterator
771771 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
772 std::pair P = *prior(DI);
772 std::pair P = *std::prev(DI);
773773 MachineInstr *DbgValue = P.first;
774774 MachineBasicBlock::iterator OrigPrevMI = P.second;
775775 if (&*RegionBegin == DbgValue)
776776 ++RegionBegin;
777777 BB->splice(++OrigPrevMI, BB, DbgValue);
778 if (OrigPrevMI == llvm::prior(RegionEnd))
778 if (OrigPrevMI == std::prev(RegionEnd))
779779 RegionEnd = DbgValue;
780780 }
781781 DbgValues.clear();
815815 ScheduleDAGMI::enterRegion(bb, begin, end, regioninstrs);
816816
817817 // For convenience remember the end of the liveness region.
818 LiveRegionEnd =
819 (RegionEnd == bb->end()) ? RegionEnd : llvm::next(RegionEnd);
818 LiveRegionEnd = (RegionEnd == bb->end()) ? RegionEnd : std::next(RegionEnd);
820819
821820 SUPressureDiffs.clear();
822821
14451444 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
14461445 if (GlobalSegment != GlobalLI->begin()) {
14471446 // Two address defs have no hole.
1448 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->end,
1447 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->end,
14491448 GlobalSegment->start)) {
14501449 return;
14511450 }
14521451 // If the prior global segment may be defined by the same two-address
14531452 // instruction that also defines LocalLI, then can't make a hole here.
1454 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->start,
1453 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->start,
14551454 LocalLI->beginIndex())) {
14561455 return;
14571456 }
14581457 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
14591458 // it would be a disconnected component in the live range.
1460 assert(llvm::prior(GlobalSegment)->start < LocalLI->beginIndex() &&
1459 assert(std::prev(GlobalSegment)->start < LocalLI->beginIndex() &&
14611460 "Disconnected LRG within the scheduling region.");
14621461 }
14631462 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
10751075
10761076 // Verify SSA form.
10771077 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1078 llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
1078 std::next(MRI->def_begin(Reg)) != MRI->def_end())
10791079 report("Multiple virtual register defs in SSA form", MO, MONum);
10801080
10811081 // Check LiveInts for a live segment, but only for virtual registers.
185185 // Get an iterator to the first instruction after the last PHI node (this may
186186 // also be the end of the basic block).
187187 MachineBasicBlock::iterator LastPHIIt =
188 prior(MBB.SkipPHIsAndLabels(MBB.begin()));
188 std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
189189
190190 while (MBB.front().isPHI())
191191 LowerPHINode(MBB, LastPHIIt);
221221 MachineBasicBlock::iterator LastPHIIt) {
222222 ++NumLowered;
223223
224 MachineBasicBlock::iterator AfterPHIsIt = llvm::next(LastPHIIt);
224 MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
225225
226226 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
227227 MachineInstr *MPhi = MBB.remove(MBB.begin());
266266
267267 // Update live variable information if there is any.
268268 if (LV) {
269 MachineInstr *PHICopy = prior(AfterPHIsIt);
269 MachineInstr *PHICopy = std::prev(AfterPHIsIt);
270270
271271 if (IncomingReg) {
272272 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
305305
306306 // Update LiveIntervals for the new copy or implicit def.
307307 if (LIS) {
308 MachineInstr *NewInstr = prior(AfterPHIsIt);
308 MachineInstr *NewInstr = std::prev(AfterPHIsIt);
309309 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
310310
311311 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
443443 }
444444 } else {
445445 // We just inserted this copy.
446 KillInst = prior(InsertPos);
446 KillInst = std::prev(InsertPos);
447447 }
448448 }
449449 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
503503 }
504504 } else {
505505 // We just inserted this copy.
506 KillInst = prior(InsertPos);
506 KillInst = std::prev(InsertPos);
507507 }
508508 }
509509 assert(KillInst->readsRegister(SrcReg) &&
305305 MachineBasicBlock::iterator Current = MBB->end();
306306 unsigned Count = MBB->size(), CurrentCount = Count;
307307 for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
308 MachineInstr *MI = llvm::prior(I);
308 MachineInstr *MI = std::prev(I);
309309 --Count;
310310 // Calls are not scheduling boundaries before register allocation, but
311311 // post-ra we don't gain anything by scheduling across calls since we
647647 // Update the Begin iterator, as the first instruction in the block
648648 // may have been scheduled later.
649649 if (i == 0)
650 RegionBegin = prior(RegionEnd);
650 RegionBegin = std::prev(RegionEnd);
651651 }
652652
653653 // Reinsert any remaining debug_values.
654654 for (std::vector >::iterator
655655 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
656 std::pair P = *prior(DI);
656 std::pair P = *std::prev(DI);
657657 MachineInstr *DbgValue = P.first;
658658 MachineBasicBlock::iterator OrigPrivMI = P.second;
659659 BB->splice(++OrigPrivMI, BB, DbgValue);
758758 SPAdj += Size;
759759
760760 MachineBasicBlock::iterator PrevI = BB->end();
761 if (I != BB->begin()) PrevI = prior(I);
761 if (I != BB->begin()) PrevI = std::prev(I);
762762 TFI->eliminateCallFramePseudoInstr(Fn, *BB, I);
763763
764764 // Visit the instructions created by eliminateCallFramePseudoInstr().
765765 if (PrevI == BB->end())
766766 I = BB->begin(); // The replaced instr was the first in the block.
767767 else
768 I = llvm::next(PrevI);
768 I = std::next(PrevI);
769769 continue;
770770 }
771771
848848 I = BB->begin();
849849
850850 MachineInstr *MI = I;
851 MachineBasicBlock::iterator J = llvm::next(I);
852 MachineBasicBlock::iterator P = I == BB->begin() ?
853 MachineBasicBlock::iterator(NULL) : llvm::prior(I);
851 MachineBasicBlock::iterator J = std::next(I);
852 MachineBasicBlock::iterator P =
853 I == BB->begin() ? MachineBasicBlock::iterator(NULL) : std::prev(I);
854854
855855 // RS should process this instruction before we might scavenge at this
856856 // location. This is because we might be replacing a virtual register
893893 // spill code will have been inserted in between I and J. This is a
894894 // problem because we need the spill code before I: Move I to just
895895 // prior to J.
896 if (I != llvm::prior(J)) {
896 if (I != std::prev(J)) {
897897 BB->splice(J, BB, I);
898898
899899 // Before we move I, we need to prepare the RS to visit I again.
263263 const LiveInterval &l1 = lis->getInterval(vr1);
264264 const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1);
265265
266 for (RegSet::const_iterator vr2Itr = llvm::next(vr1Itr);
267 vr2Itr != vrEnd; ++vr2Itr) {
266 for (RegSet::const_iterator vr2Itr = std::next(vr1Itr); vr2Itr != vrEnd;
267 ++vr2Itr) {
268268 unsigned vr2 = *vr2Itr;
269269 const LiveInterval &l2 = lis->getInterval(vr2);
270270 const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2);
800800
801801 MachineBasicBlock *MBB = CopyMI->getParent();
802802 MachineBasicBlock::iterator MII =
803 llvm::next(MachineBasicBlock::iterator(CopyMI));
803 std::next(MachineBasicBlock::iterator(CopyMI));
804804 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI);
805 MachineInstr *NewMI = prior(MII);
805 MachineInstr *NewMI = std::prev(MII);
806806
807807 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
808808 CopyMI->eraseFromParent();
174174 Tracking = true;
175175 } else {
176176 assert(MBBI != MBB->end() && "Already past the end of the basic block!");
177 MBBI = llvm::next(MBBI);
177 MBBI = std::next(MBBI);
178178 }
179179 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
180180
414414 "Cannot scavenge register without an emergency spill slot!");
415415 TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
416416 RC, TRI);
417 MachineBasicBlock::iterator II = prior(I);
417 MachineBasicBlock::iterator II = std::prev(I);
418418
419419 unsigned FIOperandNum = getFrameIndexOperandNum(II);
420420 TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
422422 // Restore the scavenged register before its use (or first terminator).
423423 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
424424 RC, TRI);
425 II = prior(UseMI);
425 II = std::prev(UseMI);
426426
427427 FIOperandNum = getFrameIndexOperandNum(II);
428428 TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
429429 }
430430
431 Scavenged[SI].Restore = prior(UseMI);
431 Scavenged[SI].Restore = std::prev(UseMI);
432432
433433 // Doing this here leads to infinite regress.
434434 // Scavenged[SI].Reg = SReg;
300300
301301 SUnit::pred_iterator BestI = Preds.begin();
302302 unsigned MaxDepth = BestI->getSUnit()->getDepth();
303 for (SUnit::pred_iterator
304 I = llvm::next(BestI), E = Preds.end(); I != E; ++I) {
303 for (SUnit::pred_iterator I = std::next(BestI), E = Preds.end(); I != E;
304 ++I) {
305305 if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth)
306306 BestI = I;
307307 }
783783 MachineInstr *DbgMI = NULL;
784784 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
785785 MII != MIE; --MII) {
786 MachineInstr *MI = prior(MII);
786 MachineInstr *MI = std::prev(MII);
787787 if (MI && DbgMI) {
788788 DbgValues.push_back(std::make_pair(DbgMI, MI));
789789 DbgMI = NULL;
799799 if (RPTracker) {
800800 PressureDiff *PDiff = PDiffs ? &(*PDiffs)[SU->NodeNum] : 0;
801801 RPTracker->recede(/*LiveUses=*/0, PDiff);
802 assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI");
802 assert(RPTracker->getPos() == std::prev(MII) &&
803 "RPTracker can't find MI");
803804 }
804805
805806 assert((CanHandleTerminators || (!MI->isTerminator() && !MI->isLabel())) &&
14261427
14271428 const SDep *backtrack() {
14281429 DFSStack.pop_back();
1429 return DFSStack.empty() ? 0 : llvm::prior(DFSStack.back().second);
1430 return DFSStack.empty() ? 0 : std::prev(DFSStack.back().second);
14301431 }
14311432
14321433 const SUnit *getCurr() const { return DFSStack.back().first; }
343343
344344 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
345345 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
346 LastLocalValue = llvm::prior(FuncInfo.InsertPt);
346 LastLocalValue = std::prev(FuncInfo.InsertPt);
347347
348348 // Restore the previous insert position.
349349 FuncInfo.InsertPt = OldInsertPt.InsertPt;
8787 // Before we start legalizing vector nodes, check if there are any vectors.
8888 bool HasVectors = false;
8989 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
90 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) {
90 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
9191 // Check if the values of the nodes contain vectors. We don't need to check
9292 // the operands because we are going to check their values at some point.
9393 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
111111 // node is only legalized after all of its operands are legalized.
112112 DAG.AssignTopologicalOrder();
113113 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
114 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
114 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
115115 LegalizeOp(SDValue(I, 0));
116116
117117 // Finally, it's possible the root changed. Get the new root.
602602 std::vector::iterator Best = Queue.begin();
603603 if (!DisableDFASched) {
604604 signed BestCost = SUSchedulingCost(*Best);
605 for (std::vector::iterator I = llvm::next(Queue.begin()),
605 for (std::vector::iterator I = std::next(Queue.begin()),
606606 E = Queue.end(); I != E; ++I) {
607607
608608 if (SUSchedulingCost(*I) > BestCost) {
613613 }
614614 // Use default TD scheduling mechanism.
615615 else {
616 for (std::vector::iterator I = llvm::next(Queue.begin()),
616 for (std::vector::iterator I = std::next(Queue.begin()),
617617 E = Queue.end(); I != E; ++I)
618618 if (Picker(*Best, *I))
619619 Best = I;
620620 }
621621
622622 SUnit *V = *Best;
623 if (Best != prior(Queue.end()))
623 if (Best != std::prev(Queue.end()))
624624 std::swap(*Best, Queue.back());
625625
626626 Queue.pop_back();
632632 void ResourcePriorityQueue::remove(SUnit *SU) {
633633 assert(!Queue.empty() && "Queue is empty!");
634634 std::vector::iterator I = std::find(Queue.begin(), Queue.end(), SU);
635 if (I != prior(Queue.end()))
635 if (I != std::prev(Queue.end()))
636636 std::swap(*I, Queue.back());
637637
638638 Queue.pop_back();
17071707 assert(SU->NodeQueueId != 0 && "Not in queue!");
17081708 std::vector::iterator I = std::find(Queue.begin(), Queue.end(),
17091709 SU);
1710 if (I != prior(Queue.end()))
1710 if (I != std::prev(Queue.end()))
17111711 std::swap(*I, Queue.back());
17121712 Queue.pop_back();
17131713 SU->NodeQueueId = 0;
17371737 template
17381738 static SUnit *popFromQueueImpl(std::vector &Q, SF &Picker) {
17391739 std::vector::iterator Best = Q.begin();
1740 for (std::vector::iterator I = llvm::next(Q.begin()),
1740 for (std::vector::iterator I = std::next(Q.begin()),
17411741 E = Q.end(); I != E; ++I)
17421742 if (Picker(*Best, *I))
17431743 Best = I;
17441744 SUnit *V = *Best;
1745 if (Best != prior(Q.end()))
1745 if (Best != std::prev(Q.end()))
17461746 std::swap(*Best, Q.back());
17471747 Q.pop_back();
17481748 return V;
737737 if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI() ||
738738 // Fast-isel may have inserted some instructions, in which case the
739739 // BB->back().isPHI() test will not fire when we want it to.
740 prior(Emitter.getInsertPos())->isPHI()) {
740 std::prev(Emitter.getInsertPos())->isPHI()) {
741741 // Did not insert any instruction.
742742 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
743743 return;
744744 }
745745
746 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
746 Orders.push_back(std::make_pair(Order, std::prev(Emitter.getInsertPos())));
747747 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
748748 }
749749
26492649 if (Cases.size() >= 2)
26502650 // Must recompute end() each iteration because it may be
26512651 // invalidated by erase if we hold on to it
2652 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2652 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
26532653 J != Cases.end(); ) {
26542654 const APInt& nextValue = cast(J->Low)->getValue();
26552655 const APInt& currentValue = cast(I->High)->getValue();
356356 for (MachineSDNode::mmo_iterator i = MN->memoperands_begin(),
357357 e = MN->memoperands_end(); i != e; ++i) {
358358 OS << **i;
359 if (llvm::next(i) != e)
359 if (std::next(i) != e)
360360 OS << " ";
361361 }
362362 OS << ">";
456456 if (Def) {
457457 MachineBasicBlock::iterator InsertPos = Def;
458458 // FIXME: VR def may not be in entry block.
459 Def->getParent()->insert(llvm::next(InsertPos), MI);
459 Def->getParent()->insert(std::next(InsertPos), MI);
460460 } else
461461 DEBUG(dbgs() << "Dropping debug info for dead vreg"
462462 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
10661066 // where they are, so we can be sure to emit subsequent instructions
10671067 // after them.
10681068 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1069 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1069 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
10701070 else
10711071 FastIS->setLastLocalValue(0);
10721072 }
10741074 unsigned NumFastIselRemaining = std::distance(Begin, End);
10751075 // Do FastISel on as many instructions as possible.
10761076 for (; BI != Begin; --BI) {
1077 const Instruction *Inst = llvm::prior(BI);
1077 const Instruction *Inst = std::prev(BI);
10781078
10791079 // If we no longer require this instruction, skip it.
10801080 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
10951095 // Try to fold the load if so.
10961096 const Instruction *BeforeInst = Inst;
10971097 while (BeforeInst != Begin) {
1098 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1098 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
10991099 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
11001100 break;
11011101 }
11031103 BeforeInst->hasOneUse() &&
11041104 FastIS->tryToFoldLoad(cast(BeforeInst), Inst)) {
11051105 // If we succeeded, don't re-select the load.
1106 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1106 BI = std::next(BasicBlock::const_iterator(BeforeInst));
11071107 --NumFastIselRemaining;
11081108 ++NumFastIselSuccess;
11091109 }
172172 Type *LPadType = LPI->getType();
173173 Value *LPadVal = UndefValue::get(LPadType);
174174 IRBuilder<> Builder(
175 llvm::next(BasicBlock::iterator(cast(SelVal))));
175 std::next(BasicBlock::iterator(cast(SelVal))));
176176 LPadVal = Builder.CreateInsertValue(LPadVal, ExnVal, 0, "lpad.val");
177177 LPadVal = Builder.CreateInsertValue(LPadVal, SelVal, 1, "lpad.val");
178178
128128 const unsigned Space = SlotIndex::InstrDist/2;
129129 assert((Space & 3) == 0 && "InstrDist must be a multiple of 2*NUM");
130130
131 IndexList::iterator startItr = prior(curItr);
131 IndexList::iterator startItr = std::prev(curItr);
132132 unsigned index = startItr->getIndex();
133133 do {
134134 curItr->setIndex(index += Space);
326326 // iteration is not zero, the last node was just updated.
327327 bool Changed = false;
328328 for (SmallVectorImpl::const_reverse_iterator I =
329 iteration == 0 ? Linked.rbegin() : llvm::next(Linked.rbegin()),
329 iteration == 0 ? Linked.rbegin() : std::next(Linked.rbegin()),
330330 E = Linked.rend(); I != E; ++I) {
331331 unsigned n = *I;
332332 if (nodes[n].update(nodes)) {
341341 // Scan forwards, skipping the first node which was just updated.
342342 Changed = false;
343343 for (SmallVectorImpl::const_iterator I =
344 llvm::next(Linked.begin()), E = Linked.end(); I != E; ++I) {
344 std::next(Linked.begin()), E = Linked.end(); I != E; ++I) {
345345 unsigned n = *I;
346346 if (nodes[n].update(nodes)) {
347347 Changed = true;
142142 if (hasDef) {
143143 MachineInstrSpan MIS(miItr);
144144
145 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), NewVReg,
145 tii->storeRegToStackSlot(*mi->getParent(), std::next(miItr), NewVReg,
146146 true, ss, trc, tri);
147 lis->InsertMachineInstrRangeInMaps(llvm::next(miItr), MIS.end());
147 lis->InsertMachineInstrRangeInMaps(std::next(miItr), MIS.end());
148148 }
149149 }
150150 }
508508 assert(MI && "enterIntvAfter called with invalid index");
509509
510510 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
511 llvm::next(MachineBasicBlock::iterator(MI)));
511 std::next(MachineBasicBlock::iterator(MI)));
512512 return VNI->def;
513513 }
514514
569569 }
570570
571571 VNInfo *VNI = defFromParent(0, ParentVNI, Boundary, *MI->getParent(),
572 llvm::next(MachineBasicBlock::iterator(MI)));
572 std::next(MachineBasicBlock::iterator(MI)));
573573 return VNI->def;
574574 }
575575
160160 std::sort(LiveOuts.begin(), LiveOuts.end());
161161 for (LiveOutVec::iterator I = LiveOuts.begin(), E = LiveOuts.end();
162162 I != E; ++I) {
163 for (LiveOutVec::iterator II = next(I); II != E; ++II) {
163 for (LiveOutVec::iterator II = std::next(I); II != E; ++II) {
164164 if (I->RegNo != II->RegNo) {
165165 // Skip all the now invalid entries.
166166 I = --II;
191191
192192 if (recordResult) {
193193 assert(PatchPointOpers(&MI).hasDef() && "Stackmap has no return value.");
194 parseOperand(MI.operands_begin(), llvm::next(MI.operands_begin()),
194 parseOperand(MI.operands_begin(), std::next(MI.operands_begin()),
195195 Locations, LiveOuts);
196196 }
197197
231231 assert(MI.getOpcode() == TargetOpcode::STACKMAP && "expected stackmap");
232232
233233 int64_t ID = MI.getOperand(0).getImm();
234 recordStackMapOpers(MI, ID, llvm::next(MI.operands_begin(), 2),
234 recordStackMapOpers(MI, ID, std::next(MI.operands_begin(), 2),
235235 MI.operands_end());
236236 }
237237
242242 int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm();
243243
244244 MachineInstr::const_mop_iterator MOI =
245 llvm::next(MI.operands_begin(), opers.getStackMapStartIdx());
245 std::next(MI.operands_begin(), opers.getStackMapStartIdx());
246246 recordStackMapOpers(MI, ID, MOI, MI.operands_end(),
247247 opers.isAnyReg() && opers.hasDef());
248248
283283 const unsigned MaxSearch = 4;
284284 bool NoInterposingChain = true;
285285
286 for (BasicBlock::reverse_iterator I = llvm::next(BB->rbegin()),
287 E = BB->rend();
286 for (BasicBlock::reverse_iterator I = std::next(BB->rbegin()), E = BB->rend();
288287 I != E && SearchCounter < MaxSearch; ++I) {
289288 Instruction *Inst = &*I;
290289
384384 toErase.push_back(I);
385385 continue;
386386 }
387
388 MachineBasicBlock::iterator NextMI = llvm::next(I);
387
388 MachineBasicBlock::iterator NextMI = std::next(I);
389389 if (NextMI == MBB->end()) continue;
390390
391391 unsigned LoadReg = 0;
696696 << "From simple Succ: " << *TailBB);
697697
698698 MachineBasicBlock *NewTarget = *TailBB->succ_begin();
699 MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(PredBB));
699 MachineBasicBlock *NextBB = std::next(MachineFunction::iterator(PredBB));
700700
701701 // Make PredFBB explicit.
702702 if (PredCond.empty())
797797 // Update PredBB livein.
798798 RS->enterBasicBlock(PredBB);
799799 if (!PredBB->empty())
800 RS->forward(prior(PredBB->end()));
800 RS->forward(std::prev(PredBB->end()));
801801 BitVector RegsLiveAtExit(TRI->getNumRegs());
802802 RS->getRegsUsed(RegsLiveAtExit, false);
803803 for (MachineBasicBlock::livein_iterator I = TailBB->livein_begin(),
856856 // If TailBB was duplicated into all its predecessors except for the prior
857857 // block, which falls through unconditionally, move the contents of this
858858 // block into the prior block.
859 MachineBasicBlock *PrevBB = prior(MachineFunction::iterator(TailBB));
859 MachineBasicBlock *PrevBB = std::prev(MachineFunction::iterator(TailBB));
860860 MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0;
861861 SmallVector PriorCond;
862862 // This has to check PrevBB->succ_size() because EH edges are ignored by
254254 ++KillPos;
255255
256256 unsigned NumVisited = 0;
257 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
257 for (MachineBasicBlock::iterator I = std::next(OldPos); I != KillPos; ++I) {
258258 MachineInstr *OtherMI = I;
259259 // DBG_VALUE cannot be counted against the limit.
260260 if (OtherMI->isDebugValue())
416416 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
417417 // If there are multiple defs, we can't do a simple analysis, so just
418418 // go with what the kill flag says.
419 if (llvm::next(Begin) != MRI->def_end())
419 if (std::next(Begin) != MRI->def_end())
420420 return true;
421421 DefMI = &*Begin;
422422 bool IsSrcPhys, IsDstPhys;
646646 if (!Sunk) {
647647 DistanceMap.insert(std::make_pair(NewMI, Dist));
648648 mi = NewMI;
649 nmi = llvm::next(mi);
649 nmi = std::next(mi);
650650 }
651651
652652 // Update source and destination register maps.
815815
816816 // Move the copies connected to MI down as well.
817817 MachineBasicBlock::iterator Begin = MI;
818 MachineBasicBlock::iterator AfterMI = llvm::next(Begin);
818 MachineBasicBlock::iterator AfterMI = std::next(Begin);
819819
820820 MachineBasicBlock::iterator End = AfterMI;
821821 while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
875875 }
876876
877877 // Move debug info as well.
878 while (Begin != MBB->begin() && llvm::prior(Begin)->isDebugValue())
878 while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
879879 --Begin;
880880
881881 nmi = End;
890890 LIS->handleMove(CopyMI);
891891 InsertPos = CopyMI;
892892 }
893 End = llvm::next(MachineBasicBlock::iterator(MI));
893 End = std::next(MachineBasicBlock::iterator(MI));
894894 }
895895
896896 // Copies following MI may have been moved as well.
10591059
10601060 // Move the old kill above MI, don't forget to move debug info as well.
10611061 MachineBasicBlock::iterator InsertPos = mi;
1062 while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue())
1062 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
10631063 --InsertPos;
10641064 MachineBasicBlock::iterator From = KillMI;
1065 MachineBasicBlock::iterator To = llvm::next(From);
1066 while (llvm::prior(From)->isDebugValue())
1065 MachineBasicBlock::iterator To = std::next(From);
1066 while (std::prev(From)->isDebugValue())
10671067 --From;
10681068 MBB->splice(InsertPos, MBB, From, To);
10691069
1070 nmi = llvm::prior(InsertPos); // Backtrack so we process the moved instr.
1070 nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
10711071 DistanceMap.erase(DI);
10721072
10731073 // Update live variables
15331533 Processed.clear();
15341534 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
15351535 mi != me; ) {
1536 MachineBasicBlock::iterator nmi = llvm::next(mi);
1536 MachineBasicBlock::iterator nmi = std::next(mi);
15371537 if (mi->isDebugValue()) {
15381538 mi = nmi;
15391539 continue;
16881688 }
16891689
16901690 MachineBasicBlock::iterator EndMBBI =
1691 llvm::next(MachineBasicBlock::iterator(MI));
1691 std::next(MachineBasicBlock::iterator(MI));
16921692
16931693 if (!DefEmitted) {
16941694 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
303303 assert(I != InstList.end() &&
304304 "Trying to get me to create degenerate basic block!");
305305
306 BasicBlock *InsertBefore = llvm::next(Function::iterator(this))
306 BasicBlock *InsertBefore = std::next(Function::iterator(this))
307307 .getNodePtrUnchecked();
308308 BasicBlock *New = BasicBlock::Create(getContext(), BBName,
309309 getParent(), InsertBefore);
10461046 if (getOpcode() != Instruction::GetElementPtr) return false;
10471047
10481048 gep_type_iterator GEPI = gep_type_begin(this), E = gep_type_end(this);
1049 User::const_op_iterator OI = llvm::next(this->op_begin());
1049 User::const_op_iterator OI = std::next(this->op_begin());
10501050
10511051 // Skip the first index, as it has no static limit.
10521052 ++GEPI;
122122 if (Inserted) {
123123 FunctionAnalysisResultListT &ResultList = FunctionAnalysisResultLists[F];
124124 ResultList.push_back(std::make_pair(PassID, lookupPass(PassID).run(F, this)));
125 RI->second = llvm::prior(ResultList.end());
125 RI->second = std::prev(ResultList.end());
126126 }
127127
128128 return *RI->second->second;
5252 assert(getCurrentSectionData() && "No current section!");
5353
5454 if (CurInsertionPoint != getCurrentSectionData()->getFragmentList().begin())
55 return prior(CurInsertionPoint);
55 return std::prev(CurInsertionPoint);
5656
5757 return 0;
5858 }
237237 // Get the next machine basic block in the function.
238238 MachineFunction::iterator MBBI = MBB;
239239 // Can't fall off end of function.
240 if (llvm::next(MBBI) == MBB->getParent()->end())
240 if (std::next(MBBI) == MBB->getParent()->end())
241241 return false;
242242
243 MachineBasicBlock *NextBB = llvm::next(MBBI);
243 MachineBasicBlock *NextBB = std::next(MBBI);
244244 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
245245 E = MBB->succ_end(); I != E; ++I)
246246 if (*I == NextBB)
527527
528528 ++NumCBrFixed;
529529 if (BMI != MI) {
530 if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
530 if (std::next(MachineBasicBlock::iterator(MI)) == std::prev(MBB->end()) &&
531531 BMI->getOpcode() == AArch64::Bimm) {
532532 // Last MI in the BB is an unconditional branch. We can swap destinations:
533533 // b.eq L1 (temporarily b.ne L1 after first change)
574574 // b L1
575575 // splitbb/fallthroughbb:
576576 // [old b L2/real continuation]
577 MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
577 MachineBasicBlock *NextBB = std::next(MachineFunction::iterator(MBB));
578578
579579 DEBUG(dbgs() << " Insert B to BB#"
580580 << MI->getOperand(CondBrMBBOperand).getMBB()->getNumber()
236236
237237
238238 // Delete the pseudo instruction TC_RETURN.
239 MachineInstr *NewMI = prior(MBBI);
239 MachineInstr *NewMI = std::prev(MBBI);
240240 MBB.erase(MBBI);
241241 MBBI = NewMI;
242242
628628
629629 // Transfer the remainder of BB and its successor edges to exitMBB.
630630 exitMBB->splice(exitMBB->begin(), BB,
631 llvm::next(MachineBasicBlock::iterator(MI)),
632 BB->end());
631 std::next(MachineBasicBlock::iterator(MI)), BB->end());
633632 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
634633
635634 const TargetRegisterClass *TRC
723722
724723 // Transfer the remainder of BB and its successor edges to exitMBB.
725724 exitMBB->splice(exitMBB->begin(), BB,
726 llvm::next(MachineBasicBlock::iterator(MI)),
727 BB->end());
725 std::next(MachineBasicBlock::iterator(MI)), BB->end());
728726 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
729727
730728 unsigned scratch = MRI.createVirtualRegister(TRC);
807805
808806 // Transfer the remainder of BB and its successor edges to exitMBB.
809807 exitMBB->splice(exitMBB->begin(), BB,
810 llvm::next(MachineBasicBlock::iterator(MI)),
811 BB->end());
808 std::next(MachineBasicBlock::iterator(MI)), BB->end());
812809 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
813810
814811 // thisMBB:
899896 MF->insert(It, EndBB);
900897
901898 // Transfer rest of current basic-block to EndBB
902 EndBB->splice(EndBB->begin(), MBB,
903 llvm::next(MachineBasicBlock::iterator(MI)),
899 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
904900 MBB->end());
905901 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
906902
335335 // If we can modify the function, delete everything below this
336336 // unconditional branch.
337337 if (AllowModify) {
338 MachineBasicBlock::iterator DI = llvm::next(I);
338 MachineBasicBlock::iterator DI = std::next(I);
339339 while (DI != MBB.end()) {
340340 MachineInstr *InstToDelete = DI;
341341 ++DI;
21752175 // Walk down one instruction which is potentially an 'and'.
21762176 const MachineInstr &Copy = *MI;
21772177 MachineBasicBlock::iterator AND(
2178 llvm::next(MachineBasicBlock::iterator(MI)));
2178 std::next(MachineBasicBlock::iterator(MI)));
21792179 if (AND == MI->getParent()->end()) return false;
21802180 MI = AND;
21812181 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
32523252 Dist = 0;
32533253
32543254 MachineBasicBlock::const_iterator I = MI; ++I;
3255 MachineBasicBlock::const_instr_iterator II =
3256 llvm::prior(I.getInstrIterator());
3255 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
32573256 assert(II->isInsideBundle() && "Empty bundle?");
32583257
32593258 int Idx = -1;
568568 // Get the next machine basic block in the function.
569569 MachineFunction::iterator MBBI = MBB;
570570 // Can't fall off end of function.
571 if (llvm::next(MBBI) == MBB->getParent()->end())
571 if (std::next(MBBI) == MBB->getParent()->end())
572572 return false;
573573
574 MachineBasicBlock *NextBB = llvm::next(MBBI);
574 MachineBasicBlock *NextBB = std::next(MBBI);
575575 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
576576 E = MBB->succ_end(); I != E; ++I)
577577 if (*I == NextBB)
916916 CompareMBBNumbers);
917917 MachineBasicBlock* WaterBB = *IP;
918918 if (WaterBB == OrigBB)
919 WaterList.insert(llvm::next(IP), NewBB);
919 WaterList.insert(std::next(IP), NewBB);
920920 else
921921 WaterList.insert(IP, OrigBB);
922922 NewWaterList.insert(OrigBB);
11871187 return false;
11881188
11891189 unsigned BestGrowth = ~0u;
1190 for (water_iterator IP = prior(WaterList.end()), B = WaterList.begin();;
1190 for (water_iterator IP = std::prev(WaterList.end()), B = WaterList.begin();;
11911191 --IP) {
11921192 MachineBasicBlock* WaterBB = *IP;
11931193 // Check if water is in range and is either at a lower address than the
12481248 if (isOffsetInRange(UserOffset, CPEOffset, U)) {
12491249 DEBUG(dbgs() << "Split at end of BB#" << UserMBB->getNumber()
12501250 << format(", expected CPE offset %#x\n", CPEOffset));
1251 NewMBB = llvm::next(MachineFunction::iterator(UserMBB));
1251 NewMBB = std::next(MachineFunction::iterator(UserMBB));
12521252 // Add an unconditional branch from UserMBB to fallthrough block. Record
12531253 // it for branch lengthening; this new branch will not get out of range,
12541254 // but if the preceding conditional branch is out of range, the targets
13191319 MachineInstr *LastIT = 0;
13201320 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
13211321 Offset < BaseInsertOffset;
1322 Offset += TII->GetInstSizeInBytes(MI),
1323 MI = llvm::next(MI)) {
1322 Offset += TII->GetInstSizeInBytes(MI), MI = std::next(MI)) {
13241323 assert(MI != UserMBB->end() && "Fell off end of block");
13251324 if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) {
13261325 CPUser &U = CPUsers[CPUIndex];
13921391 NewWaterList.insert(NewIsland);
13931392
13941393 // The new CPE goes before the following block (NewMBB).
1395 NewMBB = llvm::next(MachineFunction::iterator(WaterBB));
1394 NewMBB = std::next(MachineFunction::iterator(WaterBB));
13961395
13971396 } else {
13981397 // No water found.
14041403 // next iteration for constant pools, but in this context, we don't want
14051404 // it. Check for this so it will be removed from the WaterList.
14061405 // Also remove any entry from NewWaterList.
1407 MachineBasicBlock *WaterBB = prior(MachineFunction::iterator(NewMBB));
1406 MachineBasicBlock *WaterBB = std::prev(MachineFunction::iterator(NewMBB));
14081407 IP = std::find(WaterList.begin(), WaterList.end(), WaterBB);
14091408 if (IP != WaterList.end())
14101409 NewWaterList.erase(WaterBB);
14421441
14431442 // Increase the size of the island block to account for the new entry.
14441443 BBInfo[NewIsland->getNumber()].Size += Size;
1445 adjustBBOffsetsAfter(llvm::prior(MachineFunction::iterator(NewIsland)));
1444 adjustBBOffsetsAfter(std::prev(MachineFunction::iterator(NewIsland)));
14461445
14471446 // Finally, change the CPI in the instruction operand to be ID.
14481447 for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
15911590
15921591 ++NumCBrFixed;
15931592 if (BMI != MI) {
1594 if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
1593 if (std::next(MachineBasicBlock::iterator(MI)) == std::prev(MBB->end()) &&
15951594 BMI->getOpcode() == Br.UncondBr) {
15961595 // Last MI in the BB is an unconditional branch. Can we simply invert the
15971596 // condition and swap destinations:
16211620 MBB->back().eraseFromParent();
16221621 // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
16231622 }
1624 MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
1623 MachineBasicBlock *NextBB = std::next(MachineFunction::iterator(MBB));
16251624
16261625 DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber()
16271626 << " also invert condition and change dest. to BB#"
20162015 SmallVector Cond;
20172016 SmallVector CondPrior;
20182017 MachineFunction::iterator BBi = BB;
2019 MachineFunction::iterator OldPrior = prior(BBi);
2018 MachineFunction::iterator OldPrior = std::prev(BBi);
20202019
20212020 // If the block terminator isn't analyzable, don't try to move the block
20222021 bool B = TII->AnalyzeBranch(*BB, TBB, FBB, Cond);
12721272
12731273 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
12741274 while (MBBI != E) {
1275 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
1275 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
12761276 Modified |= ExpandMI(MBB, MBBI);
12771277 MBBI = NMBBI;
12781278 }
631631 addReg(JumpTarget.getReg(), RegState::Kill);
632632 }
633633
634 MachineInstr *NewMI = prior(MBBI);
634 MachineInstr *NewMI = std::prev(MBBI);
635635 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
636636 NewMI->addOperand(MBBI->getOperand(i));
637637
10161016 }
10171017
10181018 // The last spill instruction inserted should kill the scratch register r4.
1019 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
1019 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
10201020 }
10211021
10221022 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
11261126 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
11271127
11281128 // Last store kills r4.
1129 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
1129 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
11301130 }
11311131
11321132 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
5656 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
5757 MachineBasicBlock::iterator I = LastMI;
5858 if (I != LastMI->getParent()->begin()) {
59 I = llvm::prior(I);
59 I = std::prev(I);
6060 DefMI = &*I;
6161 }
6262 }
61986198
61996199 // Transfer the remainder of BB and its successor edges to exitMBB.
62006200 exitMBB->splice(exitMBB->begin(), BB,
6201 llvm::next(MachineBasicBlock::iterator(MI)),
6202 BB->end());
6201 std::next(MachineBasicBlock::iterator(MI)), BB->end());
62036202 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
62046203
62056204 // thisMBB:
62836282
62846283 // Transfer the remainder of BB and its successor edges to exitMBB.
62856284 exitMBB->splice(exitMBB->begin(), BB,
6286 llvm::next(MachineBasicBlock::iterator(MI)),
6287 BB->end());
6285 std::next(MachineBasicBlock::iterator(MI)), BB->end());
62886286 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
62896287
62906288 const TargetRegisterClass *TRC = isThumb2 ?
63916389
63926390 // Transfer the remainder of BB and its successor edges to exitMBB.
63936391 exitMBB->splice(exitMBB->begin(), BB,
6394 llvm::next(MachineBasicBlock::iterator(MI)),
6395 BB->end());
6392 std::next(MachineBasicBlock::iterator(MI)), BB->end());
63966393 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
63976394
63986395 const TargetRegisterClass *TRC = isThumb2 ?
65116508
65126509 // Transfer the remainder of BB and its successor edges to exitMBB.
65136510 exitMBB->splice(exitMBB->begin(), BB,
6514 llvm::next(MachineBasicBlock::iterator(MI)),
6515 BB->end());
6511 std::next(MachineBasicBlock::iterator(MI)), BB->end());
65166512 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
65176513
65186514 const TargetRegisterClass *TRC = isThumb2 ?
74437439
74447440 // Transfer the remainder of BB and its successor edges to exitMBB.
74457441 exitMBB->splice(exitMBB->begin(), BB,
7446 llvm::next(MachineBasicBlock::iterator(MI)),
7447 BB->end());
7442 std::next(MachineBasicBlock::iterator(MI)), BB->end());
74487443 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
74497444
74507445 // Load an immediate to varEnd.
77707765
77717766 // Transfer the remainder of BB and its successor edges to sinkMBB.
77727767 sinkMBB->splice(sinkMBB->begin(), BB,
7773 llvm::next(MachineBasicBlock::iterator(MI)),
7774 BB->end());
7768 std::next(MachineBasicBlock::iterator(MI)), BB->end());
77757769 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
77767770
77777771 BB->addSuccessor(copy0MBB);
78047798 case ARM::BCCi64:
78057799 case ARM::BCCZi64: {
78067800 // If there is an unconditional branch to the other successor, remove it.
7807 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
7801 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
78087802
78097803 // Compare both parts that make up the double comparison separately for
78107804 // equality.
78897883
78907884 // Transfer the remainder of BB and its successor edges to sinkMBB.
78917885 SinkBB->splice(SinkBB->begin(), BB,
7892 llvm::next(MachineBasicBlock::iterator(MI)),
7893 BB->end());
7886 std::next(MachineBasicBlock::iterator(MI)), BB->end());
78947887 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
78957888
78967889 BB->addSuccessor(RSBBB);
483483 return;
484484
485485 // Merge succeeded, update records.
486 Merges.push_back(prior(Loc));
486 Merges.push_back(std::prev(Loc));
487487
488488 // In gathering loads together, we may have moved the imp-def of a register
489489 // past one of its uses. This is OK, since we know better than the rest of
811811 // Try merging with the previous instruction.
812812 MachineBasicBlock::iterator BeginMBBI = MBB.begin();
813813 if (MBBI != BeginMBBI) {
814 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
814 MachineBasicBlock::iterator PrevMBBI = std::prev(MBBI);
815815 while (PrevMBBI != BeginMBBI && PrevMBBI->isDebugValue())
816816 --PrevMBBI;
817817 if (Mode == ARM_AM::ia &&
830830 // Try merging with the next instruction.
831831 MachineBasicBlock::iterator EndMBBI = MBB.end();
832832 if (!DoMerge && MBBI != EndMBBI) {
833 MachineBasicBlock::iterator NextMBBI = llvm::next(MBBI);
833 MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
834834 while (NextMBBI != EndMBBI && NextMBBI->isDebugValue())
835835 ++NextMBBI;
836836 if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
958958 // Try merging with the previous instruction.
959959 MachineBasicBlock::iterator BeginMBBI = MBB.begin();
960960 if (MBBI != BeginMBBI) {
961 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
961 MachineBasicBlock::iterator PrevMBBI = std::prev(MBBI);
962962 while (PrevMBBI != BeginMBBI && PrevMBBI->isDebugValue())
963963 --PrevMBBI;
964964 if (isMatchingDecrement(PrevMBBI, Base, Bytes, Limit, Pred, PredReg)) {
977977 // Try merging with the next instruction.
978978 MachineBasicBlock::iterator EndMBBI = MBB.end();
979979 if (!DoMerge && MBBI != EndMBBI) {
980 MachineBasicBlock::iterator NextMBBI = llvm::next(MBBI);
980 MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
981981 while (NextMBBI != EndMBBI && NextMBBI->isDebugValue())
982982 ++NextMBBI;
983983 if (!isAM5 &&
11211121 }
11221122
11231123 if (Loc != MBB.begin())
1124 RS->forward(prior(Loc));
1124 RS->forward(std::prev(Loc));
11251125 }
11261126
11271127 static int getMemoryOpOffset(const MachineInstr *MI) {
12311231 getKillRegState(OddDeadKill) | getUndefRegState(OddUndef));
12321232 ++NumSTRD2STM;
12331233 }
1234 NewBBI = llvm::prior(MBBI);
1234 NewBBI = std::prev(MBBI);
12351235 } else {
12361236 // Split into two instructions.
12371237 unsigned NewOpc = (isLd)
12531253 OddReg, OddDeadKill, false,
12541254 BaseReg, false, BaseUndef, false, OffUndef,
12551255 Pred, PredReg, TII, isT2);
1256 NewBBI = llvm::prior(MBBI);
1256 NewBBI = std::prev(MBBI);
12571257 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
12581258 EvenReg, EvenDeadKill, false,
12591259 BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
12731273 EvenReg, EvenDeadKill, EvenUndef,
12741274 BaseReg, false, BaseUndef, false, OffUndef,
12751275 Pred, PredReg, TII, isT2);
1276 NewBBI = llvm::prior(MBBI);
1276 NewBBI = std::prev(MBBI);
12771277 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2,
12781278 OddReg, OddDeadKill, OddUndef,
12791279 BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
14181418 // Find a scratch register.
14191419 unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass);
14201420 // Process the load / store instructions.
1421 RS->forward(prior(MBBI));
1421 RS->forward(std::prev(MBBI));
14221422
14231423 // Merge ops.
14241424 Merges.clear();
14401440 ++NumMerges;
14411441
14421442 // RS may be pointing to an instruction that's deleted.
1443 RS->skipTo(prior(MBBI));
1443 RS->skipTo(std::prev(MBBI));
14441444 } else if (NumMemOps == 1) {
14451445 // Try folding preceding/trailing base inc/dec into the single
14461446 // load/store.
14471447 if (MergeBaseUpdateLoadStore(MBB, MemOps[0].MBBI, TII, Advance, MBBI)) {
14481448 ++NumMerges;
1449 RS->forward(prior(MBBI));
1449 RS->forward(std::prev(MBBI));
14501450 }
14511451 }
14521452
14891489 (MBBI->getOpcode() == ARM::BX_RET ||
14901490 MBBI->getOpcode() == ARM::tBX_RET ||
14911491 MBBI->getOpcode() == ARM::MOVPCLR)) {
1492 MachineInstr *PrevMI = prior(MBBI);
1492 MachineInstr *PrevMI = std::prev(MBBI);
14931493 unsigned Opcode = PrevMI->getOpcode();
14941494 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||
14951495 Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||
311311 dbgs() << "Expanding: " << *MI;
312312 dbgs() << " to:\n";
313313 MachineBasicBlock::iterator MII = MI;
314 MII = llvm::prior(MII);
314 MII = std::prev(MII);
315315 MachineInstr &MI2 = *MII;
316 MII = llvm::prior(MII);
316 MII = std::prev(MII);
317317 MachineInstr &MI1 = *MII;
318318 dbgs() << " " << MI1;
319319 dbgs() << " " << MI2;
181181
182182 int FramePtrOffsetInBlock = 0;
183183 unsigned adjustedGPRCS1Size = GPRCS1Size;
184 if (tryFoldSPUpdateIntoPushPop(STI, MF, prior(MBBI), NumBytes)) {
184 if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) {
185185 FramePtrOffsetInBlock = NumBytes;
186186 adjustedGPRCS1Size += NumBytes;
187187 NumBytes = 0;
364364 } else {
365365 if (MBBI->getOpcode() == ARM::tBX_RET &&
366366 &MBB.front() != MBBI &&
367 prior(MBBI)->getOpcode() == ARM::tPOP) {
368 MachineBasicBlock::iterator PMBBI = prior(MBBI);
367 std::prev(MBBI)->getOpcode() == ARM::tPOP) {
368 MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
369369 if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
370370 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
371371 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
420420 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
421421 }
422422 Offset = (Offset - Mask * Scale);
423 MachineBasicBlock::iterator NII = llvm::next(II);
423 MachineBasicBlock::iterator NII = std::next(II);
424424 emitThumbRegPlusImmediate(MBB, NII, dl, DestReg, DestReg, Offset, TII,
425425 *this);
426426 } else {
241241
242242 // Finalize the bundle.
243243 MachineBasicBlock::instr_iterator LI = LastITMI;
244 finalizeBundle(MBB, InsertPos.getInstrIterator(), llvm::next(LI));
244 finalizeBundle(MBB, InsertPos.getInstrIterator(), std::next(LI));
245245
246246 Modified = true;
247247 ++NumITs;
944944 MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),E = MBB.instr_end();
945945 MachineBasicBlock::instr_iterator NextMII;
946946 for (; MII != E; MII = NextMII) {
947 NextMII = llvm::next(MII);
947 NextMII = std::next(MII);
948948
949949 MachineInstr *MI = &*MII;
950950 if (MI->isBundle()) {
961961
962962 if (ReduceMI(MBB, MI, LiveCPSR, IsSelfLoop)) {
963963 Modified = true;
964 MachineBasicBlock::instr_iterator I = prior(NextMII);
964 MachineBasicBlock::instr_iterator I = std::prev(NextMII);
965965 MI = &*I;
966966 // Removing and reinserting the first instruction in a bundle will break
967967 // up the bundle. Fix the bundling if it was broken.
299299 MachineBasicBlock::iterator I(I1), End(I2);
300300 // At O3 we got better results (dhrystone) by being more conservative here.
301301 if (!ShouldCombineAggressively)
302 End = llvm::next(MachineBasicBlock::iterator(I2));
302 End = std::next(MachineBasicBlock::iterator(I2));
303303 IsImmUseReg = I1->getOperand(1).isImm() || I1->getOperand(1).isGlobal();
304304 unsigned I1UseReg = IsImmUseReg ? 0 : I1->getOperand(1).getReg();
305305 // Track killed operands. If we move across an instruction that kills our
463463 /// false if the combine must be inserted at the returned instruction.
464464 MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
465465 bool &DoInsertAtI1) {
466 MachineBasicBlock::iterator I2 = llvm::next(MachineBasicBlock::iterator(I1));
466 MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
467467 unsigned I1DestReg = I1->getOperand(0).getReg();
468468
469469 for (MachineBasicBlock::iterator End = I1->getParent()->end(); I2 != End;
143143
144144 void HexagonFrameLowering::emitEpilogue(MachineFunction &MF,
145145 MachineBasicBlock &MBB) const {
146 MachineBasicBlock::iterator MBBI = prior(MBB.end());
146 MachineBasicBlock::iterator MBBI = std::prev(MBB.end());
147147 DebugLoc dl = MBBI->getDebugLoc();
148148 //
149149 // Only insert deallocframe if we need to. Also at -O0. See comment
150150 // in emitPrologue above.
151151 //
152152 if (hasFP(MF) || MF.getTarget().getOptLevel() == CodeGenOpt::None) {
153 MachineBasicBlock::iterator MBBI = prior(MBB.end());
153 MachineBasicBlock::iterator MBBI = std::prev(MBB.end());
154154 MachineBasicBlock::iterator MBBI_end = MBB.end();
155155
156156 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
169169 // Check for RESTORE_DEALLOC_RET_JMP_V4 call. Don't emit an extra DEALLOC
170170 // instruction if we encounter it.
171171 MachineBasicBlock::iterator BeforeJMPR =
172 MBB.begin() == MBBI ? MBBI : prior(MBBI);
172 MBB.begin() == MBBI ? MBBI : std::prev(MBBI);
173173 if (BeforeJMPR != MBBI &&
174174 BeforeJMPR->getOpcode() == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) {
175175 // Remove the JMPR node.
189189 // DEALLOCFRAME instruction after it.
190190 MachineBasicBlock::iterator Term = MBB.getFirstTerminator();
191191 MachineBasicBlock::iterator I =
192 Term == MBB.begin() ? MBB.end() : prior(Term);
192 Term == MBB.begin() ? MBB.end() : std::prev(Term);
193193 if (I != MBB.end() &&
194194 I->getOpcode() == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4)
195195 return;
906906 // this instruction is dead: both it (and the phi node) can be removed.
907907 use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);
908908 use_nodbg_iterator End = MRI->use_nodbg_end();
909 if (llvm::next(I) != End || !I.getOperand().getParent()->isPHI())
909 if (std::next(I) != End || !I.getOperand().getParent()->isPHI())
910910 return false;
911911
912912 MachineInstr *OnePhi = I.getOperand().getParent();
919919 use_nodbg_iterator nextJ;
920920 for (use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg);
921921 J != End; J = nextJ) {
922 nextJ = llvm::next(J);
922 nextJ = std::next(J);
923923 MachineOperand &Use = J.getOperand();
924924 MachineInstr *UseMI = Use.getParent();
925925
953953 MachineRegisterInfo::use_iterator nextI;
954954 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
955955 E = MRI->use_end(); I != E; I = nextI) {
956 nextI = llvm::next(I); // I is invalidated by the setReg
956 nextI = std::next(I); // I is invalidated by the setReg
957957 MachineOperand &Use = I.getOperand();
958958 MachineInstr *UseMI = Use.getParent();
959959 if (UseMI == MI)
11611161 // Out of order.
11621162 unsigned PredR = CmpI->getOperand(0).getReg();
11631163 bool FoundBump = false;
1164 instr_iterator CmpIt = CmpI, NextIt = llvm::next(CmpIt);
1164 instr_iterator CmpIt = CmpI, NextIt = std::next(CmpIt);
11651165 for (instr_iterator I = NextIt, E = BB->instr_end(); I != E; ++I) {
11661166 MachineInstr *In = &*I;
11671167 for (unsigned i = 0, n = In->getNumOperands(); i < n; ++i) {
11751175 if (In == BumpI) {
11761176 instr_iterator After = BumpI;
11771177 instr_iterator From = CmpI;
1178 BB->splice(llvm::next(After), BB, From);
1178 BB->splice(std::next(After), BB, From);
11791179 FoundBump = true;
11801180 break;
11811181 }
146146 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
147147 false)) {
148148 MachineBasicBlock *NextBB =
149 llvm::next(MachineFunction::iterator(&MBB));
149 std::next(MachineFunction::iterator(&MBB));
150150 if (NewTBB == NextBB) {
151151 ReverseBranchCondition(Cond);
152152 RemoveBranch(MBB);
236236 // instruction stream until we find the nearest boundary.
237237 MachineBasicBlock::iterator I = RegionEnd;
238238 for(;I != MBB->begin(); --I, --RemainingCount) {
239 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
239 if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
240240 break;
241241 }
242242 I = MBB->begin();
243243
244244 // Skip empty scheduling regions.
245245 if (I == RegionEnd) {
246 RegionEnd = llvm::prior(RegionEnd);
246 RegionEnd = std::prev(RegionEnd);
247247 --RemainingCount;
248248 continue;
249249 }
250250 // Skip regions with one instruction.
251 if (I == llvm::prior(RegionEnd)) {
252 RegionEnd = llvm::prior(RegionEnd);
251 if (I == std::prev(RegionEnd)) {
252 RegionEnd = std::prev(RegionEnd);
253253 continue;
254254 }
255255
7070 .addReg(MSP430::SPW);
7171
7272 // Mark the FramePtr as live-in in every block except the entry.
73 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
73 for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
7474 I != E; ++I)
7575 I->addLiveIn(MSP430::FPW);
7676
137137
138138 // Skip the callee-saved pop instructions.
139139 while (MBBI != MBB.begin()) {
140 MachineBasicBlock::iterator PI = prior(MBBI);
140 MachineBasicBlock::iterator PI = std::prev(MBBI);
141141 unsigned Opc = PI->getOpcode();
142142 if (Opc != MSP430::POP16r && !PI->isTerminator())
143143 break;
12471247
12481248 // Update machine-CFG edges by transferring all successors of the current
12491249 // block to the block containing instructions after shift.
1250 RemBB->splice(RemBB->begin(), BB,
1251 llvm::next(MachineBasicBlock::iterator(MI)),
1250 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
12521251 BB->end());
12531252 RemBB->transferSuccessorsAndUpdatePHIs(BB);
12541253
13431342 // Update machine-CFG edges by transferring all successors of the current
13441343 // block to the new block which will contain the Phi node for the select.
13451344 copy1MBB->splice(copy1MBB->begin(), BB,
1346 llvm::next(MachineBasicBlock::iterator(MI)),
1347 BB->end());
1345 std::next(MachineBasicBlock::iterator(MI)), BB->end());
13481346 copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
13491347 // Next, add the true and fallthrough blocks as its successors.
13501348 BB->addSuccessor(copy0MBB);
204204 }
205205
206206 // If the block has any instructions after a JMP, delete them.
207 while (llvm::next(I) != MBB.end())
208 llvm::next(I)->eraseFromParent();
207 while (std::next(I) != MBB.end())
208 std::next(I)->eraseFromParent();
209209 Cond.clear();
210210 FBB = 0;
211211
141141 // We need to materialize the offset via add instruction.
142142 unsigned DstReg = MI.getOperand(0).getReg();
143143 if (Offset < 0)
144 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
144 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
145145 .addReg(DstReg).addImm(-Offset);
146146 else
147 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
147 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
148148 .addReg(DstReg).addImm(Offset);
149149
150150 return;
548548
549549 // Transfer the remainder of BB and its successor edges to sinkMBB.
550550 sinkMBB->splice(sinkMBB->begin(), BB,
551 llvm::next(MachineBasicBlock::iterator(MI)),
552 BB->end());
551 std::next(MachineBasicBlock::iterator(MI)), BB->end());
553552 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
554553
555554 // Next, add the true and fallthrough blocks as its successors.
611610
612611 // Transfer the remainder of BB and its successor edges to sinkMBB.
613612 sinkMBB->splice(sinkMBB->begin(), BB,
614 llvm::next(MachineBasicBlock::iterator(MI)),
615 BB->end());
613 std::next(MachineBasicBlock::iterator(MI)), BB->end());
616614 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
617615
618616 // Next, add the true and fallthrough blocks as its successors.
676674
677675 // Transfer the remainder of BB and its successor edges to sinkMBB.
678676 sinkMBB->splice(sinkMBB->begin(), BB,
679 llvm::next(MachineBasicBlock::iterator(MI)),
680 BB->end());
677 std::next(MachineBasicBlock::iterator(MI)), BB->end());
681678 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
682679
683680 // Next, add the true and fallthrough blocks as its successors.
410410 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
411411 .addReg(Reg, RegState::Kill);
412412 if (FirstRegSaved || SecondRegSaved) {
413 II = llvm::next(II);
413 II = std::next(II);
414414 if (FirstRegSaved)
415415 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
416416 if (SecondRegSaved)
615615 // Get the next machine basic block in the function.
616616 MachineFunction::iterator MBBI = MBB;
617617 // Can't fall off end of function.
618 if (llvm::next(MBBI) == MBB->getParent()->end())
618 if (std::next(MBBI) == MBB->getParent()->end())
619619 return false;
620620
621 MachineBasicBlock *NextBB = llvm::next(MBBI);
621 MachineBasicBlock *NextBB = std::next(MBBI);
622622 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
623623 E = MBB->succ_end(); I != E; ++I)
624624 if (*I == NextBB)
931931 CompareMBBNumbers);
932932 MachineBasicBlock* WaterBB = *IP;
933933 if (WaterBB == OrigBB)
934 WaterList.insert(llvm::next(IP), NewBB);
934 WaterList.insert(std::next(IP), NewBB);
935935 else
936936 WaterList.insert(IP, OrigBB);
937937 NewWaterList.insert(OrigBB);
12171217 return false;
12181218
12191219 unsigned BestGrowth = ~0u;
1220 for (water_iterator IP = prior(WaterList.end()), B = WaterList.begin();;
1220 for (water_iterator IP = std::prev(WaterList.end()), B = WaterList.begin();;
12211221 --IP) {
12221222 MachineBasicBlock* WaterBB = *IP;
12231223 // Check if water is in range and is either at a lower address than the
12761276 if (isOffsetInRange(UserOffset, CPEOffset, U)) {
12771277 DEBUG(dbgs() << "Split at end of BB#" << UserMBB->getNumber()
12781278 << format(", expected CPE offset %#x\n", CPEOffset));
1279 NewMBB = llvm::next(MachineFunction::iterator(UserMBB));
1279 NewMBB = std::next(MachineFunction::iterator(UserMBB));
12801280 // Add an unconditional branch from UserMBB to fallthrough block. Record
12811281 // it for branch lengthening; this new branch will not get out of range,
12821282 // but if the preceding conditional branch is out of range, the targets
13291329 //MachineInstr *LastIT = 0;
13301330 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
13311331 Offset < BaseInsertOffset;
1332 Offset += TII->GetInstSizeInBytes(MI),
1333 MI = llvm::next(MI)) {
1332 Offset += TII->GetInstSizeInBytes(MI), MI = std::next(MI)) {
13341333 assert(MI != UserMBB->end() && "Fell off end of block");
13351334 if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) {
13361335 CPUser &U = CPUsers[CPUIndex];
13871386 NewWaterList.insert(NewIsland);
13881387
13891388 // The new CPE goes before the following block (NewMBB).
1390 NewMBB = llvm::next(MachineFunction::iterator(WaterBB));
1389 NewMBB = std::next(MachineFunction::iterator(WaterBB));
13911390
13921391 } else {
13931392 // No water found.
14051404 // next iteration for constant pools, but in this context, we don't want
14061405 // it. Check for this so it will be removed from the WaterList.
14071406 // Also remove any entry from NewWaterList.
1408 MachineBasicBlock *WaterBB = prior(MachineFunction::iterator(NewMBB));
1407 MachineBasicBlock *WaterBB = std::prev(MachineFunction::iterator(NewMBB));
14091408 IP = std::find(WaterList.begin(), WaterList.end(), WaterBB);
14101409 if (IP != WaterList.end())
14111410 NewWaterList.erase(WaterBB);
14471446
14481447 // Increase the size of the island block to account for the new entry.
14491448 BBInfo[NewIsland->getNumber()].Size += Size;
1450 adjustBBOffsetsAfter(llvm::prior(MachineFunction::iterator(NewIsland)));
1449 adjustBBOffsetsAfter(std::prev(MachineFunction::iterator(NewIsland)));
14511450
14521451
14531452
16281627
16291628 ++NumCBrFixed;
16301629 if (BMI != MI) {
1631 if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
1630 if (std::next(MachineBasicBlock::iterator(MI)) == std::prev(MBB->end()) &&
16321631 isUnconditionalBranch(BMI->getOpcode())) {
16331632 // Last MI in the BB is an unconditional branch. Can we simply invert the
16341633 // condition and swap destinations:
16611660 MBB->back().eraseFromParent();
16621661 // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
16631662 }
1664 MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
1663 MachineBasicBlock *NextBB = std::next(MachineFunction::iterator(MBB));
16651664
16661665 DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber()
16671666 << " also invert condition and change dest. to BB#"
499499 // Bundle the NOP to the instruction with the delay slot.
500500 const MipsInstrInfo *TII =
501501 static_cast(TM.getInstrInfo());
502 BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
503 MIBundleBuilder(MBB, I, llvm::next(llvm::next(I)));
502 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
503 MIBundleBuilder(MBB, I, std::next(I, 2));
504504 }
505505
506506 return Changed;
550550 if (!searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Filler))
551551 return false;
552552
553 MBB.splice(llvm::next(Slot), &MBB, llvm::next(Filler).base());
554 MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
553 MBB.splice(std::next(Slot), &MBB, std::next(Filler).base());
554 MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
555555 ++UsefulSlots;
556556 return true;
557557 }
567567
568568 RegDU.setCallerSaved(*Slot);
569569
570 if (!searchRange(MBB, llvm::next(Slot), MBB.end(), RegDU, NM, Filler))
571 return false;
572
573 MBB.splice(llvm::next(Slot), &MBB, Filler);
574 MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
570 if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Filler))
571 return false;
572
573 MBB.splice(std::next(Slot), &MBB, Filler);
574 MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
575575 ++UsefulSlots;
576576 return true;
577577 }
817817 MachineBasicBlock::iterator I(MI);
818818 MachineInstrBuilder MIB;
819819 MachineOperand &Divisor = MI->getOperand(2);
820 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
820 MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
821821 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
822822 .addReg(Mips::ZERO).addImm(7);
823823
967967
968968 // Transfer the remainder of BB and its successor edges to exitMBB.
969969 exitMBB->splice(exitMBB->begin(), BB,
970 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
970 std::next(MachineBasicBlock::iterator(MI)), BB->end());
971971 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
972972
973973 // thisMBB:
10531053
10541054 // Transfer the remainder of BB and its successor edges to exitMBB.
10551055 exitMBB->splice(exitMBB->begin(), BB,
1056 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1056 std::next(MachineBasicBlock::iterator(MI)), BB->end());
10571057 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
10581058
10591059 BB->addSuccessor(loopMBB);
12081208
12091209 // Transfer the remainder of BB and its successor edges to exitMBB.
12101210 exitMBB->splice(exitMBB->begin(), BB,
1211 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1211 std::next(MachineBasicBlock::iterator(MI)), BB->end());
12121212 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
12131213
12141214 // thisMBB:
12941294
12951295 // Transfer the remainder of BB and its successor edges to exitMBB.
12961296 exitMBB->splice(exitMBB->begin(), BB,
1297 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1297 std::next(MachineBasicBlock::iterator(MI)), BB->end());
12981298 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
12991299
13001300 BB->addSuccessor(loop1MBB);
133133 (!LastBr->isConditionalBranch() && !LastBr->isUnconditionalBranch()))
134134 return;
135135
136 ReverseIter FirstBr = getNonDebugInstr(llvm::next(LastBr), End);
136 ReverseIter FirstBr = getNonDebugInstr(std::next(LastBr), End);
137137
138138 // MBB has only one branch instruction if FirstBr is not a branch
139139 // instruction.
153153 NewMBB->removeSuccessor(Tgt);
154154 MBB->addSuccessor(NewMBB);
155155 MBB->addSuccessor(Tgt);
156 MF->insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
156 MF->insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
157157
158158 NewMBB->splice(NewMBB->end(), MBB, (++LastBr).base(), MBB->end());
159159 }
26202620 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
26212621 DebugLoc DL = MI->getDebugLoc();
26222622 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2623 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2623 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
26242624 MachineFunction *F = BB->getParent();
26252625 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
26262626 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
26302630 F->insert(It, Sink);
26312631
26322632 // Transfer the remainder of BB and its successor edges to Sink.
2633 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2633 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
26342634 BB->end());
26352635 Sink->transferSuccessorsAndUpdatePHIs(BB);
26362636
26852685 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
26862686 DebugLoc DL = MI->getDebugLoc();
26872687 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2688 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2688 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
26892689 MachineFunction *F = BB->getParent();
26902690 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
26912691 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
26952695 F->insert(It, Sink);
26962696
26972697 // Transfer the remainder of BB and its successor edges to Sink.
2698 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2698 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
26992699 BB->end());
27002700 Sink->transferSuccessorsAndUpdatePHIs(BB);
27012701
60306030 F->insert(It, loopMBB);
60316031 F->insert(It, exitMBB);
60326032 exitMBB->splice(exitMBB->begin(), BB,
6033 llvm::next(MachineBasicBlock::iterator(MI)),
6034 BB->end());
6033 std::next(MachineBasicBlock::iterator(MI)), BB->end());
60356034 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
60366035
60376036 MachineRegisterInfo &RegInfo = F->getRegInfo();
60996098 F->insert(It, loopMBB);
61006099 F->insert(It, exitMBB);
61016100 exitMBB->splice(exitMBB->begin(), BB,
6102 llvm::next(MachineBasicBlock::iterator(MI)),
6103 BB->end());
6101 std::next(MachineBasicBlock::iterator(MI)), BB->end());
61046102 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
61056103
61066104 MachineRegisterInfo &RegInfo = F->getRegInfo();
62526250
62536251 // Transfer the remainder of BB and its successor edges to sinkMBB.
62546252 sinkMBB->splice(sinkMBB->begin(), MBB,
6255 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6253 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
62566254 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
62576255
62586256 // Note that the structure of the jmp_buf used here is not compatible
65176515
65186516 // Transfer the remainder of BB and its successor edges to sinkMBB.
65196517 sinkMBB->splice(sinkMBB->begin(), BB,
6520 llvm::next(MachineBasicBlock::iterator(MI)),
6521 BB->end());
6518 std::next(MachineBasicBlock::iterator(MI)), BB->end());
65226519 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
65236520
65246521 // Next, add the true and fallthrough blocks as its successors.
66386635 F->insert(It, midMBB);
66396636 F->insert(It, exitMBB);
66406637 exitMBB->splice(exitMBB->begin(), BB,
6641 llvm::next(MachineBasicBlock::iterator(MI)),
6642 BB->end());
6638 std::next(MachineBasicBlock::iterator(MI)), BB->end());
66436639 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
66446640
66456641 // thisMBB:
67096705 F->insert(It, midMBB);
67106706 F->insert(It, exitMBB);
67116707 exitMBB->splice(exitMBB->begin(), BB,
6712 llvm::next(MachineBasicBlock::iterator(MI)),
6713 BB->end());
6708 std::next(MachineBasicBlock::iterator(MI)), BB->end());
67146709 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
67156710
67166711 MachineRegisterInfo &RegInfo = F->getRegInfo();
14271427 CmpInstr->eraseFromParent();
14281428
14291429 MachineBasicBlock::iterator MII = MI;
1430 BuildMI(*MI->getParent(), llvm::next(MII), MI->getDebugLoc(),
1430 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
14311431 get(TargetOpcode::COPY), CRReg)
14321432 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
14331433
12371237
12381238 numClonedBlock += Num;
12391239 Num += serialPatternMatch(*HeadMBB->succ_begin());
1240 Num += serialPatternMatch(*llvm::next(HeadMBB->succ_begin()));
1240 Num += serialPatternMatch(*std::next(HeadMBB->succ_begin()));
12411241 Num += ifPatternMatch(HeadMBB);
12421242 assert(Num > 0);
12431243
17661766 if (MBB->succ_size() != 2)
17671767 return;
17681768 MachineBasicBlock *MBB1 = *MBB->succ_begin();
1769 MachineBasicBlock *MBB2 = *llvm::next(MBB->succ_begin());
1769 MachineBasicBlock *MBB2 = *std::next(MBB->succ_begin());
17701770 if (MBB1 != MBB2)
17711771 return;
17721772
7474 MachineBasicBlock::iterator I = MBB.begin();
7575 while (I != MBB.end()) {
7676 MachineInstr &MI = *I;
77 I = llvm::next(I);
77 I = std::next(I);
7878
7979 // Expand LDS_*_RET instructions
8080 if (TII->isLDSRetInstr(MI.getOpcode())) {
206206 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
207207 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
208208 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
209 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
209 unsigned EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
210210
211211 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
212212 .addOperand(MI->getOperand(0))
456456 // Instruction is left unmodified if its not the last one of its type
457457 bool isLastInstructionOfItsType = true;
458458 unsigned InstExportType = MI->getOperand(1).getImm();
459 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
459 for (MachineBasicBlock::iterator NextExportInst = std::next(I),
460460 EndBlock = BB->end(); NextExportInst != EndBlock;
461 NextExportInst = llvm::next(NextExportInst)) {
461 NextExportInst = std::next(NextExportInst)) {
462462 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
463463 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
464464 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
469469 }
470470 }
471471 }
472 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
472 bool EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
473473 if (!EOP && !isLastInstructionOfItsType)
474474 return BB;
475475 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
716716 }
717717
718718 // Remove successive JUMP
719 while (I != MBB.begin() && llvm::prior(I)->getOpcode() == AMDGPU::JUMP) {
720 MachineBasicBlock::iterator PriorI = llvm::prior(I);
719 while (I != MBB.begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
720 MachineBasicBlock::iterator PriorI = std::prev(I);
721721 if (AllowModify)
722722 I->removeFromParent();
723723 I = PriorI;
783783 It != E; ++It) {
784784 if (It->getOpcode() == AMDGPU::CF_ALU ||
785785 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
786 return llvm::prior(It.base());
786 return std::prev(It.base());
787787 }
788788 return MBB.end();
789789 }
310310 substitutePV(MI, PV);
311311 MachineBasicBlock::iterator It = VLIWPacketizerList::addToPacket(MI);
312312 if (isTransSlot) {
313 endPacket(llvm::next(It)->getParent(), llvm::next(It));
313 endPacket(std::next(It)->getParent(), std::next(It));
314314 }
315315 return It;
316316 }
370370 // instruction stream until we find the nearest boundary.
371371 MachineBasicBlock::iterator I = RegionEnd;
372372 for(;I != MBB->begin(); --I, --RemainingCount) {
373 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
373 if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
374374 break;
375375 }
376376 I = MBB->begin();
377377
378378 // Skip empty scheduling regions.
379379 if (I == RegionEnd) {
380 RegionEnd = llvm::prior(RegionEnd);
380 RegionEnd = std::prev(RegionEnd);
381381 --RemainingCount;
382382 continue;
383383 }
384384 // Skip regions with one instruction.
385 if (I == llvm::prior(RegionEnd)) {
386 RegionEnd = llvm::prior(RegionEnd);
385 if (I == std::prev(RegionEnd)) {
386 RegionEnd = std::prev(RegionEnd);
387387 continue;
388388 }
389389
437437 BI != BE; ++BI) {
438438
439439 MachineBasicBlock &MBB = *BI;
440 for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
440 for (MachineBasicBlock::iterator I = MBB.begin(), Next = std::next(I);
441441 I != MBB.end(); I = Next) {
442442
443 Next = llvm::next(I);
443 Next = std::next(I);
444444 MachineInstr &MI = *I;
445445 if (TII->isDS(MI.getOpcode())) {
446446 NeedM0 = true;
478478 && MBBI->getOperand(1).getReg() == SP::G0
479479 && MBBI->getOperand(2).getReg() == SP::G0);
480480
481 MachineBasicBlock::iterator PrevInst = llvm::prior(MBBI);
481 MachineBasicBlock::iterator PrevInst = std::prev(MBBI);
482482
483483 // It cannot be combined with a bundled instruction.
484484 if (PrevInst->isBundledWithSucc())
29392939
29402940 // Transfer the remainder of BB and its successor edges to sinkMBB.
29412941 sinkMBB->splice(sinkMBB->begin(), BB,
2942 llvm::next(MachineBasicBlock::iterator(MI)),
2942 std::next(MachineBasicBlock::iterator(MI)),
29432943 BB->end());
29442944 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
29452945
157157 continue;
158158 }
159159
160 while (llvm::next(I) != MBB.end())
161 llvm::next(I)->eraseFromParent();
160 while (std::next(I) != MBB.end())
161 std::next(I)->eraseFromParent();
162162
163163 Cond.clear();
164164 FBB = 0;
377377 // Mark the FramePtr as live at the beginning of every block except
378378 // the entry block. (We'll have marked R11 as live on entry when
379379 // saving the GPRs.)
380 for (MachineFunction::iterator
381 I = llvm::next(MF.begin()), E = MF.end(); I != E; ++I)
380 for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
381 I != E; ++I)
382382 I->addLiveIn(SystemZ::R11D);
383383 }
384384
25612561 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
25622562 MachineFunction &MF = *MBB->getParent();
25632563 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
2564 MF.insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
2564 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
25652565 return NewMBB;
25662566 }
25672567
25712571 MachineBasicBlock *MBB) {
25722572 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
25732573 NewMBB->splice(NewMBB->begin(), MBB,
2574 llvm::next(MachineBasicBlock::iterator(MI)),
2575 MBB->end());
2574 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
25762575 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
25772576 return NewMBB;
25782577 }
279279 }
280280
281281 // If the block has any instructions after a JMP, delete them.
282 while (llvm::next(I) != MBB.end())
283 llvm::next(I)->eraseFromParent();
282 while (std::next(I) != MBB.end())
283 std::next(I)->eraseFromParent();
284284
285285 Cond.clear();
286286 FBB = 0;
431431
432432 MachineInstr *PrevMI = 0;
433433 if (I != BB.begin())
434 PrevMI = prior(I);
434 PrevMI = std::prev(I);
435435
436436 ++NumFP; // Keep track of # of pseudo instrs
437437 DEBUG(dbgs() << "\nFPInst:\t" << *MI);
474474 } else {
475475 MachineBasicBlock::iterator Start = I;
476476 // Rewind to first instruction newly inserted.
477 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
477 while (Start != BB.begin() && std::prev(Start) != PrevI) --Start;
478478 dbgs() << "Inserted instructions:\n\t";
479479 Start->print(dbgs(), &MF.getTarget());
480 while (++Start != llvm::next(I)) {}
480 while (++Start != std::next(I)) {}
481481 }
482482 dumpStack();
483483 );
904904
905905 // Kill registers by popping.
906906 if (Kills && I != MBB->begin()) {
907 MachineBasicBlock::iterator I2 = llvm::prior(I);
907 MachineBasicBlock::iterator I2 = std::prev(I);
908908 while (StackTop) {
909909 unsigned KReg = getStackEntry(0);
910910 if (!(Kills & (1 << KReg)))
206206 unsigned StackPtr, uint64_t *NumBytes = NULL) {
207207 if (MBBI == MBB.begin()) return;
208208
209 MachineBasicBlock::iterator PI = prior(MBBI);
209 MachineBasicBlock::iterator PI = std::prev(MBBI);
210210 unsigned Opc = PI->getOpcode();
211211 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
212212 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
234234
235235 if (MBBI == MBB.end()) return;
236236
237 MachineBasicBlock::iterator NI = llvm::next(MBBI);
237 MachineBasicBlock::iterator NI = std::next(MBBI);
238238 if (NI == MBB.end()) return;
239239
240240 unsigned Opc = NI->getOpcode();
267267 (!doMergeWithPrevious && MBBI == MBB.end()))
268268 return 0;
269269
270 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
271 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
270 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
271 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : std::next(MBBI);
272272 unsigned Opc = PI->getOpcode();
273273 int Offset = 0;
274274
536536 }
537537
538538 // Mark the FramePtr as live-in in every block except the entry.
539 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
539 for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
540540 I != E; ++I)
541541 I->addLiveIn(FramePtr);
542542 } else {
782782
783783 // Skip the callee-saved pop instructions.
784784 while (MBBI != MBB.begin()) {
785 MachineBasicBlock::iterator PI = prior(MBBI);
785 MachineBasicBlock::iterator PI = std::prev(MBBI);
786786 unsigned Opc = PI->getOpcode();
787787
788788 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
884884 addReg(JumpTarget.getReg(), RegState::Kill);
885885 }
886886
887 MachineInstr *NewMI = prior(MBBI);
887 MachineInstr *NewMI = std::prev(MBBI);
888888 NewMI->copyImplicitOps(MF, MBBI);
889889
890890 // Delete the pseudo instruction TCRETURN.
15541554 // sure we restore the stack pointer immediately after the call, there may
15551555 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
15561556 MachineBasicBlock::iterator B = MBB.begin();
1557 while (I != B && !llvm::prior(I)->isCall())
1557 while (I != B && !std::prev(I)->isCall())
15581558 --I;
15591559 MBB.insert(I, New);
15601560 }
1444414444
1444514445 // Transfer the remainder of BB and its successor edges to sinkMBB.
1444614446 sinkMBB->splice(sinkMBB->begin(), MBB,
14447 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14447 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1444814448 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
1444914449
1445014450 // thisMBB:
1467814678
1467914679 // Transfer the remainder of BB and its successor edges to sinkMBB.
1468014680 sinkMBB->splice(sinkMBB->begin(), MBB,
14681 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14681 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1468214682 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
1468314683
1468414684 // thisMBB:
1496414964
1496514965 // Transfer the remainder of BB and its successor edges to sinkMBB.
1496614966 sinkMBB->splice(sinkMBB->begin(), MBB,
14967 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14967 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1496814968 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
1496914969
1497014970 // thisMBB:
1536015360
1536115361 // Transfer the remainder of MBB and its successor edges to endMBB.
1536215362 endMBB->splice(endMBB->begin(), thisMBB,
15363 llvm::next(MachineBasicBlock::iterator(MI)),
15364 thisMBB->end());
15363 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
1536515364 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
1536615365
1536715366 // Make offsetMBB and overflowMBB successors of thisMBB
1553115530
1553215531 // Transfer the remainder of MBB and its successor edges to EndMBB.
1553315532 EndMBB->splice(EndMBB->begin(), MBB,
15534 llvm::next(MachineBasicBlock::iterator(MI)),
15535 MBB->end());
15533 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1553615534 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
1553715535
1553815536 // The original block will now fall through to the XMM save block.
1559415592 MachineBasicBlock* BB,
1559515593 const TargetRegisterInfo* TRI) {
1559615594 // Scan forward through BB for a use/def of EFLAGS.
15597 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15595 MachineBasicBlock::iterator miI(std::next(SelectItr));
1559815596 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
1559915597 const MachineInstr& mi = *miI;