llvm.org GIT mirror llvm / d5d864b
CPP backend: set volatile property on atomic instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210890 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 6 years ago
2 changed file(s) with 79 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
15761576 nl(Out) << iName << "->setName(\"";
15771577 printEscapedString(cxi->getName());
15781578 Out << "\");";
1579 nl(Out) << iName << "->setVolatile("
1580 << (cxi->isVolatile() ? "true" : "false") << ");";
15791581 break;
15801582 }
15811583 case Instruction::AtomicRMW: {
16061608 nl(Out) << iName << "->setName(\"";
16071609 printEscapedString(rmwi->getName());
16081610 Out << "\");";
1611 nl(Out) << iName << "->setVolatile("
1612 << (rmwi->isVolatile() ? "true" : "false") << ");";
16091613 break;
16101614 }
16111615 case Instruction::LandingPad: {
0 ; RUN: llc -march=cpp -o - %s | FileCheck %s
1
2 define void @test_atomicrmw(i32* %addr, i32 %inc) {
3 %inst0 = atomicrmw xchg i32* %addr, i32 %inc seq_cst
4 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xchg, {{.*}}, SequentiallyConsistent, CrossThread
5 ; CHECK: [[INST]]->setName("inst0");
6 ; CHECK: [[INST]]->setVolatile(false);
7
8 %inst1 = atomicrmw add i32* %addr, i32 %inc seq_cst
9 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Add, {{.*}}, SequentiallyConsistent, CrossThread
10 ; CHECK: [[INST]]->setName("inst1");
11 ; CHECK: [[INST]]->setVolatile(false);
12
13 %inst2 = atomicrmw volatile sub i32* %addr, i32 %inc singlethread monotonic
14 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Sub, {{.*}}, Monotonic, SingleThread
15 ; CHECK: [[INST]]->setName("inst2");
16 ; CHECK: [[INST]]->setVolatile(true);
17
18 %inst3 = atomicrmw and i32* %addr, i32 %inc acq_rel
19 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::And, {{.*}}, AcquireRelease, CrossThread
20 ; CHECK: [[INST]]->setName("inst3");
21 ; CHECK: [[INST]]->setVolatile(false);
22
23 %inst4 = atomicrmw nand i32* %addr, i32 %inc release
24 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Nand, {{.*}}, Release, CrossThread
25 ; CHECK: [[INST]]->setName("inst4");
26 ; CHECK: [[INST]]->setVolatile(false);
27
28 %inst5 = atomicrmw volatile or i32* %addr, i32 %inc singlethread seq_cst
29 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Or, {{.*}}, SequentiallyConsistent, SingleThread
30 ; CHECK: [[INST]]->setName("inst5");
31 ; CHECK: [[INST]]->setVolatile(true);
32
33 %inst6 = atomicrmw xor i32* %addr, i32 %inc release
34 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xor, {{.*}}, Release, CrossThread
35 ; CHECK: [[INST]]->setName("inst6");
36 ; CHECK: [[INST]]->setVolatile(false);
37
38 %inst7 = atomicrmw volatile max i32* %addr, i32 %inc singlethread monotonic
39 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Max, {{.*}}, Monotonic, SingleThread
40 ; CHECK: [[INST]]->setName("inst7");
41 ; CHECK: [[INST]]->setVolatile(true);
42
43 %inst8 = atomicrmw min i32* %addr, i32 %inc acquire
44 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Min, {{.*}}, Acquire, CrossThread
45 ; CHECK: [[INST]]->setName("inst8");
46 ; CHECK: [[INST]]->setVolatile(false);
47
48 %inst9 = atomicrmw volatile umax i32* %addr, i32 %inc monotonic
49 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMax, {{.*}}, Monotonic, CrossThread
50 ; CHECK: [[INST]]->setName("inst9");
51 ; CHECK: [[INST]]->setVolatile(true);
52
53 %inst10 = atomicrmw umin i32* %addr, i32 %inc singlethread release
54 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMin, {{.*}}, Release, SingleThread
55 ; CHECK: [[INST]]->setName("inst10");
56 ; CHECK: [[INST]]->setVolatile(false);
57
58
59 ret void
60 }
61
62 define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
63 %inst0 = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
64 ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread
65 ; CHECK: [[INST]]->setName("inst0");
66 ; CHECK: [[INST]]->setVolatile(false);
67
68 %inst1 = cmpxchg volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire
69 ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread
70 ; CHECK: [[INST]]->setName("inst1");
71 ; CHECK: [[INST]]->setVolatile(true);
72
73 ret void
74 }