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[docs] Document how to debug instruction scheduling model generation Describe: + Exact tablegen command and how to get it + tablegen command debug option for subtarget generation + Use of schedcover.py on the debug output to determine coverage Differential Revision: https://reviews.llvm.org/D35058 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308476 91177308-0d34-0410-b5e6-96231b3b80d8 Joel Jones 2 years ago
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10101010 value can be named by an enumemation in llvm::XXX::Sched namespace generated
10111011 by TableGen in XXXGenInstrInfo.inc. The name of the schedule classes are
10121012 the same as provided in XXXSchedule.td plus a default NoItinerary class.
1013
1014 The schedule models are generated by TableGen by the SubtargetEmitter,
1015 using the ``CodeGenSchedModels`` class. This is distinct from the itinerary
1016 method of specifying machine resource use. The tool ``utils/schedcover.py``
1017 can be used to determine which instructions have been covered by the
1018 schedule model description and which haven't. The first step is to use the
1019 instructions below to create an output file. Then run ``schedcover.py`` on the
1020 output file:
1021
1022 .. code-block:: shell
1023
1024 $ /utils/schedcover.py /lib/Target/AArch64/tblGenSubtarget.with
1025 instruction, default, CortexA53Model, CortexA57Model, CycloneModel, ExynosM1Model, FalkorModel, KryoModel, ThunderX2T99Model, ThunderXT8XModel
1026 ABSv16i8, WriteV, , , CyWriteV3, M1WriteNMISC1, FalkorWr_2VXVY_2cyc, KryoWrite_2cyc_XY_XY_150ln, ,
1027 ABSv1i64, WriteV, , , CyWriteV3, M1WriteNMISC1, FalkorWr_1VXVY_2cyc, KryoWrite_2cyc_XY_noRSV_67ln, ,
1028 ...
1029
1030 To capture the debug output from generating a schedule model, change to the
1031 appropriate target directory and use the following command:
1032 command with the ``subtarget-emitter`` debug option:
1033
1034 .. code-block:: shell
1035
1036 $ /bin/llvm-tblgen -debug-only=subtarget-emitter -gen-subtarget \
1037 -I /lib/Target/ -I /include \
1038 -I /lib/Target /lib/Target//.td \
1039 -o /lib/Target//GenSubtargetInfo.inc.tmp \
1040 > tblGenSubtarget.dbg 2>&1
1041
1042 Where ```` is the build directory, ``src`` is the source directory,
1043 and ```` is the name of the target.
1044 To double check that the above command is what is needed, one can capture the
1045 exact TableGen command from a build by using:
1046
1047 .. code-block:: shell
1048
1049 $ VERBOSE=1 make ...
1050
1051 and search for ``llvm-tblgen`` commands in the output.
1052
10131053
10141054 Instruction Relation Mapping
10151055 ----------------------------