llvm.org GIT mirror llvm / d5a79b9
AMDGPU: Consolidate some getGeneration checks This is incomplete, and ideally these would all be removed, but it's better to localize them to the subtarget first with comments about what they're for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363902 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 26 days ago
9 changed file(s) with 82 addition(s) and 31 deletion(s). Raw diff Collapse all Expand all
10991099 (OffsetBits == 8 && !isUInt<8>(Offset)))
11001100 return false;
11011101
1102 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
1102 if (Subtarget->hasUsableDSOffset() ||
11031103 Subtarget->unsafeDSOffsetFoldingEnabled())
11041104 return true;
11051105
13621362 SDValue Ptr, Offen, Idxen, Addr64;
13631363
13641364 // addr64 bit was removed for volcanic islands.
1365 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1365 if (!Subtarget->hasAddr64())
13661366 return false;
13671367
13681368 if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
24142414 }
24152415
24162416 bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
2417 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
2418 return false;
2419 }
2417 assert(CurDAG->getTarget().getTargetTriple().getArch() == Triple::amdgcn);
2418
24202419 const SIRegisterInfo *SIRI =
24212420 static_cast(Subtarget->getRegisterInfo());
24222421 const SIInstrInfo * SII =
442442 unsigned MemSize = Query.MMODescrs[0].SizeInBits;
443443 return (MemSize == 96) &&
444444 Query.Types[0].isVector() &&
445 ST.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS;
445 !ST.hasDwordx3LoadStores();
446446 },
447447 [=](const LegalityQuery &Query) {
448448 return std::make_pair(0, V2S32);
470470 return true;
471471
472472 case 96:
473 // XXX hasLoadX3
474 return (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS);
473 return ST.hasDwordx3LoadStores();
475474
476475 case 256:
477476 case 512:
110110 // integer types.
111111 if ((PT->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
112112 PT->getAddressSpace() == AMDGPUAS::REGION_ADDRESS) &&
113 ST.getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
113 !ST.hasUsableDSOffset())
114114 continue;
115115
116116 // FIXME: We can replace this with equivalent alias.scope/noalias
483483 return (getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS);
484484 }
485485
486 // Return true if the target only has the reverse operand versions of VALU
487 // shift instructions (e.g. v_lshrrev_b32, and no v_lshr_b32).
488 bool hasOnlyRevVALUShifts() const {
489 return getGeneration() >= VOLCANIC_ISLANDS;
490 }
491
486492 bool hasBFE() const {
487493 return true;
488494 }
535541 return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
536542 }
537543
544 /// True if the offset field of DS instructions works as expected. On SI, the
545 /// offset uses a 16-bit adder and does not always wrap properly.
546 bool hasUsableDSOffset() const {
547 return getGeneration() >= SEA_ISLANDS;
548 }
549
538550 bool unsafeDSOffsetFoldingEnabled() const {
539551 return EnableUnsafeDSOffsetFolding;
552 }
553
554 /// Condition output from div_scale is usable.
555 bool hasUsableDivScaleConditionOutput() const {
556 return getGeneration() != SOUTHERN_ISLANDS;
557 }
558
559 /// Extra wait hazard is needed in some cases before
560 /// s_cbranch_vccnz/s_cbranch_vccz.
561 bool hasReadVCCZBug() const {
562 return getGeneration() <= SEA_ISLANDS;
563 }
564
565 /// A read of an SGPR by SMRD instruction requires 4 wait states when the SGPR
566 /// was written by a VALU instruction.
567 bool hasSMRDReadVALUDefHazard() const {
568 return getGeneration() == SOUTHERN_ISLANDS;
569 }
570
571 /// A read of an SGPR by a VMEM instruction requires 5 wait states when the
572 /// SGPR was written by a VALU Instruction.
573 bool hasVMEMReadSGPRVALUDefHazard() const {
574 return getGeneration() >= VOLCANIC_ISLANDS;
575 }
576
577 bool hasRFEHazards() const {
578 return getGeneration() >= VOLCANIC_ISLANDS;
579 }
580
581 /// Number of hazard wait states for s_setreg_b32/s_setreg_imm32_b32.
582 unsigned getSetRegWaitStates() const {
583 return getGeneration() <= SEA_ISLANDS ? 1 : 2;
540584 }
541585
542586 bool dumpCode() const {
570614 return CIInsts && EnableDS128;
571615 }
572616
617 /// Have v_trunc_f64, v_ceil_f64, v_rndne_f64
618 bool haveRoundOpsF64() const {
619 return CIInsts;
620 }
621
573622 /// \returns If MUBUF instructions always perform range checking, even for
574623 /// buffer resources used for private memory access.
575624 bool privateMemoryResourceIsRangeChecked() const {
619668 return FlatAddressSpace;
620669 }
621670
671 bool hasFlatScrRegister() const {
672 return hasFlatAddressSpace();
673 }
674
622675 bool hasFlatInstOffsets() const {
623676 return FlatInstOffsets;
624677 }
649702
650703 bool d16PreservesUnusedBits() const {
651704 return hasD16LoadStore() && !isSRAMECCEnabled();
705 }
706
707 bool hasD16Images() const {
708 return getGeneration() >= VOLCANIC_ISLANDS;
652709 }
653710
654711 /// Return if most LDS instructions have an m0 use that require m0 to be
400400 if (SLT == MVT::f64) {
401401 int Cost = 4 * get64BitInstrCost() + 7 * getQuarterRateInstrCost();
402402 // Add cost of workaround.
403 if (ST->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
403 if (!ST->hasUsableDivScaleConditionOutput())
404404 Cost += 3 * getFullRateInstrCost();
405405
406406 return LT.first * Cost * NElts;
521521 WaitStatesNeeded = checkSoftClauseHazards(SMRD);
522522
523523 // This SMRD hazard only affects SI.
524 if (ST.getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS)
524 if (!ST.hasSMRDReadVALUDefHazard())
525525 return WaitStatesNeeded;
526526
527527 // A read of an SGPR by SMRD instruction requires 4 wait states when the
560560 }
561561
562562 int GCNHazardRecognizer::checkVMEMHazards(MachineInstr* VMEM) {
563 if (ST.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
563 if (!ST.hasVMEMReadSGPRVALUDefHazard())
564564 return 0;
565565
566566 int WaitStatesNeeded = checkSoftClauseHazards(VMEM);
639639 const SIInstrInfo *TII = ST.getInstrInfo();
640640 unsigned HWReg = getHWReg(TII, *SetRegInstr);
641641
642 const int SetRegWaitStates =
643 ST.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ? 1 : 2;
642 const int SetRegWaitStates = ST.getSetRegWaitStates();
644643 auto IsHazardFn = [TII, HWReg] (MachineInstr *MI) {
645644 return HWReg == getHWReg(TII, *MI);
646645 };
786785 }
787786
788787 int GCNHazardRecognizer::checkRFEHazards(MachineInstr *RFE) {
789 if (ST.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
788 if (!ST.hasRFEHazards())
790789 return 0;
791790
792791 const SIInstrInfo *TII = ST.getInstrInfo();
422422 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
423423
424424
425 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
425 if (Subtarget->haveRoundOpsF64()) {
426426 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
427427 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
428428 setOperationAction(ISD::FRINT, MVT::f64, Legal);
28642864
28652865 }
28662866
2867 if ((Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||
2868 Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10) &&
2867 if (!Subtarget->hasFlatScrRegister() &&
28692868 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
28702869 report_fatal_error(Twine("invalid register \""
28712870 + StringRef(RegName) + "\" for subtarget."));
49784977
49794978 MVT StoreVT = VData.getSimpleValueType();
49804979 if (StoreVT.getScalarType() == MVT::f16) {
4981 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS ||
4982 !BaseOpcode->HasD16)
4980 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
49834981 return Op; // D16 is unsupported for this instruction
49844982
49854983 IsD16 = true;
49924990 // and whether packing is supported.
49934991 MVT LoadVT = ResultTypes[0].getSimpleVT();
49944992 if (LoadVT.getScalarType() == MVT::f16) {
4995 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS ||
4996 !BaseOpcode->HasD16)
4993 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
49974994 return Op; // D16 is unsupported for this instruction
49984995
49994996 IsD16 = true;
72617258
72627259 SDValue Scale;
72637260
7264 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
7261 if (!Subtarget->hasUsableDivScaleConditionOutput()) {
72657262 // Workaround a hardware bug on SI where the condition output from div_scale
72667263 // is not usable.
72677264
73817378 // out-of-bounds even if base + offsets is in bounds. Split vectorized
73827379 // stores here to avoid emitting ds_write2_b32. We may re-combine the
73837380 // store later in the SILoadStoreOptimizer.
7384 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
7381 if (!Subtarget->hasUsableDSOffset() &&
73857382 NumElements == 2 && VT.getStoreSize() == 8 &&
73867383 Store->getAlignment() < 8) {
73877384 return SplitVectorStore(Op, DAG);
10411041 // TODO: Remove this work-around, enable the assert for Bug 457939
10421042 // after fixing the scheduler. Also, the Shader Compiler code is
10431043 // independent of target.
1044 if (readsVCCZ(MI) && ST->getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS) {
1044 if (readsVCCZ(MI) && ST->hasReadVCCZBug()) {
10451045 if (ScoreBrackets.getScoreLB(LGKM_CNT) <
10461046 ScoreBrackets.getScoreUB(LGKM_CNT) &&
10471047 ScoreBrackets.hasPendingEvent(SMEM_ACCESS)) {
45964596 continue;
45974597
45984598 case AMDGPU::S_LSHL_B32:
4599 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4599 if (ST.hasOnlyRevVALUShifts()) {
46004600 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
46014601 swapOperands(Inst);
46024602 }
46034603 break;
46044604 case AMDGPU::S_ASHR_I32:
4605 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4605 if (ST.hasOnlyRevVALUShifts()) {
46064606 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
46074607 swapOperands(Inst);
46084608 }
46094609 break;
46104610 case AMDGPU::S_LSHR_B32:
4611 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4611 if (ST.hasOnlyRevVALUShifts()) {
46124612 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
46134613 swapOperands(Inst);
46144614 }
46154615 break;
46164616 case AMDGPU::S_LSHL_B64:
4617 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4617 if (ST.hasOnlyRevVALUShifts()) {
46184618 NewOpcode = AMDGPU::V_LSHLREV_B64;
46194619 swapOperands(Inst);
46204620 }
46214621 break;
46224622 case AMDGPU::S_ASHR_I64:
4623 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4623 if (ST.hasOnlyRevVALUShifts()) {
46244624 NewOpcode = AMDGPU::V_ASHRREV_I64;
46254625 swapOperands(Inst);
46264626 }
46274627 break;
46284628 case AMDGPU::S_LSHR_B64:
4629 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4629 if (ST.hasOnlyRevVALUShifts()) {
46304630 NewOpcode = AMDGPU::V_LSHRREV_B64;
46314631 swapOperands(Inst);
46324632 }