llvm.org GIT mirror llvm / d585dc1
AMDGPU/GlobalISel: Use a more correct getValueMapping This was finding the wrong size registers for anything with more than 2 components. Patch by Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326483 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
1 changed file(s) with 56 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
1515
1616 enum PartialMappingIdx {
1717 None = - 1,
18 PM_SGPR32 = 0,
19 PM_SGPR64 = 1,
20 PM_VGPR32 = 2,
21 PM_VGPR64 = 3,
22 PM_SGPR1 = 4,
23 PM_VGPR1 = 5,
18 PM_SGPR1 = 0,
19 PM_SGPR16 = 4,
20 PM_SGPR32 = 5,
21 PM_SGPR64 = 6,
22 PM_SGPR128 = 7,
23 PM_SGPR256 = 8,
24 PM_SGPR512 = 9,
25 PM_VGPR1 = 10,
26 PM_VGPR16 = 14,
27 PM_VGPR32 = 15,
28 PM_VGPR64 = 16,
29 PM_VGPR128 = 17,
30 PM_VGPR256 = 18,
31 PM_VGPR512 = 19,
32 PM_SGPR96 = 20,
33 PM_VGPR96 = 21
2434 };
2535
2636 const RegisterBankInfo::PartialMapping PartMappings[] {
2737 // StartIdx, Length, RegBank
38 {0, 1, SCCRegBank},
39 {0, 16, SGPRRegBank},
2840 {0, 32, SGPRRegBank},
2941 {0, 64, SGPRRegBank},
42 {0, 128, SGPRRegBank},
43 {0, 256, SGPRRegBank},
44 {0, 512, SGPRRegBank},
45 {0, 1, SGPRRegBank},
46 {0, 16, VGPRRegBank},
3047 {0, 32, VGPRRegBank},
3148 {0, 64, VGPRRegBank},
32 {0, 1, SCCRegBank},
33 {0, 1, SGPRRegBank}
49 {0, 128, VGPRRegBank},
50 {0, 256, VGPRRegBank},
51 {0, 512, VGPRRegBank},
52 {0, 96, SGPRRegBank},
53 {0, 96, VGPRRegBank},
3454 };
3555
3656 const RegisterBankInfo::ValueMapping ValMappings[] {
37 // SGPR 32-bit
3857 {&PartMappings[0], 1},
39 // SGPR 64-bit
58 {nullptr, 0},
59 {nullptr, 0},
60 {nullptr, 0},
4061 {&PartMappings[1], 1},
41 // VGPR 32-bit
4262 {&PartMappings[2], 1},
43 // VGPR 64-bit
4463 {&PartMappings[3], 1},
4564 {&PartMappings[4], 1},
46 {&PartMappings[5], 1}
65 {&PartMappings[5], 1},
66 {&PartMappings[6], 1},
67 {&PartMappings[7], 1},
68 {nullptr, 0},
69 {nullptr, 0},
70 {nullptr, 0},
71 {&PartMappings[8], 1},
72 {&PartMappings[9], 1},
73 {&PartMappings[10], 1},
74 {&PartMappings[11], 1},
75 {&PartMappings[12], 1},
76 {&PartMappings[13], 1},
77 {&PartMappings[14], 1},
78 {&PartMappings[15], 1}
4779 };
4880
4981 enum ValueMappingIdx {
5082 SGPRStartIdx = 0,
51 VGPRStartIdx = 2
83 VGPRStartIdx = 10
5284 };
5385
5486 const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
5587 unsigned Size) {
5688 unsigned Idx;
57 if (Size == 1) {
89 switch (Size) {
90 case 1:
5891 Idx = BankID == AMDGPU::SCCRegBankID ? PM_SGPR1 : PM_VGPR1;
59 } else {
60 assert(Size % 32 == 0);
61 Idx = BankID == AMDGPU::SGPRRegBankID ? SGPRStartIdx : VGPRStartIdx;
62 Idx += (Size / 32) - 1;
92 break;
93 case 96:
94 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
95 break;
96 default:
97 Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx;
98 Idx += llvm::countTrailingZeros(Size);
99 break;
63100 }
64101 return &ValMappings[Idx];
65102 }