llvm.org GIT mirror llvm / d580c5b
[RISCV] Optimize emission of SELECT sequences This patch optimizes the emission of a sequence of SELECTs with the same condition, avoiding the insertion of unnecessary control flow. Such a sequence often occurs when a SELECT of values wider than XLEN is legalized into two SELECTs with legal types. We have identified several use cases where the SELECTs could be interleaved with other instructions. Therefore, we extend the sequence to include non-SELECT instructions if we are able to detect that the non-SELECT instructions do not impact the optimization. This patch supersedes https://reviews.llvm.org/D59096, which attempted to address this issue by introducing a new SelectionDAG node. Hat tip to Eli Friedman for his feedback on how to best handle this issue. Differential Revision: https://reviews.llvm.org/D59355 Patch by Luís Marques. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356741 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 1 year, 8 months ago
4 changed file(s) with 825 addition(s) and 438 deletion(s). Raw diff Collapse all Expand all
1616 #include "RISCVRegisterInfo.h"
1717 #include "RISCVSubtarget.h"
1818 #include "RISCVTargetMachine.h"
19 #include "llvm/ADT/SmallSet.h"
1920 #include "llvm/ADT/Statistic.h"
2021 #include "llvm/CodeGen/CallingConvLower.h"
2122 #include "llvm/CodeGen/MachineFrameInfo.h"
786787 return BB;
787788 }
788789
790 static bool isSelectPseudo(MachineInstr &MI) {
791 switch (MI.getOpcode()) {
792 default:
793 return false;
794 case RISCV::Select_GPR_Using_CC_GPR:
795 case RISCV::Select_FPR32_Using_CC_GPR:
796 case RISCV::Select_FPR64_Using_CC_GPR:
797 return true;
798 }
799 }
800
789801 static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
790802 MachineBasicBlock *BB) {
791 // To "insert" a SELECT instruction, we actually have to insert the triangle
792 // control-flow pattern. The incoming instruction knows the destination vreg
803 // To "insert" Select_* instructions, we actually have to insert the triangle
804 // control-flow pattern. The incoming instructions know the destination vreg
793805 // to set, the condition code register to branch on, the true/false values to
794806 // select between, and the condcode to use to select the appropriate branch.
795807 //
799811 // | IfFalseMBB
800812 // | /
801813 // TailMBB
814 //
815 // When we find a sequence of selects we attempt to optimize their emission
816 // by sharing the control flow. Currently we only handle cases where we have
817 // multiple selects with the exact same condition (same LHS, RHS and CC).
818 // The selects may be interleaved with other instructions if the other
819 // instructions meet some requirements we deem safe:
820 // - They are debug instructions. Otherwise,
821 // - They do not have side-effects, do not access memory and their inputs do
822 // not depend on the results of the select pseudo-instructions.
823 // The TrueV/FalseV operands of the selects cannot depend on the result of
824 // previous selects in the sequence.
825 // These conditions could be further relaxed. See the X86 target for a
826 // related approach and more information.
827 unsigned LHS = MI.getOperand(1).getReg();
828 unsigned RHS = MI.getOperand(2).getReg();
829 auto CC = static_cast(MI.getOperand(3).getImm());
830
831 SmallVector SelectDebugValues;
832 SmallSet SelectDests;
833 SelectDests.insert(MI.getOperand(0).getReg());
834
835 MachineInstr *LastSelectPseudo = &MI;
836
837 for (auto E = BB->end(), SequenceMBBI = MachineBasicBlock::iterator(MI);
838 SequenceMBBI != E; ++SequenceMBBI) {
839 if (SequenceMBBI->isDebugInstr())
840 continue;
841 else if (isSelectPseudo(*SequenceMBBI)) {
842 if (SequenceMBBI->getOperand(1).getReg() != LHS ||
843 SequenceMBBI->getOperand(2).getReg() != RHS ||
844 SequenceMBBI->getOperand(3).getImm() != CC ||
845 SelectDests.count(SequenceMBBI->getOperand(4).getReg()) ||
846 SelectDests.count(SequenceMBBI->getOperand(5).getReg()))
847 break;
848 LastSelectPseudo = &*SequenceMBBI;
849 SequenceMBBI->collectDebugValues(SelectDebugValues);
850 SelectDests.insert(SequenceMBBI->getOperand(0).getReg());
851 } else {
852 if (SequenceMBBI->hasUnmodeledSideEffects() ||
853 SequenceMBBI->mayLoadOrStore())
854 break;
855 if (llvm::any_of(SequenceMBBI->operands(), [&](MachineOperand &MO) {
856 return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg());
857 }))
858 break;
859 }
860 }
861
802862 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
803863 const BasicBlock *LLVM_BB = BB->getBasicBlock();
804864 DebugLoc DL = MI.getDebugLoc();
811871
812872 F->insert(I, IfFalseMBB);
813873 F->insert(I, TailMBB);
814 // Move all remaining instructions to TailMBB.
815 TailMBB->splice(TailMBB->begin(), HeadMBB, std::next(MI.getIterator()),
816 HeadMBB->end());
874
875 // Transfer debug instructions associated with the selects to TailMBB.
876 for (MachineInstr *DebugInstr : SelectDebugValues) {
877 TailMBB->push_back(DebugInstr->removeFromParent());
878 }
879
880 // Move all instructions after the sequence to TailMBB.
881 TailMBB->splice(TailMBB->end(), HeadMBB,
882 std::next(LastSelectPseudo->getIterator()), HeadMBB->end());
817883 // Update machine-CFG edges by transferring all successors of the current
818 // block to the new block which will contain the Phi node for the select.
884 // block to the new block which will contain the Phi nodes for the selects.
819885 TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB);
820886 // Set the successors for HeadMBB.
821887 HeadMBB->addSuccessor(IfFalseMBB);
822888 HeadMBB->addSuccessor(TailMBB);
823889
824890 // Insert appropriate branch.
825 unsigned LHS = MI.getOperand(1).getReg();
826 unsigned RHS = MI.getOperand(2).getReg();
827 auto CC = static_cast(MI.getOperand(3).getImm());
828891 unsigned Opcode = getBranchOpcodeForIntCondCode(CC);
829892
830893 BuildMI(HeadMBB, DL, TII.get(Opcode))
835898 // IfFalseMBB just falls through to TailMBB.
836899 IfFalseMBB->addSuccessor(TailMBB);
837900
838 // %Result = phi [ %TrueValue, HeadMBB ], [ %FalseValue, IfFalseMBB ]
839 BuildMI(*TailMBB, TailMBB->begin(), DL, TII.get(RISCV::PHI),
840 MI.getOperand(0).getReg())
841 .addReg(MI.getOperand(4).getReg())
842 .addMBB(HeadMBB)
843 .addReg(MI.getOperand(5).getReg())
844 .addMBB(IfFalseMBB);
845
846 MI.eraseFromParent(); // The pseudo instruction is gone now.
901 // Create PHIs for all of the select pseudo-instructions.
902 auto SelectMBBI = MI.getIterator();
903 auto SelectEnd = std::next(LastSelectPseudo->getIterator());
904 auto InsertionPoint = TailMBB->begin();
905 while (SelectMBBI != SelectEnd) {
906 auto Next = std::next(SelectMBBI);
907 if (isSelectPseudo(*SelectMBBI)) {
908 // %Result = phi [ %TrueValue, HeadMBB ], [ %FalseValue, IfFalseMBB ]
909 BuildMI(*TailMBB, InsertionPoint, SelectMBBI->getDebugLoc(),
910 TII.get(RISCV::PHI), SelectMBBI->getOperand(0).getReg())
911 .addReg(SelectMBBI->getOperand(4).getReg())
912 .addMBB(HeadMBB)
913 .addReg(SelectMBBI->getOperand(5).getReg())
914 .addMBB(IfFalseMBB);
915 SelectMBBI->eraseFromParent();
916 }
917 SelectMBBI = Next;
918 }
919
847920 return TailMBB;
848921 }
849922
1457314573 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
1457414574 ; RV32I-NEXT: # in Loop: Header=BB200_1 Depth=1
1457514575 ; RV32I-NEXT: slt a0, s0, a1
14576 ; RV32I-NEXT: sw a2, 0(sp)
14577 ; RV32I-NEXT: beqz a0, .LBB200_4
14578 ; RV32I-NEXT: j .LBB200_5
14576 ; RV32I-NEXT: j .LBB200_4
1457914577 ; RV32I-NEXT: .LBB200_3: # in Loop: Header=BB200_1 Depth=1
1458014578 ; RV32I-NEXT: sltu a0, s2, a2
14581 ; RV32I-NEXT: sw a2, 0(sp)
14582 ; RV32I-NEXT: bnez a0, .LBB200_5
1458314579 ; RV32I-NEXT: .LBB200_4: # %atomicrmw.start
1458414580 ; RV32I-NEXT: # in Loop: Header=BB200_1 Depth=1
14581 ; RV32I-NEXT: sw a2, 0(sp)
14582 ; RV32I-NEXT: mv a3, a1
14583 ; RV32I-NEXT: bnez a0, .LBB200_6
14584 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
14585 ; RV32I-NEXT: # in Loop: Header=BB200_1 Depth=1
1458514586 ; RV32I-NEXT: mv a2, s2
14586 ; RV32I-NEXT: .LBB200_5: # %atomicrmw.start
14587 ; RV32I-NEXT: # in Loop: Header=BB200_1 Depth=1
14588 ; RV32I-NEXT: mv a3, a1
14589 ; RV32I-NEXT: bnez a0, .LBB200_7
14590 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
14591 ; RV32I-NEXT: # in Loop: Header=BB200_1 Depth=1
1459214587 ; RV32I-NEXT: mv a3, s0
14593 ; RV32I-NEXT: .LBB200_7: # %atomicrmw.start
14588 ; RV32I-NEXT: .LBB200_6: # %atomicrmw.start
1459414589 ; RV32I-NEXT: # in Loop: Header=BB200_1 Depth=1
1459514590 ; RV32I-NEXT: sw a1, 4(sp)
1459614591 ; RV32I-NEXT: mv a0, s1
1460114596 ; RV32I-NEXT: lw a1, 4(sp)
1460214597 ; RV32I-NEXT: lw a2, 0(sp)
1460314598 ; RV32I-NEXT: beqz a0, .LBB200_1
14604 ; RV32I-NEXT: # %bb.8: # %atomicrmw.end
14599 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1460514600 ; RV32I-NEXT: mv a0, a2
1460614601 ; RV32I-NEXT: lw s3, 12(sp)
1460714602 ; RV32I-NEXT: lw s2, 16(sp)
1463114626 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
1463214627 ; RV32IA-NEXT: # in Loop: Header=BB200_1 Depth=1
1463314628 ; RV32IA-NEXT: slt a0, s0, a1
14634 ; RV32IA-NEXT: sw a2, 0(sp)
14635 ; RV32IA-NEXT: beqz a0, .LBB200_4
14636 ; RV32IA-NEXT: j .LBB200_5
14629 ; RV32IA-NEXT: j .LBB200_4
1463714630 ; RV32IA-NEXT: .LBB200_3: # in Loop: Header=BB200_1 Depth=1
1463814631 ; RV32IA-NEXT: sltu a0, s2, a2
14639 ; RV32IA-NEXT: sw a2, 0(sp)
14640 ; RV32IA-NEXT: bnez a0, .LBB200_5
1464114632 ; RV32IA-NEXT: .LBB200_4: # %atomicrmw.start
1464214633 ; RV32IA-NEXT: # in Loop: Header=BB200_1 Depth=1
14634 ; RV32IA-NEXT: sw a2, 0(sp)
14635 ; RV32IA-NEXT: mv a3, a1
14636 ; RV32IA-NEXT: bnez a0, .LBB200_6
14637 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
14638 ; RV32IA-NEXT: # in Loop: Header=BB200_1 Depth=1
1464314639 ; RV32IA-NEXT: mv a2, s2
14644 ; RV32IA-NEXT: .LBB200_5: # %atomicrmw.start
14645 ; RV32IA-NEXT: # in Loop: Header=BB200_1 Depth=1
14646 ; RV32IA-NEXT: mv a3, a1
14647 ; RV32IA-NEXT: bnez a0, .LBB200_7
14648 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
14649 ; RV32IA-NEXT: # in Loop: Header=BB200_1 Depth=1
1465014640 ; RV32IA-NEXT: mv a3, s0
14651 ; RV32IA-NEXT: .LBB200_7: # %atomicrmw.start
14641 ; RV32IA-NEXT: .LBB200_6: # %atomicrmw.start
1465214642 ; RV32IA-NEXT: # in Loop: Header=BB200_1 Depth=1
1465314643 ; RV32IA-NEXT: sw a1, 4(sp)
1465414644 ; RV32IA-NEXT: mv a0, s1
1465914649 ; RV32IA-NEXT: lw a1, 4(sp)
1466014650 ; RV32IA-NEXT: lw a2, 0(sp)
1466114651 ; RV32IA-NEXT: beqz a0, .LBB200_1
14662 ; RV32IA-NEXT: # %bb.8: # %atomicrmw.end
14652 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1466314653 ; RV32IA-NEXT: mv a0, a2
1466414654 ; RV32IA-NEXT: lw s3, 12(sp)
1466514655 ; RV32IA-NEXT: lw s2, 16(sp)
1473414724 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
1473514725 ; RV32I-NEXT: # in Loop: Header=BB201_1 Depth=1
1473614726 ; RV32I-NEXT: slt a0, s0, a1
14737 ; RV32I-NEXT: sw a2, 0(sp)
14738 ; RV32I-NEXT: beqz a0, .LBB201_4
14739 ; RV32I-NEXT: j .LBB201_5
14727 ; RV32I-NEXT: j .LBB201_4
1474014728 ; RV32I-NEXT: .LBB201_3: # in Loop: Header=BB201_1 Depth=1
1474114729 ; RV32I-NEXT: sltu a0, s2, a2
14742 ; RV32I-NEXT: sw a2, 0(sp)
14743 ; RV32I-NEXT: bnez a0, .LBB201_5
1474414730 ; RV32I-NEXT: .LBB201_4: # %atomicrmw.start
1474514731 ; RV32I-NEXT: # in Loop: Header=BB201_1 Depth=1
14732 ; RV32I-NEXT: sw a2, 0(sp)
14733 ; RV32I-NEXT: mv a3, a1
14734 ; RV32I-NEXT: bnez a0, .LBB201_6
14735 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
14736 ; RV32I-NEXT: # in Loop: Header=BB201_1 Depth=1
1474614737 ; RV32I-NEXT: mv a2, s2
14747 ; RV32I-NEXT: .LBB201_5: # %atomicrmw.start
14748 ; RV32I-NEXT: # in Loop: Header=BB201_1 Depth=1
14749 ; RV32I-NEXT: mv a3, a1
14750 ; RV32I-NEXT: bnez a0, .LBB201_7
14751 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
14752 ; RV32I-NEXT: # in Loop: Header=BB201_1 Depth=1
1475314738 ; RV32I-NEXT: mv a3, s0
14754 ; RV32I-NEXT: .LBB201_7: # %atomicrmw.start
14739 ; RV32I-NEXT: .LBB201_6: # %atomicrmw.start
1475514740 ; RV32I-NEXT: # in Loop: Header=BB201_1 Depth=1
1475614741 ; RV32I-NEXT: sw a1, 4(sp)
1475714742 ; RV32I-NEXT: mv a0, s1
1476214747 ; RV32I-NEXT: lw a1, 4(sp)
1476314748 ; RV32I-NEXT: lw a2, 0(sp)
1476414749 ; RV32I-NEXT: beqz a0, .LBB201_1
14765 ; RV32I-NEXT: # %bb.8: # %atomicrmw.end
14750 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1476614751 ; RV32I-NEXT: mv a0, a2
1476714752 ; RV32I-NEXT: lw s3, 12(sp)
1476814753 ; RV32I-NEXT: lw s2, 16(sp)
1479214777 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
1479314778 ; RV32IA-NEXT: # in Loop: Header=BB201_1 Depth=1
1479414779 ; RV32IA-NEXT: slt a0, s0, a1
14795 ; RV32IA-NEXT: sw a2, 0(sp)
14796 ; RV32IA-NEXT: beqz a0, .LBB201_4
14797 ; RV32IA-NEXT: j .LBB201_5
14780 ; RV32IA-NEXT: j .LBB201_4
1479814781 ; RV32IA-NEXT: .LBB201_3: # in Loop: Header=BB201_1 Depth=1
1479914782 ; RV32IA-NEXT: sltu a0, s2, a2
14800 ; RV32IA-NEXT: sw a2, 0(sp)
14801 ; RV32IA-NEXT: bnez a0, .LBB201_5
1480214783 ; RV32IA-NEXT: .LBB201_4: # %atomicrmw.start
1480314784 ; RV32IA-NEXT: # in Loop: Header=BB201_1 Depth=1
14785 ; RV32IA-NEXT: sw a2, 0(sp)
14786 ; RV32IA-NEXT: mv a3, a1
14787 ; RV32IA-NEXT: bnez a0, .LBB201_6
14788 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
14789 ; RV32IA-NEXT: # in Loop: Header=BB201_1 Depth=1
1480414790 ; RV32IA-NEXT: mv a2, s2
14805 ; RV32IA-NEXT: .LBB201_5: # %atomicrmw.start
14806 ; RV32IA-NEXT: # in Loop: Header=BB201_1 Depth=1
14807 ; RV32IA-NEXT: mv a3, a1
14808 ; RV32IA-NEXT: bnez a0, .LBB201_7
14809 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
14810 ; RV32IA-NEXT: # in Loop: Header=BB201_1 Depth=1
1481114791 ; RV32IA-NEXT: mv a3, s0
14812 ; RV32IA-NEXT: .LBB201_7: # %atomicrmw.start
14792 ; RV32IA-NEXT: .LBB201_6: # %atomicrmw.start
1481314793 ; RV32IA-NEXT: # in Loop: Header=BB201_1 Depth=1
1481414794 ; RV32IA-NEXT: sw a1, 4(sp)
1481514795 ; RV32IA-NEXT: mv a0, s1
1482014800 ; RV32IA-NEXT: lw a1, 4(sp)
1482114801 ; RV32IA-NEXT: lw a2, 0(sp)
1482214802 ; RV32IA-NEXT: beqz a0, .LBB201_1
14823 ; RV32IA-NEXT: # %bb.8: # %atomicrmw.end
14803 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1482414804 ; RV32IA-NEXT: mv a0, a2
1482514805 ; RV32IA-NEXT: lw s3, 12(sp)
1482614806 ; RV32IA-NEXT: lw s2, 16(sp)
1489514875 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
1489614876 ; RV32I-NEXT: # in Loop: Header=BB202_1 Depth=1
1489714877 ; RV32I-NEXT: slt a0, s0, a1
14898 ; RV32I-NEXT: sw a2, 0(sp)
14899 ; RV32I-NEXT: beqz a0, .LBB202_4
14900 ; RV32I-NEXT: j .LBB202_5
14878 ; RV32I-NEXT: j .LBB202_4
1490114879 ; RV32I-NEXT: .LBB202_3: # in Loop: Header=BB202_1 Depth=1
1490214880 ; RV32I-NEXT: sltu a0, s2, a2
14903 ; RV32I-NEXT: sw a2, 0(sp)
14904 ; RV32I-NEXT: bnez a0, .LBB202_5
1490514881 ; RV32I-NEXT: .LBB202_4: # %atomicrmw.start
1490614882 ; RV32I-NEXT: # in Loop: Header=BB202_1 Depth=1
14883 ; RV32I-NEXT: sw a2, 0(sp)
14884 ; RV32I-NEXT: mv a3, a1
14885 ; RV32I-NEXT: bnez a0, .LBB202_6
14886 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
14887 ; RV32I-NEXT: # in Loop: Header=BB202_1 Depth=1
1490714888 ; RV32I-NEXT: mv a2, s2
14908 ; RV32I-NEXT: .LBB202_5: # %atomicrmw.start
14909 ; RV32I-NEXT: # in Loop: Header=BB202_1 Depth=1
14910 ; RV32I-NEXT: mv a3, a1
14911 ; RV32I-NEXT: bnez a0, .LBB202_7
14912 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
14913 ; RV32I-NEXT: # in Loop: Header=BB202_1 Depth=1
1491414889 ; RV32I-NEXT: mv a3, s0
14915 ; RV32I-NEXT: .LBB202_7: # %atomicrmw.start
14890 ; RV32I-NEXT: .LBB202_6: # %atomicrmw.start
1491614891 ; RV32I-NEXT: # in Loop: Header=BB202_1 Depth=1
1491714892 ; RV32I-NEXT: sw a1, 4(sp)
1491814893 ; RV32I-NEXT: mv a0, s1
1492314898 ; RV32I-NEXT: lw a1, 4(sp)
1492414899 ; RV32I-NEXT: lw a2, 0(sp)
1492514900 ; RV32I-NEXT: beqz a0, .LBB202_1
14926 ; RV32I-NEXT: # %bb.8: # %atomicrmw.end
14901 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1492714902 ; RV32I-NEXT: mv a0, a2
1492814903 ; RV32I-NEXT: lw s3, 12(sp)
1492914904 ; RV32I-NEXT: lw s2, 16(sp)
1495314928 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
1495414929 ; RV32IA-NEXT: # in Loop: Header=BB202_1 Depth=1
1495514930 ; RV32IA-NEXT: slt a0, s0, a1
14956 ; RV32IA-NEXT: sw a2, 0(sp)
14957 ; RV32IA-NEXT: beqz a0, .LBB202_4
14958 ; RV32IA-NEXT: j .LBB202_5
14931 ; RV32IA-NEXT: j .LBB202_4
1495914932 ; RV32IA-NEXT: .LBB202_3: # in Loop: Header=BB202_1 Depth=1
1496014933 ; RV32IA-NEXT: sltu a0, s2, a2
14961 ; RV32IA-NEXT: sw a2, 0(sp)
14962 ; RV32IA-NEXT: bnez a0, .LBB202_5
1496314934 ; RV32IA-NEXT: .LBB202_4: # %atomicrmw.start
1496414935 ; RV32IA-NEXT: # in Loop: Header=BB202_1 Depth=1
14936 ; RV32IA-NEXT: sw a2, 0(sp)
14937 ; RV32IA-NEXT: mv a3, a1
14938 ; RV32IA-NEXT: bnez a0, .LBB202_6
14939 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
14940 ; RV32IA-NEXT: # in Loop: Header=BB202_1 Depth=1
1496514941 ; RV32IA-NEXT: mv a2, s2
14966 ; RV32IA-NEXT: .LBB202_5: # %atomicrmw.start
14967 ; RV32IA-NEXT: # in Loop: Header=BB202_1 Depth=1
14968 ; RV32IA-NEXT: mv a3, a1
14969 ; RV32IA-NEXT: bnez a0, .LBB202_7
14970 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
14971 ; RV32IA-NEXT: # in Loop: Header=BB202_1 Depth=1
1497214942 ; RV32IA-NEXT: mv a3, s0
14973 ; RV32IA-NEXT: .LBB202_7: # %atomicrmw.start
14943 ; RV32IA-NEXT: .LBB202_6: # %atomicrmw.start
1497414944 ; RV32IA-NEXT: # in Loop: Header=BB202_1 Depth=1
1497514945 ; RV32IA-NEXT: sw a1, 4(sp)
1497614946 ; RV32IA-NEXT: mv a0, s1
1498114951 ; RV32IA-NEXT: lw a1, 4(sp)
1498214952 ; RV32IA-NEXT: lw a2, 0(sp)
1498314953 ; RV32IA-NEXT: beqz a0, .LBB202_1
14984 ; RV32IA-NEXT: # %bb.8: # %atomicrmw.end
14954 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1498514955 ; RV32IA-NEXT: mv a0, a2
1498614956 ; RV32IA-NEXT: lw s3, 12(sp)
1498714957 ; RV32IA-NEXT: lw s2, 16(sp)
1505615026 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
1505715027 ; RV32I-NEXT: # in Loop: Header=BB203_1 Depth=1
1505815028 ; RV32I-NEXT: slt a0, s0, a1
15059 ; RV32I-NEXT: sw a2, 0(sp)
15060 ; RV32I-NEXT: beqz a0, .LBB203_4
15061 ; RV32I-NEXT: j .LBB203_5
15029 ; RV32I-NEXT: j .LBB203_4
1506215030 ; RV32I-NEXT: .LBB203_3: # in Loop: Header=BB203_1 Depth=1
1506315031 ; RV32I-NEXT: sltu a0, s2, a2
15064 ; RV32I-NEXT: sw a2, 0(sp)
15065 ; RV32I-NEXT: bnez a0, .LBB203_5
1506615032 ; RV32I-NEXT: .LBB203_4: # %atomicrmw.start
1506715033 ; RV32I-NEXT: # in Loop: Header=BB203_1 Depth=1
15034 ; RV32I-NEXT: sw a2, 0(sp)
15035 ; RV32I-NEXT: mv a3, a1
15036 ; RV32I-NEXT: bnez a0, .LBB203_6
15037 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
15038 ; RV32I-NEXT: # in Loop: Header=BB203_1 Depth=1
1506815039 ; RV32I-NEXT: mv a2, s2
15069 ; RV32I-NEXT: .LBB203_5: # %atomicrmw.start
15070 ; RV32I-NEXT: # in Loop: Header=BB203_1 Depth=1
15071 ; RV32I-NEXT: mv a3, a1
15072 ; RV32I-NEXT: bnez a0, .LBB203_7
15073 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
15074 ; RV32I-NEXT: # in Loop: Header=BB203_1 Depth=1
1507515040 ; RV32I-NEXT: mv a3, s0
15076 ; RV32I-NEXT: .LBB203_7: # %atomicrmw.start
15041 ; RV32I-NEXT: .LBB203_6: # %atomicrmw.start
1507715042 ; RV32I-NEXT: # in Loop: Header=BB203_1 Depth=1
1507815043 ; RV32I-NEXT: sw a1, 4(sp)
1507915044 ; RV32I-NEXT: mv a0, s1
1508415049 ; RV32I-NEXT: lw a1, 4(sp)
1508515050 ; RV32I-NEXT: lw a2, 0(sp)
1508615051 ; RV32I-NEXT: beqz a0, .LBB203_1
15087 ; RV32I-NEXT: # %bb.8: # %atomicrmw.end
15052 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1508815053 ; RV32I-NEXT: mv a0, a2
1508915054 ; RV32I-NEXT: lw s3, 12(sp)
1509015055 ; RV32I-NEXT: lw s2, 16(sp)
1511415079 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
1511515080 ; RV32IA-NEXT: # in Loop: Header=BB203_1 Depth=1
1511615081 ; RV32IA-NEXT: slt a0, s0, a1
15117 ; RV32IA-NEXT: sw a2, 0(sp)
15118 ; RV32IA-NEXT: beqz a0, .LBB203_4
15119 ; RV32IA-NEXT: j .LBB203_5
15082 ; RV32IA-NEXT: j .LBB203_4
1512015083 ; RV32IA-NEXT: .LBB203_3: # in Loop: Header=BB203_1 Depth=1
1512115084 ; RV32IA-NEXT: sltu a0, s2, a2
15122 ; RV32IA-NEXT: sw a2, 0(sp)
15123 ; RV32IA-NEXT: bnez a0, .LBB203_5
1512415085 ; RV32IA-NEXT: .LBB203_4: # %atomicrmw.start
1512515086 ; RV32IA-NEXT: # in Loop: Header=BB203_1 Depth=1
15087 ; RV32IA-NEXT: sw a2, 0(sp)
15088 ; RV32IA-NEXT: mv a3, a1
15089 ; RV32IA-NEXT: bnez a0, .LBB203_6
15090 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
15091 ; RV32IA-NEXT: # in Loop: Header=BB203_1 Depth=1
1512615092 ; RV32IA-NEXT: mv a2, s2
15127 ; RV32IA-NEXT: .LBB203_5: # %atomicrmw.start
15128 ; RV32IA-NEXT: # in Loop: Header=BB203_1 Depth=1
15129 ; RV32IA-NEXT: mv a3, a1
15130 ; RV32IA-NEXT: bnez a0, .LBB203_7
15131 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
15132 ; RV32IA-NEXT: # in Loop: Header=BB203_1 Depth=1
1513315093 ; RV32IA-NEXT: mv a3, s0
15134 ; RV32IA-NEXT: .LBB203_7: # %atomicrmw.start
15094 ; RV32IA-NEXT: .LBB203_6: # %atomicrmw.start
1513515095 ; RV32IA-NEXT: # in Loop: Header=BB203_1 Depth=1
1513615096 ; RV32IA-NEXT: sw a1, 4(sp)
1513715097 ; RV32IA-NEXT: mv a0, s1
1514215102 ; RV32IA-NEXT: lw a1, 4(sp)
1514315103 ; RV32IA-NEXT: lw a2, 0(sp)
1514415104 ; RV32IA-NEXT: beqz a0, .LBB203_1
15145 ; RV32IA-NEXT: # %bb.8: # %atomicrmw.end
15105 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1514615106 ; RV32IA-NEXT: mv a0, a2
1514715107 ; RV32IA-NEXT: lw s3, 12(sp)
1514815108 ; RV32IA-NEXT: lw s2, 16(sp)
1521715177 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
1521815178 ; RV32I-NEXT: # in Loop: Header=BB204_1 Depth=1
1521915179 ; RV32I-NEXT: slt a0, s0, a1
15220 ; RV32I-NEXT: sw a2, 0(sp)
15221 ; RV32I-NEXT: beqz a0, .LBB204_4
15222 ; RV32I-NEXT: j .LBB204_5
15180 ; RV32I-NEXT: j .LBB204_4
1522315181 ; RV32I-NEXT: .LBB204_3: # in Loop: Header=BB204_1 Depth=1
1522415182 ; RV32I-NEXT: sltu a0, s2, a2
15225 ; RV32I-NEXT: sw a2, 0(sp)
15226 ; RV32I-NEXT: bnez a0, .LBB204_5
1522715183 ; RV32I-NEXT: .LBB204_4: # %atomicrmw.start
1522815184 ; RV32I-NEXT: # in Loop: Header=BB204_1 Depth=1
15185 ; RV32I-NEXT: sw a2, 0(sp)
15186 ; RV32I-NEXT: mv a3, a1
15187 ; RV32I-NEXT: bnez a0, .LBB204_6
15188 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
15189 ; RV32I-NEXT: # in Loop: Header=BB204_1 Depth=1
1522915190 ; RV32I-NEXT: mv a2, s2
15230 ; RV32I-NEXT: .LBB204_5: # %atomicrmw.start
15231 ; RV32I-NEXT: # in Loop: Header=BB204_1 Depth=1
15232 ; RV32I-NEXT: mv a3, a1
15233 ; RV32I-NEXT: bnez a0, .LBB204_7
15234 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
15235 ; RV32I-NEXT: # in Loop: Header=BB204_1 Depth=1
1523615191 ; RV32I-NEXT: mv a3, s0
15237 ; RV32I-NEXT: .LBB204_7: # %atomicrmw.start
15192 ; RV32I-NEXT: .LBB204_6: # %atomicrmw.start
1523815193 ; RV32I-NEXT: # in Loop: Header=BB204_1 Depth=1
1523915194 ; RV32I-NEXT: sw a1, 4(sp)
1524015195 ; RV32I-NEXT: mv a0, s1
1524515200 ; RV32I-NEXT: lw a1, 4(sp)
1524615201 ; RV32I-NEXT: lw a2, 0(sp)
1524715202 ; RV32I-NEXT: beqz a0, .LBB204_1
15248 ; RV32I-NEXT: # %bb.8: # %atomicrmw.end
15203 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1524915204 ; RV32I-NEXT: mv a0, a2
1525015205 ; RV32I-NEXT: lw s3, 12(sp)
1525115206 ; RV32I-NEXT: lw s2, 16(sp)
1527515230 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
1527615231 ; RV32IA-NEXT: # in Loop: Header=BB204_1 Depth=1
1527715232 ; RV32IA-NEXT: slt a0, s0, a1
15278 ; RV32IA-NEXT: sw a2, 0(sp)
15279 ; RV32IA-NEXT: beqz a0, .LBB204_4
15280 ; RV32IA-NEXT: j .LBB204_5
15233 ; RV32IA-NEXT: j .LBB204_4
1528115234 ; RV32IA-NEXT: .LBB204_3: # in Loop: Header=BB204_1 Depth=1
1528215235 ; RV32IA-NEXT: sltu a0, s2, a2
15283 ; RV32IA-NEXT: sw a2, 0(sp)
15284 ; RV32IA-NEXT: bnez a0, .LBB204_5
1528515236 ; RV32IA-NEXT: .LBB204_4: # %atomicrmw.start
1528615237 ; RV32IA-NEXT: # in Loop: Header=BB204_1 Depth=1
15238 ; RV32IA-NEXT: sw a2, 0(sp)
15239 ; RV32IA-NEXT: mv a3, a1
15240 ; RV32IA-NEXT: bnez a0, .LBB204_6
15241 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
15242 ; RV32IA-NEXT: # in Loop: Header=BB204_1 Depth=1
1528715243 ; RV32IA-NEXT: mv a2, s2
15288 ; RV32IA-NEXT: .LBB204_5: # %atomicrmw.start
15289 ; RV32IA-NEXT: # in Loop: Header=BB204_1 Depth=1
15290 ; RV32IA-NEXT: mv a3, a1
15291 ; RV32IA-NEXT: bnez a0, .LBB204_7
15292 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
15293 ; RV32IA-NEXT: # in Loop: Header=BB204_1 Depth=1
1529415244 ; RV32IA-NEXT: mv a3, s0
15295 ; RV32IA-NEXT: .LBB204_7: # %atomicrmw.start
15245 ; RV32IA-NEXT: .LBB204_6: # %atomicrmw.start
1529615246 ; RV32IA-NEXT: # in Loop: Header=BB204_1 Depth=1
1529715247 ; RV32IA-NEXT: sw a1, 4(sp)
1529815248 ; RV32IA-NEXT: mv a0, s1
1530315253 ; RV32IA-NEXT: lw a1, 4(sp)
1530415254 ; RV32IA-NEXT: lw a2, 0(sp)
1530515255 ; RV32IA-NEXT: beqz a0, .LBB204_1
15306 ; RV32IA-NEXT: # %bb.8: # %atomicrmw.end
15256 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1530715257 ; RV32IA-NEXT: mv a0, a2
1530815258 ; RV32IA-NEXT: lw s3, 12(sp)
1530915259 ; RV32IA-NEXT: lw s2, 16(sp)
1538515335 ; RV32I-NEXT: # in Loop: Header=BB205_1 Depth=1
1538615336 ; RV32I-NEXT: xori a0, a0, 1
1538715337 ; RV32I-NEXT: sw a2, 0(sp)
15338 ; RV32I-NEXT: mv a3, a1
1538815339 ; RV32I-NEXT: bnez a0, .LBB205_6
1538915340 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
1539015341 ; RV32I-NEXT: # in Loop: Header=BB205_1 Depth=1
1539115342 ; RV32I-NEXT: mv a2, s2
15343 ; RV32I-NEXT: mv a3, s0
1539215344 ; RV32I-NEXT: .LBB205_6: # %atomicrmw.start
15393 ; RV32I-NEXT: # in Loop: Header=BB205_1 Depth=1
15394 ; RV32I-NEXT: mv a3, a1
15395 ; RV32I-NEXT: bnez a0, .LBB205_8
15396 ; RV32I-NEXT: # %bb.7: # %atomicrmw.start
15397 ; RV32I-NEXT: # in Loop: Header=BB205_1 Depth=1
15398 ; RV32I-NEXT: mv a3, s0
15399 ; RV32I-NEXT: .LBB205_8: # %atomicrmw.start
1540015345 ; RV32I-NEXT: # in Loop: Header=BB205_1 Depth=1
1540115346 ; RV32I-NEXT: sw a1, 4(sp)
1540215347 ; RV32I-NEXT: mv a0, s1
1540715352 ; RV32I-NEXT: lw a1, 4(sp)
1540815353 ; RV32I-NEXT: lw a2, 0(sp)
1540915354 ; RV32I-NEXT: beqz a0, .LBB205_1
15410 ; RV32I-NEXT: # %bb.9: # %atomicrmw.end
15355 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1541115356 ; RV32I-NEXT: mv a0, a2
1541215357 ; RV32I-NEXT: lw s3, 12(sp)
1541315358 ; RV32I-NEXT: lw s2, 16(sp)
1544415389 ; RV32IA-NEXT: # in Loop: Header=BB205_1 Depth=1
1544515390 ; RV32IA-NEXT: xori a0, a0, 1
1544615391 ; RV32IA-NEXT: sw a2, 0(sp)
15392 ; RV32IA-NEXT: mv a3, a1
1544715393 ; RV32IA-NEXT: bnez a0, .LBB205_6
1544815394 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
1544915395 ; RV32IA-NEXT: # in Loop: Header=BB205_1 Depth=1
1545015396 ; RV32IA-NEXT: mv a2, s2
15397 ; RV32IA-NEXT: mv a3, s0
1545115398 ; RV32IA-NEXT: .LBB205_6: # %atomicrmw.start
15452 ; RV32IA-NEXT: # in Loop: Header=BB205_1 Depth=1
15453 ; RV32IA-NEXT: mv a3, a1
15454 ; RV32IA-NEXT: bnez a0, .LBB205_8
15455 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.start
15456 ; RV32IA-NEXT: # in Loop: Header=BB205_1 Depth=1
15457 ; RV32IA-NEXT: mv a3, s0
15458 ; RV32IA-NEXT: .LBB205_8: # %atomicrmw.start
1545915399 ; RV32IA-NEXT: # in Loop: Header=BB205_1 Depth=1
1546015400 ; RV32IA-NEXT: sw a1, 4(sp)
1546115401 ; RV32IA-NEXT: mv a0, s1
1546615406 ; RV32IA-NEXT: lw a1, 4(sp)
1546715407 ; RV32IA-NEXT: lw a2, 0(sp)
1546815408 ; RV32IA-NEXT: beqz a0, .LBB205_1
15469 ; RV32IA-NEXT: # %bb.9: # %atomicrmw.end
15409 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1547015410 ; RV32IA-NEXT: mv a0, a2
1547115411 ; RV32IA-NEXT: lw s3, 12(sp)
1547215412 ; RV32IA-NEXT: lw s2, 16(sp)
1554815488 ; RV32I-NEXT: # in Loop: Header=BB206_1 Depth=1
1554915489 ; RV32I-NEXT: xori a0, a0, 1
1555015490 ; RV32I-NEXT: sw a2, 0(sp)
15491 ; RV32I-NEXT: mv a3, a1
1555115492 ; RV32I-NEXT: bnez a0, .LBB206_6
1555215493 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
1555315494 ; RV32I-NEXT: # in Loop: Header=BB206_1 Depth=1
1555415495 ; RV32I-NEXT: mv a2, s2
15496 ; RV32I-NEXT: mv a3, s0
1555515497 ; RV32I-NEXT: .LBB206_6: # %atomicrmw.start
15556 ; RV32I-NEXT: # in Loop: Header=BB206_1 Depth=1
15557 ; RV32I-NEXT: mv a3, a1
15558 ; RV32I-NEXT: bnez a0, .LBB206_8
15559 ; RV32I-NEXT: # %bb.7: # %atomicrmw.start
15560 ; RV32I-NEXT: # in Loop: Header=BB206_1 Depth=1
15561 ; RV32I-NEXT: mv a3, s0
15562 ; RV32I-NEXT: .LBB206_8: # %atomicrmw.start
1556315498 ; RV32I-NEXT: # in Loop: Header=BB206_1 Depth=1
1556415499 ; RV32I-NEXT: sw a1, 4(sp)
1556515500 ; RV32I-NEXT: mv a0, s1
1557015505 ; RV32I-NEXT: lw a1, 4(sp)
1557115506 ; RV32I-NEXT: lw a2, 0(sp)
1557215507 ; RV32I-NEXT: beqz a0, .LBB206_1
15573 ; RV32I-NEXT: # %bb.9: # %atomicrmw.end
15508 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1557415509 ; RV32I-NEXT: mv a0, a2
1557515510 ; RV32I-NEXT: lw s3, 12(sp)
1557615511 ; RV32I-NEXT: lw s2, 16(sp)
1560715542 ; RV32IA-NEXT: # in Loop: Header=BB206_1 Depth=1
1560815543 ; RV32IA-NEXT: xori a0, a0, 1
1560915544 ; RV32IA-NEXT: sw a2, 0(sp)
15545 ; RV32IA-NEXT: mv a3, a1
1561015546 ; RV32IA-NEXT: bnez a0, .LBB206_6
1561115547 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
1561215548 ; RV32IA-NEXT: # in Loop: Header=BB206_1 Depth=1
1561315549 ; RV32IA-NEXT: mv a2, s2
15550 ; RV32IA-NEXT: mv a3, s0
1561415551 ; RV32IA-NEXT: .LBB206_6: # %atomicrmw.start
15615 ; RV32IA-NEXT: # in Loop: Header=BB206_1 Depth=1
15616 ; RV32IA-NEXT: mv a3, a1
15617 ; RV32IA-NEXT: bnez a0, .LBB206_8
15618 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.start
15619 ; RV32IA-NEXT: # in Loop: Header=BB206_1 Depth=1
15620 ; RV32IA-NEXT: mv a3, s0
15621 ; RV32IA-NEXT: .LBB206_8: # %atomicrmw.start
1562215552 ; RV32IA-NEXT: # in Loop: Header=BB206_1 Depth=1
1562315553 ; RV32IA-NEXT: sw a1, 4(sp)
1562415554 ; RV32IA-NEXT: mv a0, s1
1562915559 ; RV32IA-NEXT: lw a1, 4(sp)
1563015560 ; RV32IA-NEXT: lw a2, 0(sp)
1563115561 ; RV32IA-NEXT: beqz a0, .LBB206_1
15632 ; RV32IA-NEXT: # %bb.9: # %atomicrmw.end
15562 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1563315563 ; RV32IA-NEXT: mv a0, a2
1563415564 ; RV32IA-NEXT: lw s3, 12(sp)
1563515565 ; RV32IA-NEXT: lw s2, 16(sp)
1571115641 ; RV32I-NEXT: # in Loop: Header=BB207_1 Depth=1
1571215642 ; RV32I-NEXT: xori a0, a0, 1
1571315643 ; RV32I-NEXT: sw a2, 0(sp)
15644 ; RV32I-NEXT: mv a3, a1
1571415645 ; RV32I-NEXT: bnez a0, .LBB207_6
1571515646 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
1571615647 ; RV32I-NEXT: # in Loop: Header=BB207_1 Depth=1
1571715648 ; RV32I-NEXT: mv a2, s2
15649 ; RV32I-NEXT: mv a3, s0
1571815650 ; RV32I-NEXT: .LBB207_6: # %atomicrmw.start
15719 ; RV32I-NEXT: # in Loop: Header=BB207_1 Depth=1
15720 ; RV32I-NEXT: mv a3, a1
15721 ; RV32I-NEXT: bnez a0, .LBB207_8
15722 ; RV32I-NEXT: # %bb.7: # %atomicrmw.start
15723 ; RV32I-NEXT: # in Loop: Header=BB207_1 Depth=1
15724 ; RV32I-NEXT: mv a3, s0
15725 ; RV32I-NEXT: .LBB207_8: # %atomicrmw.start
1572615651 ; RV32I-NEXT: # in Loop: Header=BB207_1 Depth=1
1572715652 ; RV32I-NEXT: sw a1, 4(sp)
1572815653 ; RV32I-NEXT: mv a0, s1
1573315658 ; RV32I-NEXT: lw a1, 4(sp)
1573415659 ; RV32I-NEXT: lw a2, 0(sp)
1573515660 ; RV32I-NEXT: beqz a0, .LBB207_1
15736 ; RV32I-NEXT: # %bb.9: # %atomicrmw.end
15661 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1573715662 ; RV32I-NEXT: mv a0, a2
1573815663 ; RV32I-NEXT: lw s3, 12(sp)
1573915664 ; RV32I-NEXT: lw s2, 16(sp)
1577015695 ; RV32IA-NEXT: # in Loop: Header=BB207_1 Depth=1
1577115696 ; RV32IA-NEXT: xori a0, a0, 1
1577215697 ; RV32IA-NEXT: sw a2, 0(sp)
15698 ; RV32IA-NEXT: mv a3, a1
1577315699 ; RV32IA-NEXT: bnez a0, .LBB207_6
1577415700 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
1577515701 ; RV32IA-NEXT: # in Loop: Header=BB207_1 Depth=1
1577615702 ; RV32IA-NEXT: mv a2, s2
15703 ; RV32IA-NEXT: mv a3, s0
1577715704 ; RV32IA-NEXT: .LBB207_6: # %atomicrmw.start
15778 ; RV32IA-NEXT: # in Loop: Header=BB207_1 Depth=1
15779 ; RV32IA-NEXT: mv a3, a1
15780 ; RV32IA-NEXT: bnez a0, .LBB207_8
15781 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.start
15782 ; RV32IA-NEXT: # in Loop: Header=BB207_1 Depth=1
15783 ; RV32IA-NEXT: mv a3, s0
15784 ; RV32IA-NEXT: .LBB207_8: # %atomicrmw.start
1578515705 ; RV32IA-NEXT: # in Loop: Header=BB207_1 Depth=1
1578615706 ; RV32IA-NEXT: sw a1, 4(sp)
1578715707 ; RV32IA-NEXT: mv a0, s1
1579215712 ; RV32IA-NEXT: lw a1, 4(sp)
1579315713 ; RV32IA-NEXT: lw a2, 0(sp)
1579415714 ; RV32IA-NEXT: beqz a0, .LBB207_1
15795 ; RV32IA-NEXT: # %bb.9: # %atomicrmw.end
15715 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1579615716 ; RV32IA-NEXT: mv a0, a2
1579715717 ; RV32IA-NEXT: lw s3, 12(sp)
1579815718 ; RV32IA-NEXT: lw s2, 16(sp)
1587415794 ; RV32I-NEXT: # in Loop: Header=BB208_1 Depth=1
1587515795 ; RV32I-NEXT: xori a0, a0, 1
1587615796 ; RV32I-NEXT: sw a2, 0(sp)
15797 ; RV32I-NEXT: mv a3, a1
1587715798 ; RV32I-NEXT: bnez a0, .LBB208_6
1587815799 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
1587915800 ; RV32I-NEXT: # in Loop: Header=BB208_1 Depth=1
1588015801 ; RV32I-NEXT: mv a2, s2
15802 ; RV32I-NEXT: mv a3, s0
1588115803 ; RV32I-NEXT: .LBB208_6: # %atomicrmw.start
15882 ; RV32I-NEXT: # in Loop: Header=BB208_1 Depth=1
15883 ; RV32I-NEXT: mv a3, a1
15884 ; RV32I-NEXT: bnez a0, .LBB208_8
15885 ; RV32I-NEXT: # %bb.7: # %atomicrmw.start
15886 ; RV32I-NEXT: # in Loop: Header=BB208_1 Depth=1
15887 ; RV32I-NEXT: mv a3, s0
15888 ; RV32I-NEXT: .LBB208_8: # %atomicrmw.start
1588915804 ; RV32I-NEXT: # in Loop: Header=BB208_1 Depth=1
1589015805 ; RV32I-NEXT: sw a1, 4(sp)
1589115806 ; RV32I-NEXT: mv a0, s1
1589615811 ; RV32I-NEXT: lw a1, 4(sp)
1589715812 ; RV32I-NEXT: lw a2, 0(sp)
1589815813 ; RV32I-NEXT: beqz a0, .LBB208_1
15899 ; RV32I-NEXT: # %bb.9: # %atomicrmw.end
15814 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1590015815 ; RV32I-NEXT: mv a0, a2
1590115816 ; RV32I-NEXT: lw s3, 12(sp)
1590215817 ; RV32I-NEXT: lw s2, 16(sp)
1593315848 ; RV32IA-NEXT: # in Loop: Header=BB208_1 Depth=1
1593415849 ; RV32IA-NEXT: xori a0, a0, 1
1593515850 ; RV32IA-NEXT: sw a2, 0(sp)
15851 ; RV32IA-NEXT: mv a3, a1
1593615852 ; RV32IA-NEXT: bnez a0, .LBB208_6
1593715853 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
1593815854 ; RV32IA-NEXT: # in Loop: Header=BB208_1 Depth=1
1593915855 ; RV32IA-NEXT: mv a2, s2
15856 ; RV32IA-NEXT: mv a3, s0
1594015857 ; RV32IA-NEXT: .LBB208_6: # %atomicrmw.start
15941 ; RV32IA-NEXT: # in Loop: Header=BB208_1 Depth=1
15942 ; RV32IA-NEXT: mv a3, a1
15943 ; RV32IA-NEXT: bnez a0, .LBB208_8
15944 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.start
15945 ; RV32IA-NEXT: # in Loop: Header=BB208_1 Depth=1
15946 ; RV32IA-NEXT: mv a3, s0
15947 ; RV32IA-NEXT: .LBB208_8: # %atomicrmw.start
1594815858 ; RV32IA-NEXT: # in Loop: Header=BB208_1 Depth=1
1594915859 ; RV32IA-NEXT: sw a1, 4(sp)
1595015860 ; RV32IA-NEXT: mv a0, s1
1595515865 ; RV32IA-NEXT: lw a1, 4(sp)
1595615866 ; RV32IA-NEXT: lw a2, 0(sp)
1595715867 ; RV32IA-NEXT: beqz a0, .LBB208_1
15958 ; RV32IA-NEXT: # %bb.9: # %atomicrmw.end
15868 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1595915869 ; RV32IA-NEXT: mv a0, a2
1596015870 ; RV32IA-NEXT: lw s3, 12(sp)
1596115871 ; RV32IA-NEXT: lw s2, 16(sp)
1603715947 ; RV32I-NEXT: # in Loop: Header=BB209_1 Depth=1
1603815948 ; RV32I-NEXT: xori a0, a0, 1
1603915949 ; RV32I-NEXT: sw a2, 0(sp)
15950 ; RV32I-NEXT: mv a3, a1
1604015951 ; RV32I-NEXT: bnez a0, .LBB209_6
1604115952 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
1604215953 ; RV32I-NEXT: # in Loop: Header=BB209_1 Depth=1
1604315954 ; RV32I-NEXT: mv a2, s2
15955 ; RV32I-NEXT: mv a3, s0
1604415956 ; RV32I-NEXT: .LBB209_6: # %atomicrmw.start
16045 ; RV32I-NEXT: # in Loop: Header=BB209_1 Depth=1
16046 ; RV32I-NEXT: mv a3, a1
16047 ; RV32I-NEXT: bnez a0, .LBB209_8
16048 ; RV32I-NEXT: # %bb.7: # %atomicrmw.start
16049 ; RV32I-NEXT: # in Loop: Header=BB209_1 Depth=1
16050 ; RV32I-NEXT: mv a3, s0
16051 ; RV32I-NEXT: .LBB209_8: # %atomicrmw.start
1605215957 ; RV32I-NEXT: # in Loop: Header=BB209_1 Depth=1
1605315958 ; RV32I-NEXT: sw a1, 4(sp)
1605415959 ; RV32I-NEXT: mv a0, s1
1605915964 ; RV32I-NEXT: lw a1, 4(sp)
1606015965 ; RV32I-NEXT: lw a2, 0(sp)
1606115966 ; RV32I-NEXT: beqz a0, .LBB209_1
16062 ; RV32I-NEXT: # %bb.9: # %atomicrmw.end
15967 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1606315968 ; RV32I-NEXT: mv a0, a2
1606415969 ; RV32I-NEXT: lw s3, 12(sp)
1606515970 ; RV32I-NEXT: lw s2, 16(sp)
1609616001 ; RV32IA-NEXT: # in Loop: Header=BB209_1 Depth=1
1609716002 ; RV32IA-NEXT: xori a0, a0, 1
1609816003 ; RV32IA-NEXT: sw a2, 0(sp)
16004 ; RV32IA-NEXT: mv a3, a1
1609916005 ; RV32IA-NEXT: bnez a0, .LBB209_6
1610016006 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
1610116007 ; RV32IA-NEXT: # in Loop: Header=BB209_1 Depth=1
1610216008 ; RV32IA-NEXT: mv a2, s2
16009 ; RV32IA-NEXT: mv a3, s0
1610316010 ; RV32IA-NEXT: .LBB209_6: # %atomicrmw.start
16104 ; RV32IA-NEXT: # in Loop: Header=BB209_1 Depth=1
16105 ; RV32IA-NEXT: mv a3, a1
16106 ; RV32IA-NEXT: bnez a0, .LBB209_8
16107 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.start
16108 ; RV32IA-NEXT: # in Loop: Header=BB209_1 Depth=1
16109 ; RV32IA-NEXT: mv a3, s0
16110 ; RV32IA-NEXT: .LBB209_8: # %atomicrmw.start
1611116011 ; RV32IA-NEXT: # in Loop: Header=BB209_1 Depth=1
1611216012 ; RV32IA-NEXT: sw a1, 4(sp)
1611316013 ; RV32IA-NEXT: mv a0, s1
1611816018 ; RV32IA-NEXT: lw a1, 4(sp)
1611916019 ; RV32IA-NEXT: lw a2, 0(sp)
1612016020 ; RV32IA-NEXT: beqz a0, .LBB209_1
16121 ; RV32IA-NEXT: # %bb.9: # %atomicrmw.end
16021 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1612216022 ; RV32IA-NEXT: mv a0, a2
1612316023 ; RV32IA-NEXT: lw s3, 12(sp)
1612416024 ; RV32IA-NEXT: lw s2, 16(sp)
1619316093 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
1619416094 ; RV32I-NEXT: # in Loop: Header=BB210_1 Depth=1
1619516095 ; RV32I-NEXT: sltu a0, s0, a1
16196 ; RV32I-NEXT: sw a2, 0(sp)
16197 ; RV32I-NEXT: beqz a0, .LBB210_4
16198 ; RV32I-NEXT: j .LBB210_5
16096 ; RV32I-NEXT: j .LBB210_4
1619916097 ; RV32I-NEXT: .LBB210_3: # in Loop: Header=BB210_1 Depth=1
1620016098 ; RV32I-NEXT: sltu a0, s2, a2
16201 ; RV32I-NEXT: sw a2, 0(sp)
16202 ; RV32I-NEXT: bnez a0, .LBB210_5
1620316099 ; RV32I-NEXT: .LBB210_4: # %atomicrmw.start
1620416100 ; RV32I-NEXT: # in Loop: Header=BB210_1 Depth=1
16101 ; RV32I-NEXT: sw a2, 0(sp)
16102 ; RV32I-NEXT: mv a3, a1
16103 ; RV32I-NEXT: bnez a0, .LBB210_6
16104 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
16105 ; RV32I-NEXT: # in Loop: Header=BB210_1 Depth=1
1620516106 ; RV32I-NEXT: mv a2, s2
16206 ; RV32I-NEXT: .LBB210_5: # %atomicrmw.start
16207 ; RV32I-NEXT: # in Loop: Header=BB210_1 Depth=1
16208 ; RV32I-NEXT: mv a3, a1
16209 ; RV32I-NEXT: bnez a0, .LBB210_7
16210 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
16211 ; RV32I-NEXT: # in Loop: Header=BB210_1 Depth=1
1621216107 ; RV32I-NEXT: mv a3, s0
16213 ; RV32I-NEXT: .LBB210_7: # %atomicrmw.start
16108 ; RV32I-NEXT: .LBB210_6: # %atomicrmw.start
1621416109 ; RV32I-NEXT: # in Loop: Header=BB210_1 Depth=1
1621516110 ; RV32I-NEXT: sw a1, 4(sp)
1621616111 ; RV32I-NEXT: mv a0, s1
1622116116 ; RV32I-NEXT: lw a1, 4(sp)
1622216117 ; RV32I-NEXT: lw a2, 0(sp)
1622316118 ; RV32I-NEXT: beqz a0, .LBB210_1
16224 ; RV32I-NEXT: # %bb.8: # %atomicrmw.end
16119 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1622516120 ; RV32I-NEXT: mv a0, a2
1622616121 ; RV32I-NEXT: lw s3, 12(sp)
1622716122 ; RV32I-NEXT: lw s2, 16(sp)
1625116146 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
1625216147 ; RV32IA-NEXT: # in Loop: Header=BB210_1 Depth=1
1625316148 ; RV32IA-NEXT: sltu a0, s0, a1
16254 ; RV32IA-NEXT: sw a2, 0(sp)
16255 ; RV32IA-NEXT: beqz a0, .LBB210_4
16256 ; RV32IA-NEXT: j .LBB210_5
16149 ; RV32IA-NEXT: j .LBB210_4
1625716150 ; RV32IA-NEXT: .LBB210_3: # in Loop: Header=BB210_1 Depth=1
1625816151 ; RV32IA-NEXT: sltu a0, s2, a2
16259 ; RV32IA-NEXT: sw a2, 0(sp)
16260 ; RV32IA-NEXT: bnez a0, .LBB210_5
1626116152 ; RV32IA-NEXT: .LBB210_4: # %atomicrmw.start
1626216153 ; RV32IA-NEXT: # in Loop: Header=BB210_1 Depth=1
16154 ; RV32IA-NEXT: sw a2, 0(sp)
16155 ; RV32IA-NEXT: mv a3, a1
16156 ; RV32IA-NEXT: bnez a0, .LBB210_6
16157 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
16158 ; RV32IA-NEXT: # in Loop: Header=BB210_1 Depth=1
1626316159 ; RV32IA-NEXT: mv a2, s2
16264 ; RV32IA-NEXT: .LBB210_5: # %atomicrmw.start
16265 ; RV32IA-NEXT: # in Loop: Header=BB210_1 Depth=1
16266 ; RV32IA-NEXT: mv a3, a1
16267 ; RV32IA-NEXT: bnez a0, .LBB210_7
16268 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
16269 ; RV32IA-NEXT: # in Loop: Header=BB210_1 Depth=1
1627016160 ; RV32IA-NEXT: mv a3, s0
16271 ; RV32IA-NEXT: .LBB210_7: # %atomicrmw.start
16161 ; RV32IA-NEXT: .LBB210_6: # %atomicrmw.start
1627216162 ; RV32IA-NEXT: # in Loop: Header=BB210_1 Depth=1
1627316163 ; RV32IA-NEXT: sw a1, 4(sp)
1627416164 ; RV32IA-NEXT: mv a0, s1
1627916169 ; RV32IA-NEXT: lw a1, 4(sp)
1628016170 ; RV32IA-NEXT: lw a2, 0(sp)
1628116171 ; RV32IA-NEXT: beqz a0, .LBB210_1
16282 ; RV32IA-NEXT: # %bb.8: # %atomicrmw.end
16172 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1628316173 ; RV32IA-NEXT: mv a0, a2
1628416174 ; RV32IA-NEXT: lw s3, 12(sp)
1628516175 ; RV32IA-NEXT: lw s2, 16(sp)
1635416244 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
1635516245 ; RV32I-NEXT: # in Loop: Header=BB211_1 Depth=1
1635616246 ; RV32I-NEXT: sltu a0, s0, a1
16357 ; RV32I-NEXT: sw a2, 0(sp)
16358 ; RV32I-NEXT: beqz a0, .LBB211_4
16359 ; RV32I-NEXT: j .LBB211_5
16247 ; RV32I-NEXT: j .LBB211_4
1636016248 ; RV32I-NEXT: .LBB211_3: # in Loop: Header=BB211_1 Depth=1
1636116249 ; RV32I-NEXT: sltu a0, s2, a2
16362 ; RV32I-NEXT: sw a2, 0(sp)
16363 ; RV32I-NEXT: bnez a0, .LBB211_5
1636416250 ; RV32I-NEXT: .LBB211_4: # %atomicrmw.start
1636516251 ; RV32I-NEXT: # in Loop: Header=BB211_1 Depth=1
16252 ; RV32I-NEXT: sw a2, 0(sp)
16253 ; RV32I-NEXT: mv a3, a1
16254 ; RV32I-NEXT: bnez a0, .LBB211_6
16255 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
16256 ; RV32I-NEXT: # in Loop: Header=BB211_1 Depth=1
1636616257 ; RV32I-NEXT: mv a2, s2
16367 ; RV32I-NEXT: .LBB211_5: # %atomicrmw.start
16368 ; RV32I-NEXT: # in Loop: Header=BB211_1 Depth=1
16369 ; RV32I-NEXT: mv a3, a1
16370 ; RV32I-NEXT: bnez a0, .LBB211_7
16371 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
16372 ; RV32I-NEXT: # in Loop: Header=BB211_1 Depth=1
1637316258 ; RV32I-NEXT: mv a3, s0
16374 ; RV32I-NEXT: .LBB211_7: # %atomicrmw.start
16259 ; RV32I-NEXT: .LBB211_6: # %atomicrmw.start
1637516260 ; RV32I-NEXT: # in Loop: Header=BB211_1 Depth=1
1637616261 ; RV32I-NEXT: sw a1, 4(sp)
1637716262 ; RV32I-NEXT: mv a0, s1
1638216267 ; RV32I-NEXT: lw a1, 4(sp)
1638316268 ; RV32I-NEXT: lw a2, 0(sp)
1638416269 ; RV32I-NEXT: beqz a0, .LBB211_1
16385 ; RV32I-NEXT: # %bb.8: # %atomicrmw.end
16270 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1638616271 ; RV32I-NEXT: mv a0, a2
1638716272 ; RV32I-NEXT: lw s3, 12(sp)
1638816273 ; RV32I-NEXT: lw s2, 16(sp)
1641216297 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
1641316298 ; RV32IA-NEXT: # in Loop: Header=BB211_1 Depth=1
1641416299 ; RV32IA-NEXT: sltu a0, s0, a1
16415 ; RV32IA-NEXT: sw a2, 0(sp)
16416 ; RV32IA-NEXT: beqz a0, .LBB211_4
16417 ; RV32IA-NEXT: j .LBB211_5
16300 ; RV32IA-NEXT: j .LBB211_4
1641816301 ; RV32IA-NEXT: .LBB211_3: # in Loop: Header=BB211_1 Depth=1
1641916302 ; RV32IA-NEXT: sltu a0, s2, a2
16420 ; RV32IA-NEXT: sw a2, 0(sp)
16421 ; RV32IA-NEXT: bnez a0, .LBB211_5
1642216303 ; RV32IA-NEXT: .LBB211_4: # %atomicrmw.start
1642316304 ; RV32IA-NEXT: # in Loop: Header=BB211_1 Depth=1
16305 ; RV32IA-NEXT: sw a2, 0(sp)
16306 ; RV32IA-NEXT: mv a3, a1
16307 ; RV32IA-NEXT: bnez a0, .LBB211_6
16308 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
16309 ; RV32IA-NEXT: # in Loop: Header=BB211_1 Depth=1
1642416310 ; RV32IA-NEXT: mv a2, s2
16425 ; RV32IA-NEXT: .LBB211_5: # %atomicrmw.start
16426 ; RV32IA-NEXT: # in Loop: Header=BB211_1 Depth=1
16427 ; RV32IA-NEXT: mv a3, a1
16428 ; RV32IA-NEXT: bnez a0, .LBB211_7
16429 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
16430 ; RV32IA-NEXT: # in Loop: Header=BB211_1 Depth=1
1643116311 ; RV32IA-NEXT: mv a3, s0
16432 ; RV32IA-NEXT: .LBB211_7: # %atomicrmw.start
16312 ; RV32IA-NEXT: .LBB211_6: # %atomicrmw.start
1643316313 ; RV32IA-NEXT: # in Loop: Header=BB211_1 Depth=1
1643416314 ; RV32IA-NEXT: sw a1, 4(sp)
1643516315 ; RV32IA-NEXT: mv a0, s1
1644016320 ; RV32IA-NEXT: lw a1, 4(sp)
1644116321 ; RV32IA-NEXT: lw a2, 0(sp)
1644216322 ; RV32IA-NEXT: beqz a0, .LBB211_1
16443 ; RV32IA-NEXT: # %bb.8: # %atomicrmw.end
16323 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1644416324 ; RV32IA-NEXT: mv a0, a2
1644516325 ; RV32IA-NEXT: lw s3, 12(sp)
1644616326 ; RV32IA-NEXT: lw s2, 16(sp)
1651516395 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
1651616396 ; RV32I-NEXT: # in Loop: Header=BB212_1 Depth=1
1651716397 ; RV32I-NEXT: sltu a0, s0, a1
16518 ; RV32I-NEXT: sw a2, 0(sp)
16519 ; RV32I-NEXT: beqz a0, .LBB212_4
16520 ; RV32I-NEXT: j .LBB212_5
16398 ; RV32I-NEXT: j .LBB212_4
1652116399 ; RV32I-NEXT: .LBB212_3: # in Loop: Header=BB212_1 Depth=1
1652216400 ; RV32I-NEXT: sltu a0, s2, a2
16523 ; RV32I-NEXT: sw a2, 0(sp)
16524 ; RV32I-NEXT: bnez a0, .LBB212_5
1652516401 ; RV32I-NEXT: .LBB212_4: # %atomicrmw.start
1652616402 ; RV32I-NEXT: # in Loop: Header=BB212_1 Depth=1
16403 ; RV32I-NEXT: sw a2, 0(sp)
16404 ; RV32I-NEXT: mv a3, a1
16405 ; RV32I-NEXT: bnez a0, .LBB212_6
16406 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
16407 ; RV32I-NEXT: # in Loop: Header=BB212_1 Depth=1
1652716408 ; RV32I-NEXT: mv a2, s2
16528 ; RV32I-NEXT: .LBB212_5: # %atomicrmw.start
16529 ; RV32I-NEXT: # in Loop: Header=BB212_1 Depth=1
16530 ; RV32I-NEXT: mv a3, a1
16531 ; RV32I-NEXT: bnez a0, .LBB212_7
16532 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
16533 ; RV32I-NEXT: # in Loop: Header=BB212_1 Depth=1
1653416409 ; RV32I-NEXT: mv a3, s0
16535 ; RV32I-NEXT: .LBB212_7: # %atomicrmw.start
16410 ; RV32I-NEXT: .LBB212_6: # %atomicrmw.start
1653616411 ; RV32I-NEXT: # in Loop: Header=BB212_1 Depth=1
1653716412 ; RV32I-NEXT: sw a1, 4(sp)
1653816413 ; RV32I-NEXT: mv a0, s1
1654316418 ; RV32I-NEXT: lw a1, 4(sp)
1654416419 ; RV32I-NEXT: lw a2, 0(sp)
1654516420 ; RV32I-NEXT: beqz a0, .LBB212_1
16546 ; RV32I-NEXT: # %bb.8: # %atomicrmw.end
16421 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1654716422 ; RV32I-NEXT: mv a0, a2
1654816423 ; RV32I-NEXT: lw s3, 12(sp)
1654916424 ; RV32I-NEXT: lw s2, 16(sp)
1657316448 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
1657416449 ; RV32IA-NEXT: # in Loop: Header=BB212_1 Depth=1
1657516450 ; RV32IA-NEXT: sltu a0, s0, a1
16576 ; RV32IA-NEXT: sw a2, 0(sp)
16577 ; RV32IA-NEXT: beqz a0, .LBB212_4
16578 ; RV32IA-NEXT: j .LBB212_5
16451 ; RV32IA-NEXT: j .LBB212_4
1657916452 ; RV32IA-NEXT: .LBB212_3: # in Loop: Header=BB212_1 Depth=1
1658016453 ; RV32IA-NEXT: sltu a0, s2, a2
16581 ; RV32IA-NEXT: sw a2, 0(sp)
16582 ; RV32IA-NEXT: bnez a0, .LBB212_5
1658316454 ; RV32IA-NEXT: .LBB212_4: # %atomicrmw.start
1658416455 ; RV32IA-NEXT: # in Loop: Header=BB212_1 Depth=1
16456 ; RV32IA-NEXT: sw a2, 0(sp)
16457 ; RV32IA-NEXT: mv a3, a1
16458 ; RV32IA-NEXT: bnez a0, .LBB212_6
16459 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
16460 ; RV32IA-NEXT: # in Loop: Header=BB212_1 Depth=1
1658516461 ; RV32IA-NEXT: mv a2, s2
16586 ; RV32IA-NEXT: .LBB212_5: # %atomicrmw.start
16587 ; RV32IA-NEXT: # in Loop: Header=BB212_1 Depth=1
16588 ; RV32IA-NEXT: mv a3, a1
16589 ; RV32IA-NEXT: bnez a0, .LBB212_7
16590 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
16591 ; RV32IA-NEXT: # in Loop: Header=BB212_1 Depth=1
1659216462 ; RV32IA-NEXT: mv a3, s0
16593 ; RV32IA-NEXT: .LBB212_7: # %atomicrmw.start
16463 ; RV32IA-NEXT: .LBB212_6: # %atomicrmw.start
1659416464 ; RV32IA-NEXT: # in Loop: Header=BB212_1 Depth=1
1659516465 ; RV32IA-NEXT: sw a1, 4(sp)
1659616466 ; RV32IA-NEXT: mv a0, s1
1660116471 ; RV32IA-NEXT: lw a1, 4(sp)
1660216472 ; RV32IA-NEXT: lw a2, 0(sp)
1660316473 ; RV32IA-NEXT: beqz a0, .LBB212_1
16604 ; RV32IA-NEXT: # %bb.8: # %atomicrmw.end
16474 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1660516475 ; RV32IA-NEXT: mv a0, a2
1660616476 ; RV32IA-NEXT: lw s3, 12(sp)
1660716477 ; RV32IA-NEXT: lw s2, 16(sp)
1667616546 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
1667716547 ; RV32I-NEXT: # in Loop: Header=BB213_1 Depth=1
1667816548 ; RV32I-NEXT: sltu a0, s0, a1
16679 ; RV32I-NEXT: sw a2, 0(sp)
16680 ; RV32I-NEXT: beqz a0, .LBB213_4
16681 ; RV32I-NEXT: j .LBB213_5
16549 ; RV32I-NEXT: j .LBB213_4
1668216550 ; RV32I-NEXT: .LBB213_3: # in Loop: Header=BB213_1 Depth=1
1668316551 ; RV32I-NEXT: sltu a0, s2, a2
16684 ; RV32I-NEXT: sw a2, 0(sp)
16685 ; RV32I-NEXT: bnez a0, .LBB213_5
1668616552 ; RV32I-NEXT: .LBB213_4: # %atomicrmw.start
1668716553 ; RV32I-NEXT: # in Loop: Header=BB213_1 Depth=1
16554 ; RV32I-NEXT: sw a2, 0(sp)
16555 ; RV32I-NEXT: mv a3, a1
16556 ; RV32I-NEXT: bnez a0, .LBB213_6
16557 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
16558 ; RV32I-NEXT: # in Loop: Header=BB213_1 Depth=1
1668816559 ; RV32I-NEXT: mv a2, s2
16689 ; RV32I-NEXT: .LBB213_5: # %atomicrmw.start
16690 ; RV32I-NEXT: # in Loop: Header=BB213_1 Depth=1
16691 ; RV32I-NEXT: mv a3, a1
16692 ; RV32I-NEXT: bnez a0, .LBB213_7
16693 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
16694 ; RV32I-NEXT: # in Loop: Header=BB213_1 Depth=1
1669516560 ; RV32I-NEXT: mv a3, s0
16696 ; RV32I-NEXT: .LBB213_7: # %atomicrmw.start
16561 ; RV32I-NEXT: .LBB213_6: # %atomicrmw.start
1669716562 ; RV32I-NEXT: # in Loop: Header=BB213_1 Depth=1
1669816563 ; RV32I-NEXT: sw a1, 4(sp)
1669916564 ; RV32I-NEXT: mv a0, s1
1670416569 ; RV32I-NEXT: lw a1, 4(sp)
1670516570 ; RV32I-NEXT: lw a2, 0(sp)
1670616571 ; RV32I-NEXT: beqz a0, .LBB213_1
16707 ; RV32I-NEXT: # %bb.8: # %atomicrmw.end
16572 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1670816573 ; RV32I-NEXT: mv a0, a2
1670916574 ; RV32I-NEXT: lw s3, 12(sp)
1671016575 ; RV32I-NEXT: lw s2, 16(sp)
1673416599 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
1673516600 ; RV32IA-NEXT: # in Loop: Header=BB213_1 Depth=1
1673616601 ; RV32IA-NEXT: sltu a0, s0, a1
16737 ; RV32IA-NEXT: sw a2, 0(sp)
16738 ; RV32IA-NEXT: beqz a0, .LBB213_4
16739 ; RV32IA-NEXT: j .LBB213_5
16602 ; RV32IA-NEXT: j .LBB213_4
1674016603 ; RV32IA-NEXT: .LBB213_3: # in Loop: Header=BB213_1 Depth=1
1674116604 ; RV32IA-NEXT: sltu a0, s2, a2
16742 ; RV32IA-NEXT: sw a2, 0(sp)
16743 ; RV32IA-NEXT: bnez a0, .LBB213_5
1674416605 ; RV32IA-NEXT: .LBB213_4: # %atomicrmw.start
1674516606 ; RV32IA-NEXT: # in Loop: Header=BB213_1 Depth=1
16607 ; RV32IA-NEXT: sw a2, 0(sp)
16608 ; RV32IA-NEXT: mv a3, a1
16609 ; RV32IA-NEXT: bnez a0, .LBB213_6
16610 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
16611 ; RV32IA-NEXT: # in Loop: Header=BB213_1 Depth=1
1674616612 ; RV32IA-NEXT: mv a2, s2
16747 ; RV32IA-NEXT: .LBB213_5: # %atomicrmw.start
16748 ; RV32IA-NEXT: # in Loop: Header=BB213_1 Depth=1
16749 ; RV32IA-NEXT: mv a3, a1
16750 ; RV32IA-NEXT: bnez a0, .LBB213_7
16751 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
16752 ; RV32IA-NEXT: # in Loop: Header=BB213_1 Depth=1
1675316613 ; RV32IA-NEXT: mv a3, s0
16754 ; RV32IA-NEXT: .LBB213_7: # %atomicrmw.start
16614 ; RV32IA-NEXT: .LBB213_6: # %atomicrmw.start
1675516615 ; RV32IA-NEXT: # in Loop: Header=BB213_1 Depth=1
1675616616 ; RV32IA-NEXT: sw a1, 4(sp)
1675716617 ; RV32IA-NEXT: mv a0, s1
1676216622 ; RV32IA-NEXT: lw a1, 4(sp)
1676316623 ; RV32IA-NEXT: lw a2, 0(sp)
1676416624 ; RV32IA-NEXT: beqz a0, .LBB213_1
16765 ; RV32IA-NEXT: # %bb.8: # %atomicrmw.end
16625 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1676616626 ; RV32IA-NEXT: mv a0, a2
1676716627 ; RV32IA-NEXT: lw s3, 12(sp)
1676816628 ; RV32IA-NEXT: lw s2, 16(sp)
1683716697 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start
1683816698 ; RV32I-NEXT: # in Loop: Header=BB214_1 Depth=1
1683916699 ; RV32I-NEXT: sltu a0, s0, a1
16840 ; RV32I-NEXT: sw a2, 0(sp)
16841 ; RV32I-NEXT: beqz a0, .LBB214_4
16842 ; RV32I-NEXT: j .LBB214_5
16700 ; RV32I-NEXT: j .LBB214_4
1684316701 ; RV32I-NEXT: .LBB214_3: # in Loop: Header=BB214_1 Depth=1
1684416702 ; RV32I-NEXT: sltu a0, s2, a2
16845 ; RV32I-NEXT: sw a2, 0(sp)
16846 ; RV32I-NEXT: bnez a0, .LBB214_5
1684716703 ; RV32I-NEXT: .LBB214_4: # %atomicrmw.start
1684816704 ; RV32I-NEXT: # in Loop: Header=BB214_1 Depth=1
16705 ; RV32I-NEXT: sw a2, 0(sp)
16706 ; RV32I-NEXT: mv a3, a1
16707 ; RV32I-NEXT: bnez a0, .LBB214_6
16708 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
16709 ; RV32I-NEXT: # in Loop: Header=BB214_1 Depth=1
1684916710 ; RV32I-NEXT: mv a2, s2
16850 ; RV32I-NEXT: .LBB214_5: # %atomicrmw.start
16851 ; RV32I-NEXT: # in Loop: Header=BB214_1 Depth=1
16852 ; RV32I-NEXT: mv a3, a1
16853 ; RV32I-NEXT: bnez a0, .LBB214_7
16854 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
16855 ; RV32I-NEXT: # in Loop: Header=BB214_1 Depth=1
1685616711 ; RV32I-NEXT: mv a3, s0
16857 ; RV32I-NEXT: .LBB214_7: # %atomicrmw.start
16712 ; RV32I-NEXT: .LBB214_6: # %atomicrmw.start
1685816713 ; RV32I-NEXT: # in Loop: Header=BB214_1 Depth=1
1685916714 ; RV32I-NEXT: sw a1, 4(sp)
1686016715 ; RV32I-NEXT: mv a0, s1
1686516720 ; RV32I-NEXT: lw a1, 4(sp)
1686616721 ; RV32I-NEXT: lw a2, 0(sp)
1686716722 ; RV32I-NEXT: beqz a0, .LBB214_1
16868 ; RV32I-NEXT: # %bb.8: # %atomicrmw.end
16723 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1686916724 ; RV32I-NEXT: mv a0, a2
1687016725 ; RV32I-NEXT: lw s3, 12(sp)
1687116726 ; RV32I-NEXT: lw s2, 16(sp)
1689516750 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start
1689616751 ; RV32IA-NEXT: # in Loop: Header=BB214_1 Depth=1
1689716752 ; RV32IA-NEXT: sltu a0, s0, a1
16898 ; RV32IA-NEXT: sw a2, 0(sp)
16899 ; RV32IA-NEXT: beqz a0, .LBB214_4
16900 ; RV32IA-NEXT: j .LBB214_5
16753 ; RV32IA-NEXT: j .LBB214_4
1690116754 ; RV32IA-NEXT: .LBB214_3: # in Loop: Header=BB214_1 Depth=1
1690216755 ; RV32IA-NEXT: sltu a0, s2, a2
16903 ; RV32IA-NEXT: sw a2, 0(sp)
16904 ; RV32IA-NEXT: bnez a0, .LBB214_5
1690516756 ; RV32IA-NEXT: .LBB214_4: # %atomicrmw.start
1690616757 ; RV32IA-NEXT: # in Loop: Header=BB214_1 Depth=1
16758 ; RV32IA-NEXT: sw a2, 0(sp)
16759 ; RV32IA-NEXT: mv a3, a1
16760 ; RV32IA-NEXT: bnez a0, .LBB214_6
16761 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
16762 ; RV32IA-NEXT: # in Loop: Header=BB214_1 Depth=1
1690716763 ; RV32IA-NEXT: mv a2, s2
16908 ; RV32IA-NEXT: .LBB214_5: # %atomicrmw.start
16909 ; RV32IA-NEXT: # in Loop: Header=BB214_1 Depth=1
16910 ; RV32IA-NEXT: mv a3, a1
16911 ; RV32IA-NEXT: bnez a0, .LBB214_7
16912 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
16913 ; RV32IA-NEXT: # in Loop: Header=BB214_1 Depth=1
1691416764 ; RV32IA-NEXT: mv a3, s0
16915 ; RV32IA-NEXT: .LBB214_7: # %atomicrmw.start
16765 ; RV32IA-NEXT: .LBB214_6: # %atomicrmw.start
1691616766 ; RV32IA-NEXT: # in Loop: Header=BB214_1 Depth=1
1691716767 ; RV32IA-NEXT: sw a1, 4(sp)
1691816768 ; RV32IA-NEXT: mv a0, s1
1692316773 ; RV32IA-NEXT: lw a1, 4(sp)
1692416774 ; RV32IA-NEXT: lw a2, 0(sp)
1692516775 ; RV32IA-NEXT: beqz a0, .LBB214_1
16926 ; RV32IA-NEXT: # %bb.8: # %atomicrmw.end
16776 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1692716777 ; RV32IA-NEXT: mv a0, a2
1692816778 ; RV32IA-NEXT: lw s3, 12(sp)
1692916779 ; RV32IA-NEXT: lw s2, 16(sp)
1700516855 ; RV32I-NEXT: # in Loop: Header=BB215_1 Depth=1
1700616856 ; RV32I-NEXT: xori a0, a0, 1
1700716857 ; RV32I-NEXT: sw a2, 0(sp)
16858 ; RV32I-NEXT: mv a3, a1
1700816859 ; RV32I-NEXT: bnez a0, .LBB215_6
1700916860 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
1701016861 ; RV32I-NEXT: # in Loop: Header=BB215_1 Depth=1
1701116862 ; RV32I-NEXT: mv a2, s2
16863 ; RV32I-NEXT: mv a3, s0
1701216864 ; RV32I-NEXT: .LBB215_6: # %atomicrmw.start
17013 ; RV32I-NEXT: # in Loop: Header=BB215_1 Depth=1
17014 ; RV32I-NEXT: mv a3, a1
17015 ; RV32I-NEXT: bnez a0, .LBB215_8
17016 ; RV32I-NEXT: # %bb.7: # %atomicrmw.start
17017 ; RV32I-NEXT: # in Loop: Header=BB215_1 Depth=1
17018 ; RV32I-NEXT: mv a3, s0
17019 ; RV32I-NEXT: .LBB215_8: # %atomicrmw.start
1702016865 ; RV32I-NEXT: # in Loop: Header=BB215_1 Depth=1
1702116866 ; RV32I-NEXT: sw a1, 4(sp)
1702216867 ; RV32I-NEXT: mv a0, s1
1702716872 ; RV32I-NEXT: lw a1, 4(sp)
1702816873 ; RV32I-NEXT: lw a2, 0(sp)
1702916874 ; RV32I-NEXT: beqz a0, .LBB215_1
17030 ; RV32I-NEXT: # %bb.9: # %atomicrmw.end
16875 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1703116876 ; RV32I-NEXT: mv a0, a2
1703216877 ; RV32I-NEXT: lw s3, 12(sp)
1703316878 ; RV32I-NEXT: lw s2, 16(sp)
1706416909 ; RV32IA-NEXT: # in Loop: Header=BB215_1 Depth=1
1706516910 ; RV32IA-NEXT: xori a0, a0, 1
1706616911 ; RV32IA-NEXT: sw a2, 0(sp)
16912 ; RV32IA-NEXT: mv a3, a1
1706716913 ; RV32IA-NEXT: bnez a0, .LBB215_6
1706816914 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
1706916915 ; RV32IA-NEXT: # in Loop: Header=BB215_1 Depth=1
1707016916 ; RV32IA-NEXT: mv a2, s2
16917 ; RV32IA-NEXT: mv a3, s0
1707116918 ; RV32IA-NEXT: .LBB215_6: # %atomicrmw.start
17072 ; RV32IA-NEXT: # in Loop: Header=BB215_1 Depth=1
17073 ; RV32IA-NEXT: mv a3, a1
17074 ; RV32IA-NEXT: bnez a0, .LBB215_8
17075 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.start
17076 ; RV32IA-NEXT: # in Loop: Header=BB215_1 Depth=1
17077 ; RV32IA-NEXT: mv a3, s0
17078 ; RV32IA-NEXT: .LBB215_8: # %atomicrmw.start
1707916919 ; RV32IA-NEXT: # in Loop: Header=BB215_1 Depth=1
1708016920 ; RV32IA-NEXT: sw a1, 4(sp)
1708116921 ; RV32IA-NEXT: mv a0, s1
1708616926 ; RV32IA-NEXT: lw a1, 4(sp)
1708716927 ; RV32IA-NEXT: lw a2, 0(sp)
1708816928 ; RV32IA-NEXT: beqz a0, .LBB215_1
17089 ; RV32IA-NEXT: # %bb.9: # %atomicrmw.end
16929 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1709016930 ; RV32IA-NEXT: mv a0, a2
1709116931 ; RV32IA-NEXT: lw s3, 12(sp)
1709216932 ; RV32IA-NEXT: lw s2, 16(sp)
1716817008 ; RV32I-NEXT: # in Loop: Header=BB216_1 Depth=1
1716917009 ; RV32I-NEXT: xori a0, a0, 1
1717017010 ; RV32I-NEXT: sw a2, 0(sp)
17011 ; RV32I-NEXT: mv a3, a1
1717117012 ; RV32I-NEXT: bnez a0, .LBB216_6
1717217013 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
1717317014 ; RV32I-NEXT: # in Loop: Header=BB216_1 Depth=1
1717417015 ; RV32I-NEXT: mv a2, s2
17016 ; RV32I-NEXT: mv a3, s0
1717517017 ; RV32I-NEXT: .LBB216_6: # %atomicrmw.start
17176 ; RV32I-NEXT: # in Loop: Header=BB216_1 Depth=1
17177 ; RV32I-NEXT: mv a3, a1
17178 ; RV32I-NEXT: bnez a0, .LBB216_8
17179 ; RV32I-NEXT: # %bb.7: # %atomicrmw.start
17180 ; RV32I-NEXT: # in Loop: Header=BB216_1 Depth=1
17181 ; RV32I-NEXT: mv a3, s0
17182 ; RV32I-NEXT: .LBB216_8: # %atomicrmw.start
1718317018 ; RV32I-NEXT: # in Loop: Header=BB216_1 Depth=1
1718417019 ; RV32I-NEXT: sw a1, 4(sp)
1718517020 ; RV32I-NEXT: mv a0, s1
1719017025 ; RV32I-NEXT: lw a1, 4(sp)
1719117026 ; RV32I-NEXT: lw a2, 0(sp)
1719217027 ; RV32I-NEXT: beqz a0, .LBB216_1
17193 ; RV32I-NEXT: # %bb.9: # %atomicrmw.end
17028 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1719417029 ; RV32I-NEXT: mv a0, a2
1719517030 ; RV32I-NEXT: lw s3, 12(sp)
1719617031 ; RV32I-NEXT: lw s2, 16(sp)
1722717062 ; RV32IA-NEXT: # in Loop: Header=BB216_1 Depth=1
1722817063 ; RV32IA-NEXT: xori a0, a0, 1
1722917064 ; RV32IA-NEXT: sw a2, 0(sp)
17065 ; RV32IA-NEXT: mv a3, a1
1723017066 ; RV32IA-NEXT: bnez a0, .LBB216_6
1723117067 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
1723217068 ; RV32IA-NEXT: # in Loop: Header=BB216_1 Depth=1
1723317069 ; RV32IA-NEXT: mv a2, s2
17070 ; RV32IA-NEXT: mv a3, s0
1723417071 ; RV32IA-NEXT: .LBB216_6: # %atomicrmw.start
17235 ; RV32IA-NEXT: # in Loop: Header=BB216_1 Depth=1
17236 ; RV32IA-NEXT: mv a3, a1
17237 ; RV32IA-NEXT: bnez a0, .LBB216_8
17238 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.start
17239 ; RV32IA-NEXT: # in Loop: Header=BB216_1 Depth=1
17240 ; RV32IA-NEXT: mv a3, s0
17241 ; RV32IA-NEXT: .LBB216_8: # %atomicrmw.start
1724217072 ; RV32IA-NEXT: # in Loop: Header=BB216_1 Depth=1
1724317073 ; RV32IA-NEXT: sw a1, 4(sp)
1724417074 ; RV32IA-NEXT: mv a0, s1
1724917079 ; RV32IA-NEXT: lw a1, 4(sp)
1725017080 ; RV32IA-NEXT: lw a2, 0(sp)
1725117081 ; RV32IA-NEXT: beqz a0, .LBB216_1
17252 ; RV32IA-NEXT: # %bb.9: # %atomicrmw.end
17082 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1725317083 ; RV32IA-NEXT: mv a0, a2
1725417084 ; RV32IA-NEXT: lw s3, 12(sp)
1725517085 ; RV32IA-NEXT: lw s2, 16(sp)
1733117161 ; RV32I-NEXT: # in Loop: Header=BB217_1 Depth=1
1733217162 ; RV32I-NEXT: xori a0, a0, 1
1733317163 ; RV32I-NEXT: sw a2, 0(sp)
17164 ; RV32I-NEXT: mv a3, a1
1733417165 ; RV32I-NEXT: bnez a0, .LBB217_6
1733517166 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
1733617167 ; RV32I-NEXT: # in Loop: Header=BB217_1 Depth=1
1733717168 ; RV32I-NEXT: mv a2, s2
17169 ; RV32I-NEXT: mv a3, s0
1733817170 ; RV32I-NEXT: .LBB217_6: # %atomicrmw.start
17339 ; RV32I-NEXT: # in Loop: Header=BB217_1 Depth=1
17340 ; RV32I-NEXT: mv a3, a1
17341 ; RV32I-NEXT: bnez a0, .LBB217_8
17342 ; RV32I-NEXT: # %bb.7: # %atomicrmw.start
17343 ; RV32I-NEXT: # in Loop: Header=BB217_1 Depth=1
17344 ; RV32I-NEXT: mv a3, s0
17345 ; RV32I-NEXT: .LBB217_8: # %atomicrmw.start
1734617171 ; RV32I-NEXT: # in Loop: Header=BB217_1 Depth=1
1734717172 ; RV32I-NEXT: sw a1, 4(sp)
1734817173 ; RV32I-NEXT: mv a0, s1
1735317178 ; RV32I-NEXT: lw a1, 4(sp)
1735417179 ; RV32I-NEXT: lw a2, 0(sp)
1735517180 ; RV32I-NEXT: beqz a0, .LBB217_1
17356 ; RV32I-NEXT: # %bb.9: # %atomicrmw.end
17181 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1735717182 ; RV32I-NEXT: mv a0, a2
1735817183 ; RV32I-NEXT: lw s3, 12(sp)
1735917184 ; RV32I-NEXT: lw s2, 16(sp)
1739017215 ; RV32IA-NEXT: # in Loop: Header=BB217_1 Depth=1
1739117216 ; RV32IA-NEXT: xori a0, a0, 1
1739217217 ; RV32IA-NEXT: sw a2, 0(sp)
17218 ; RV32IA-NEXT: mv a3, a1
1739317219 ; RV32IA-NEXT: bnez a0, .LBB217_6
1739417220 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
1739517221 ; RV32IA-NEXT: # in Loop: Header=BB217_1 Depth=1
1739617222 ; RV32IA-NEXT: mv a2, s2
17223 ; RV32IA-NEXT: mv a3, s0
1739717224 ; RV32IA-NEXT: .LBB217_6: # %atomicrmw.start
17398 ; RV32IA-NEXT: # in Loop: Header=BB217_1 Depth=1
17399 ; RV32IA-NEXT: mv a3, a1
17400 ; RV32IA-NEXT: bnez a0, .LBB217_8
17401 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.start
17402 ; RV32IA-NEXT: # in Loop: Header=BB217_1 Depth=1
17403 ; RV32IA-NEXT: mv a3, s0
17404 ; RV32IA-NEXT: .LBB217_8: # %atomicrmw.start
1740517225 ; RV32IA-NEXT: # in Loop: Header=BB217_1 Depth=1
1740617226 ; RV32IA-NEXT: sw a1, 4(sp)
1740717227 ; RV32IA-NEXT: mv a0, s1
1741217232 ; RV32IA-NEXT: lw a1, 4(sp)
1741317233 ; RV32IA-NEXT: lw a2, 0(sp)
1741417234 ; RV32IA-NEXT: beqz a0, .LBB217_1
17415 ; RV32IA-NEXT: # %bb.9: # %atomicrmw.end
17235 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1741617236 ; RV32IA-NEXT: mv a0, a2
1741717237 ; RV32IA-NEXT: lw s3, 12(sp)
1741817238 ; RV32IA-NEXT: lw s2, 16(sp)
1749417314 ; RV32I-NEXT: # in Loop: Header=BB218_1 Depth=1
1749517315 ; RV32I-NEXT: xori a0, a0, 1
1749617316 ; RV32I-NEXT: sw a2, 0(sp)
17317 ; RV32I-NEXT: mv a3, a1
1749717318 ; RV32I-NEXT: bnez a0, .LBB218_6
1749817319 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
1749917320 ; RV32I-NEXT: # in Loop: Header=BB218_1 Depth=1
1750017321 ; RV32I-NEXT: mv a2, s2
17322 ; RV32I-NEXT: mv a3, s0
1750117323 ; RV32I-NEXT: .LBB218_6: # %atomicrmw.start
17502 ; RV32I-NEXT: # in Loop: Header=BB218_1 Depth=1
17503 ; RV32I-NEXT: mv a3, a1
17504 ; RV32I-NEXT: bnez a0, .LBB218_8
17505 ; RV32I-NEXT: # %bb.7: # %atomicrmw.start
17506 ; RV32I-NEXT: # in Loop: Header=BB218_1 Depth=1
17507 ; RV32I-NEXT: mv a3, s0
17508 ; RV32I-NEXT: .LBB218_8: # %atomicrmw.start
1750917324 ; RV32I-NEXT: # in Loop: Header=BB218_1 Depth=1
1751017325 ; RV32I-NEXT: sw a1, 4(sp)
1751117326 ; RV32I-NEXT: mv a0, s1
1751617331 ; RV32I-NEXT: lw a1, 4(sp)
1751717332 ; RV32I-NEXT: lw a2, 0(sp)
1751817333 ; RV32I-NEXT: beqz a0, .LBB218_1
17519 ; RV32I-NEXT: # %bb.9: # %atomicrmw.end
17334 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1752017335 ; RV32I-NEXT: mv a0, a2
1752117336 ; RV32I-NEXT: lw s3, 12(sp)
1752217337 ; RV32I-NEXT: lw s2, 16(sp)
1755317368 ; RV32IA-NEXT: # in Loop: Header=BB218_1 Depth=1
1755417369 ; RV32IA-NEXT: xori a0, a0, 1
1755517370 ; RV32IA-NEXT: sw a2, 0(sp)
17371 ; RV32IA-NEXT: mv a3, a1
1755617372 ; RV32IA-NEXT: bnez a0, .LBB218_6
1755717373 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
1755817374 ; RV32IA-NEXT: # in Loop: Header=BB218_1 Depth=1
1755917375 ; RV32IA-NEXT: mv a2, s2
17376 ; RV32IA-NEXT: mv a3, s0
1756017377 ; RV32IA-NEXT: .LBB218_6: # %atomicrmw.start
17561 ; RV32IA-NEXT: # in Loop: Header=BB218_1 Depth=1
17562 ; RV32IA-NEXT: mv a3, a1
17563 ; RV32IA-NEXT: bnez a0, .LBB218_8
17564 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.start
17565 ; RV32IA-NEXT: # in Loop: Header=BB218_1 Depth=1
17566 ; RV32IA-NEXT: mv a3, s0
17567 ; RV32IA-NEXT: .LBB218_8: # %atomicrmw.start
1756817378 ; RV32IA-NEXT: # in Loop: Header=BB218_1 Depth=1
1756917379 ; RV32IA-NEXT: sw a1, 4(sp)
1757017380 ; RV32IA-NEXT: mv a0, s1
1757517385 ; RV32IA-NEXT: lw a1, 4(sp)
1757617386 ; RV32IA-NEXT: lw a2, 0(sp)
1757717387 ; RV32IA-NEXT: beqz a0, .LBB218_1
17578 ; RV32IA-NEXT: # %bb.9: # %atomicrmw.end
17388 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1757917389 ; RV32IA-NEXT: mv a0, a2
1758017390 ; RV32IA-NEXT: lw s3, 12(sp)
1758117391 ; RV32IA-NEXT: lw s2, 16(sp)
1765717467 ; RV32I-NEXT: # in Loop: Header=BB219_1 Depth=1
1765817468 ; RV32I-NEXT: xori a0, a0, 1
1765917469 ; RV32I-NEXT: sw a2, 0(sp)
17470 ; RV32I-NEXT: mv a3, a1
1766017471 ; RV32I-NEXT: bnez a0, .LBB219_6
1766117472 ; RV32I-NEXT: # %bb.5: # %atomicrmw.start
1766217473 ; RV32I-NEXT: # in Loop: Header=BB219_1 Depth=1
1766317474 ; RV32I-NEXT: mv a2, s2
17475 ; RV32I-NEXT: mv a3, s0
1766417476 ; RV32I-NEXT: .LBB219_6: # %atomicrmw.start
17665 ; RV32I-NEXT: # in Loop: Header=BB219_1 Depth=1
17666 ; RV32I-NEXT: mv a3, a1
17667 ; RV32I-NEXT: bnez a0, .LBB219_8
17668 ; RV32I-NEXT: # %bb.7: # %atomicrmw.start
17669 ; RV32I-NEXT: # in Loop: Header=BB219_1 Depth=1
17670 ; RV32I-NEXT: mv a3, s0
17671 ; RV32I-NEXT: .LBB219_8: # %atomicrmw.start
1767217477 ; RV32I-NEXT: # in Loop: Header=BB219_1 Depth=1
1767317478 ; RV32I-NEXT: sw a1, 4(sp)
1767417479 ; RV32I-NEXT: mv a0, s1
1767917484 ; RV32I-NEXT: lw a1, 4(sp)
1768017485 ; RV32I-NEXT: lw a2, 0(sp)
1768117486 ; RV32I-NEXT: beqz a0, .LBB219_1
17682 ; RV32I-NEXT: # %bb.9: # %atomicrmw.end
17487 ; RV32I-NEXT: # %bb.7: # %atomicrmw.end
1768317488 ; RV32I-NEXT: mv a0, a2
1768417489 ; RV32I-NEXT: lw s3, 12(sp)
1768517490 ; RV32I-NEXT: lw s2, 16(sp)
1771617521 ; RV32IA-NEXT: # in Loop: Header=BB219_1 Depth=1
1771717522 ; RV32IA-NEXT: xori a0, a0, 1
1771817523 ; RV32IA-NEXT: sw a2, 0(sp)
17524 ; RV32IA-NEXT: mv a3, a1
1771917525 ; RV32IA-NEXT: bnez a0, .LBB219_6
1772017526 ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
1772117527 ; RV32IA-NEXT: # in Loop: Header=BB219_1 Depth=1
1772217528 ; RV32IA-NEXT: mv a2, s2
17529 ; RV32IA-NEXT: mv a3, s0
1772317530 ; RV32IA-NEXT: .LBB219_6: # %atomicrmw.start
17724 ; RV32IA-NEXT: # in Loop: Header=BB219_1 Depth=1
17725 ; RV32IA-NEXT: mv a3, a1
17726 ; RV32IA-NEXT: bnez a0, .LBB219_8
17727 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.start
17728 ; RV32IA-NEXT: # in Loop: Header=BB219_1 Depth=1
17729 ; RV32IA-NEXT: mv a3, s0
17730 ; RV32IA-NEXT: .LBB219_8: # %atomicrmw.start
1773117531 ; RV32IA-NEXT: # in Loop: Header=BB219_1 Depth=1
1773217532 ; RV32IA-NEXT: sw a1, 4(sp)
1773317533 ; RV32IA-NEXT: mv a0, s1
1773817538 ; RV32IA-NEXT: lw a1, 4(sp)
1773917539 ; RV32IA-NEXT: lw a2, 0(sp)
1774017540 ; RV32IA-NEXT: beqz a0, .LBB219_1
17741 ; RV32IA-NEXT: # %bb.9: # %atomicrmw.end
17541 ; RV32IA-NEXT: # %bb.7: # %atomicrmw.end
1774217542 ; RV32IA-NEXT: mv a0, a2
1774317543 ; RV32IA-NEXT: lw s3, 12(sp)
1774417544 ; RV32IA-NEXT: lw s2, 16(sp)
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
2 ; RUN: | FileCheck %s -check-prefix=RV32I
3 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
4 ; RUN: | FileCheck %s -check-prefix=RV64I
5
6 ; Selects of wide values are split into two selects, which can easily cause
7 ; unnecessary control flow. Here we check some cases where we can currently
8 ; emit a sequence of selects with shared control flow.
9
10 define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind {
11 ; RV32I-LABEL: cmovcc64:
12 ; RV32I: # %bb.0: # %entry
13 ; RV32I-NEXT: addi a5, zero, 123
14 ; RV32I-NEXT: beq a0, a5, .LBB0_2
15 ; RV32I-NEXT: # %bb.1: # %entry
16 ; RV32I-NEXT: mv a1, a3
17 ; RV32I-NEXT: mv a2, a4
18 ; RV32I-NEXT: .LBB0_2: # %entry
19 ; RV32I-NEXT: mv a0, a1
20 ; RV32I-NEXT: mv a1, a2
21 ; RV32I-NEXT: ret
22 ;
23 ; RV64I-LABEL: cmovcc64:
24 ; RV64I: # %bb.0: # %entry
25 ; RV64I-NEXT: addi a3, zero, 123
26 ; RV64I-NEXT: beq a0, a3, .LBB0_2
27 ; RV64I-NEXT: # %bb.1: # %entry
28 ; RV64I-NEXT: mv a1, a2
29 ; RV64I-NEXT: .LBB0_2: # %entry
30 ; RV64I-NEXT: mv a0, a1
31 ; RV64I-NEXT: ret
32 entry:
33 %cmp = icmp eq i32 %a, 123
34 %cond = select i1 %cmp, i64 %b, i64 %c
35 ret i64 %cond
36 }
37
38 define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
39 ; RV32I-LABEL: cmovcc128:
40 ; RV32I: # %bb.0: # %entry
41 ; RV32I-NEXT: xori a1, a1, 123
42 ; RV32I-NEXT: or a1, a1, a2
43 ; RV32I-NEXT: beqz a1, .LBB1_2
44 ; RV32I-NEXT: # %bb.1: # %entry
45 ; RV32I-NEXT: addi a1, a4, 4
46 ; RV32I-NEXT: addi a2, a4, 8
47 ; RV32I-NEXT: addi a5, a4, 12
48 ; RV32I-NEXT: mv a3, a4
49 ; RV32I-NEXT: j .LBB1_3
50 ; RV32I-NEXT: .LBB1_2:
51 ; RV32I-NEXT: addi a1, a3, 4
52 ; RV32I-NEXT: addi a2, a3, 8
53 ; RV32I-NEXT: addi a5, a3, 12
54 ; RV32I-NEXT: .LBB1_3: # %entry
55 ; RV32I-NEXT: lw a4, 0(a5)
56 ; RV32I-NEXT: sw a4, 12(a0)
57 ; RV32I-NEXT: lw a2, 0(a2)
58 ; RV32I-NEXT: sw a2, 8(a0)
59 ; RV32I-NEXT: lw a1, 0(a1)
60 ; RV32I-NEXT: sw a1, 4(a0)
61 ; RV32I-NEXT: lw a1, 0(a3)
62 ; RV32I-NEXT: sw a1, 0(a0)
63 ; RV32I-NEXT: ret
64 ;
65 ; RV64I-LABEL: cmovcc128:
66 ; RV64I: # %bb.0: # %entry
67 ; RV64I-NEXT: addi a5, zero, 123
68 ; RV64I-NEXT: beq a0, a5, .LBB1_2
69 ; RV64I-NEXT: # %bb.1: # %entry
70 ; RV64I-NEXT: mv a1, a3
71 ; RV64I-NEXT: mv a2, a4
72 ; RV64I-NEXT: .LBB1_2: # %entry
73 ; RV64I-NEXT: mv a0, a1
74 ; RV64I-NEXT: mv a1, a2
75 ; RV64I-NEXT: ret
76 entry:
77 %cmp = icmp eq i64 %a, 123
78 %cond = select i1 %cmp, i128 %b, i128 %c
79 ret i128 %cond
80 }
81
82 define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {
83 ; RV32I-LABEL: cmov64:
84 ; RV32I: # %bb.0: # %entry
85 ; RV32I-NEXT: andi a0, a0, 1
86 ; RV32I-NEXT: bnez a0, .LBB2_2
87 ; RV32I-NEXT: # %bb.1: # %entry
88 ; RV32I-NEXT: mv a1, a3
89 ; RV32I-NEXT: mv a2, a4
90 ; RV32I-NEXT: .LBB2_2: # %entry
91 ; RV32I-NEXT: mv a0, a1
92 ; RV32I-NEXT: mv a1, a2
93 ; RV32I-NEXT: ret
94 ;
95 ; RV64I-LABEL: cmov64:
96 ; RV64I: # %bb.0: # %entry
97 ; RV64I-NEXT: andi a0, a0, 1
98 ; RV64I-NEXT: bnez a0, .LBB2_2
99 ; RV64I-NEXT: # %bb.1: # %entry
100 ; RV64I-NEXT: mv a1, a2
101 ; RV64I-NEXT: .LBB2_2: # %entry
102 ; RV64I-NEXT: mv a0, a1
103 ; RV64I-NEXT: ret
104 entry:
105 %cond = select i1 %a, i64 %b, i64 %c
106 ret i64 %cond
107 }
108
109 define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
110 ; RV32I-LABEL: cmov128:
111 ; RV32I: # %bb.0: # %entry
112 ; RV32I-NEXT: andi a1, a1, 1
113 ; RV32I-NEXT: bnez a1, .LBB3_2
114 ; RV32I-NEXT: # %bb.1: # %entry
115 ; RV32I-NEXT: addi a1, a3, 4
116 ; RV32I-NEXT: addi a4, a3, 8
117 ; RV32I-NEXT: addi a5, a3, 12
118 ; RV32I-NEXT: mv a2, a3
119 ; RV32I-NEXT: j .LBB3_3
120 ; RV32I-NEXT: .LBB3_2:
121 ; RV32I-NEXT: addi a1, a2, 4
122 ; RV32I-NEXT: addi a4, a2, 8
123 ; RV32I-NEXT: addi a5, a2, 12
124 ; RV32I-NEXT: .LBB3_3: # %entry
125 ; RV32I-NEXT: lw a3, 0(a5)
126 ; RV32I-NEXT: sw a3, 12(a0)
127 ; RV32I-NEXT: lw a3, 0(a4)
128 ; RV32I-NEXT: sw a3, 8(a0)
129 ; RV32I-NEXT: lw a1, 0(a1)
130 ; RV32I-NEXT: sw a1, 4(a0)
131 ; RV32I-NEXT: lw a1, 0(a2)
132 ; RV32I-NEXT: sw a1, 0(a0)
133 ; RV32I-NEXT: ret
134 ;
135 ; RV64I-LABEL: cmov128:
136 ; RV64I: # %bb.0: # %entry
137 ; RV64I-NEXT: andi a0, a0, 1
138 ; RV64I-NEXT: bnez a0, .LBB3_2
139 ; RV64I-NEXT: # %bb.1: # %entry
140 ; RV64I-NEXT: mv a1, a3
141 ; RV64I-NEXT: mv a2, a4
142 ; RV64I-NEXT: .LBB3_2: # %entry
143 ; RV64I-NEXT: mv a0, a1
144 ; RV64I-NEXT: mv a1, a2
145 ; RV64I-NEXT: ret
146 entry:
147 %cond = select i1 %a, i128 %b, i128 %c
148 ret i128 %cond
149 }
150
151 define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind {
152 ; RV32I-LABEL: cmovfloat:
153 ; RV32I: # %bb.0: # %entry
154 ; RV32I-NEXT: andi a0, a0, 1
155 ; RV32I-NEXT: bnez a0, .LBB4_2
156 ; RV32I-NEXT: # %bb.1: # %entry
157 ; RV32I-NEXT: fmv.w.x ft0, a4
158 ; RV32I-NEXT: fmv.w.x ft1, a2
159 ; RV32I-NEXT: j .LBB4_3
160 ; RV32I-NEXT: .LBB4_2:
161 ; RV32I-NEXT: fmv.w.x ft0, a3
162 ; RV32I-NEXT: fmv.w.x ft1, a1
163 ; RV32I-NEXT: .LBB4_3: # %entry
164 ; RV32I-NEXT: fadd.s ft0, ft1, ft0
165 ; RV32I-NEXT: fmv.x.w a0, ft0
166 ; RV32I-NEXT: ret
167 ;
168 ; RV64I-LABEL: cmovfloat:
169 ; RV64I: # %bb.0: # %entry
170 ; RV64I-NEXT: andi a0, a0, 1
171 ; RV64I-NEXT: bnez a0, .LBB4_2
172 ; RV64I-NEXT: # %bb.1: # %entry
173 ; RV64I-NEXT: fmv.w.x ft0, a4
174 ; RV64I-NEXT: fmv.w.x ft1, a2
175 ; RV64I-NEXT: j .LBB4_3
176 ; RV64I-NEXT: .LBB4_2:
177 ; RV64I-NEXT: fmv.w.x ft0, a3
178 ; RV64I-NEXT: fmv.w.x ft1, a1
179 ; RV64I-NEXT: .LBB4_3: # %entry
180 ; RV64I-NEXT: fadd.s ft0, ft1, ft0
181 ; RV64I-NEXT: fmv.x.w a0, ft0
182 ; RV64I-NEXT: ret
183 entry:
184 %cond1 = select i1 %a, float %b, float %c
185 %cond2 = select i1 %a, float %d, float %e
186 %ret = fadd float %cond1, %cond2
187 ret float %ret
188 }
189
190 define double @cmovdouble(i1 %a, double %b, double %c) nounwind {
191 ; RV32I-LABEL: cmovdouble:
192 ; RV32I: # %bb.0: # %entry
193 ; RV32I-NEXT: addi sp, sp, -16
194 ; RV32I-NEXT: sw a3, 8(sp)
195 ; RV32I-NEXT: sw a4, 12(sp)
196 ; RV32I-NEXT: fld ft0, 8(sp)
197 ; RV32I-NEXT: sw a1, 8(sp)
198 ; RV32I-NEXT: sw a2, 12(sp)
199 ; RV32I-NEXT: fld ft1, 8(sp)
200 ; RV32I-NEXT: andi a0, a0, 1
201 ; RV32I-NEXT: bnez a0, .LBB5_2
202 ; RV32I-NEXT: # %bb.1: # %entry
203 ; RV32I-NEXT: fmv.d ft1, ft0
204 ; RV32I-NEXT: .LBB5_2: # %entry
205 ; RV32I-NEXT: fsd ft1, 8(sp)
206 ; RV32I-NEXT: lw a0, 8(sp)
207 ; RV32I-NEXT: lw a1, 12(sp)
208 ; RV32I-NEXT: addi sp, sp, 16
209 ; RV32I-NEXT: ret
210 ;
211 ; RV64I-LABEL: cmovdouble:
212 ; RV64I: # %bb.0: # %entry
213 ; RV64I-NEXT: andi a0, a0, 1
214 ; RV64I-NEXT: bnez a0, .LBB5_2
215 ; RV64I-NEXT: # %bb.1: # %entry
216 ; RV64I-NEXT: fmv.d.x ft0, a2
217 ; RV64I-NEXT: fmv.x.d a0, ft0
218 ; RV64I-NEXT: ret
219 ; RV64I-NEXT: .LBB5_2:
220 ; RV64I-NEXT: fmv.d.x ft0, a1
221 ; RV64I-NEXT: fmv.x.d a0, ft0
222 ; RV64I-NEXT: ret
223 entry:
224 %cond = select i1 %a, double %b, double %c
225 ret double %cond
226 }
227
228 ; Check that selects with dependencies on previous ones aren't incorrectly
229 ; optimized.
230
231 define i32 @cmovccdep(i32 signext %a, i32 %b, i32 %c, i32 %d) nounwind {
232 ; RV32I-LABEL: cmovccdep:
233 ; RV32I: # %bb.0: # %entry
234 ; RV32I-NEXT: addi a4, zero, 123
235 ; RV32I-NEXT: bne a0, a4, .LBB6_3
236 ; RV32I-NEXT: # %bb.1: # %entry
237 ; RV32I-NEXT: mv a2, a1
238 ; RV32I-NEXT: bne a0, a4, .LBB6_4
239 ; RV32I-NEXT: .LBB6_2: # %entry
240 ; RV32I-NEXT: add a0, a1, a2
241 ; RV32I-NEXT: ret
242 ; RV32I-NEXT: .LBB6_3: # %entry
243 ; RV32I-NEXT: mv a1, a2
244 ; RV32I-NEXT: mv a2, a1
245 ; RV32I-NEXT: beq a0, a4, .LBB6_2
246 ; RV32I-NEXT: .LBB6_4: # %entry
247 ; RV32I-NEXT: mv a2, a3
248 ; RV32I-NEXT: add a0, a1, a2
249 ; RV32I-NEXT: ret
250 ;
251 ; RV64I-LABEL: cmovccdep:
252 ; RV64I: # %bb.0: # %entry
253 ; RV64I-NEXT: addi a4, zero, 123
254 ; RV64I-NEXT: bne a0, a4, .LBB6_3
255 ; RV64I-NEXT: # %bb.1: # %entry
256 ; RV64I-NEXT: mv a2, a1
257 ; RV64I-NEXT: bne a0, a4, .LBB6_4
258 ; RV64I-NEXT: .LBB6_2: # %entry
259 ; RV64I-NEXT: add a0, a1, a2
260 ; RV64I-NEXT: ret
261 ; RV64I-NEXT: .LBB6_3: # %entry
262 ; RV64I-NEXT: mv a1, a2
263 ; RV64I-NEXT: mv a2, a1
264 ; RV64I-NEXT: beq a0, a4, .LBB6_2
265 ; RV64I-NEXT: .LBB6_4: # %entry
266 ; RV64I-NEXT: mv a2, a3
267 ; RV64I-NEXT: add a0, a1, a2
268 ; RV64I-NEXT: ret
269 entry:
270 %cmp = icmp eq i32 %a, 123
271 %cond1 = select i1 %cmp, i32 %b, i32 %c
272 %cond2 = select i1 %cmp, i32 %cond1, i32 %d
273 %ret = add i32 %cond1, %cond2
274 ret i32 %ret
275 }
276
277 ; Check that selects with different conditions aren't incorrectly optimized.
278
279 define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
280 ; RV32I-LABEL: cmovdiffcc:
281 ; RV32I: # %bb.0: # %entry
282 ; RV32I-NEXT: andi a1, a1, 1
283 ; RV32I-NEXT: beqz a1, .LBB7_3
284 ; RV32I-NEXT: # %bb.1: # %entry
285 ; RV32I-NEXT: andi a0, a0, 1
286 ; RV32I-NEXT: beqz a0, .LBB7_4
287 ; RV32I-NEXT: .LBB7_2: # %entry
288 ; RV32I-NEXT: add a0, a2, a4
289 ; RV32I-NEXT: ret
290 ; RV32I-NEXT: .LBB7_3: # %entry
291 ; RV32I-NEXT: mv a4, a5
292 ; RV32I-NEXT: andi a0, a0, 1
293 ; RV32I-NEXT: bnez a0, .LBB7_2
294 ; RV32I-NEXT: .LBB7_4: # %entry
295 ; RV32I-NEXT: mv a2, a3
296 ; RV32I-NEXT: add a0, a2, a4
297 ; RV32I-NEXT: ret
298 ;
299 ; RV64I-LABEL: cmovdiffcc:
300 ; RV64I: # %bb.0: # %entry
301 ; RV64I-NEXT: andi a1, a1, 1
302 ; RV64I-NEXT: beqz a1, .LBB7_3
303 ; RV64I-NEXT: # %bb.1: # %entry
304 ; RV64I-NEXT: andi a0, a0, 1
305 ; RV64I-NEXT: beqz a0, .LBB7_4
306 ; RV64I-NEXT: .LBB7_2: # %entry
307 ; RV64I-NEXT: add a0, a2, a4
308 ; RV64I-NEXT: ret
309 ; RV64I-NEXT: .LBB7_3: # %entry
310 ; RV64I-NEXT: mv a4, a5
311 ; RV64I-NEXT: andi a0, a0, 1
312 ; RV64I-NEXT: bnez a0, .LBB7_2
313 ; RV64I-NEXT: .LBB7_4: # %entry
314 ; RV64I-NEXT: mv a2, a3
315 ; RV64I-NEXT: add a0, a2, a4
316 ; RV64I-NEXT: ret
317 entry:
318 %cond1 = select i1 %a, i32 %c, i32 %d
319 %cond2 = select i1 %b, i32 %e, i32 %f
320 %ret = add i32 %cond1, %cond2
321 ret i32 %ret
322 }
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=riscv32 -run-pass=expand-isel-pseudos -simplify-mir -o - %s \
2 # RUN: | FileCheck -check-prefix=RV32I %s
3 # RUN: llc -mtriple=riscv64 -run-pass=expand-isel-pseudos -simplify-mir -o - %s \
4 # RUN: | FileCheck -check-prefix=RV64I %s
5
6 # Provide dummy definitions of functions and just enough metadata to create a
7 # DBG_VALUE.
8 --- |
9 define void @cmov_interleaved_bad() {
10 ret void
11 }
12 define void @cmov_interleaved_debug_value() {
13 ret void
14 }
15 !1 = !DIExpression()
16 ...
17 ---
18 # Here we have a sequence of select instructions with a non-select instruction
19 # in the middle. Because the non-select depends on the result of a previous
20 # select, we cannot optimize the sequence to share control-flow.
21 name: cmov_interleaved_bad
22 alignment: 2
23 tracksRegLiveness: true
24 registers:
25 - { id: 0, class: gpr }
26 - { id: 1, class: gpr }
27 - { id: 2, class: gpr }
28 - { id: 3, class: gpr }
29 - { id: 4, class: gpr }
30 - { id: 5, class: gpr }
31 - { id: 6, class: gpr }
32 - { id: 7, class: gpr }
33 - { id: 8, class: gpr }
34 - { id: 9, class: gpr }
35 - { id: 10, class: gpr }
36 liveins:
37 - { reg: '$x10', virtual-reg: '%0' }
38 - { reg: '$x11', virtual-reg: '%1' }
39 - { reg: '$x12', virtual-reg: '%2' }
40 - { reg: '$x13', virtual-reg: '%3' }
41 body: |
42 bb.0:
43 liveins: $x10, $x11, $x12, $x13
44
45 ; RV32I-LABEL: name: cmov_interleaved_bad
46 ; RV32I: successors: %bb.1, %bb.2
47 ; RV32I: liveins: $x10, $x11, $x12, $x13
48 ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
49 ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
50 ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
51 ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
52 ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
53 ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
54 ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
55 ; RV32I: .1:
56 ; RV32I: .2:
57 ; RV32I: successors: %bb.3, %bb.4
58 ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
59 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
60 ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.4
61 ; RV32I: .3:
62 ; RV32I: .4:
63 ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
64 ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
65 ; RV32I: $x10 = COPY [[ADD]]
66 ; RV32I: PseudoRET implicit $x10
67 ; RV64I-LABEL: name: cmov_interleaved_bad
68 ; RV64I: successors: %bb.1, %bb.2
69 ; RV64I: liveins: $x10, $x11, $x12, $x13
70 ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
71 ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
72 ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
73 ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
74 ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
75 ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
76 ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
77 ; RV64I: .1:
78 ; RV64I: .2:
79 ; RV64I: successors: %bb.3, %bb.4
80 ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
81 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
82 ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.4
83 ; RV64I: .3:
84 ; RV64I: .4:
85 ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
86 ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
87 ; RV64I: $x10 = COPY [[ADD]]
88 ; RV64I: PseudoRET implicit $x10
89 %3:gpr = COPY $x13
90 %2:gpr = COPY $x12
91 %1:gpr = COPY $x11
92 %0:gpr = COPY $x10
93 %5:gpr = ANDI %0, 1
94 %6:gpr = COPY $x0
95 %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
96 %8:gpr = ADDI %7, 1
97 %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %3, %2
98 %10:gpr = ADD %7, killed %9
99 $x10 = COPY %10
100 PseudoRET implicit $x10
101
102 ...
103 ---
104 # Demonstrate that debug info associated with selects is correctly moved to
105 # the tail basic block, while debug info associated with non-selects is left
106 # in the head basic block.
107 name: cmov_interleaved_debug_value
108 alignment: 2
109 tracksRegLiveness: true
110 registers:
111 - { id: 0, class: gpr }
112 - { id: 1, class: gpr }
113 - { id: 2, class: gpr }
114 - { id: 3, class: gpr }
115 - { id: 4, class: gpr }
116 - { id: 5, class: gpr }
117 - { id: 6, class: gpr }
118 - { id: 7, class: gpr }
119 - { id: 8, class: gpr }
120 - { id: 9, class: gpr }
121 - { id: 10, class: gpr }
122 liveins:
123 - { reg: '$x10', virtual-reg: '%0' }
124 - { reg: '$x11', virtual-reg: '%1' }
125 - { reg: '$x12', virtual-reg: '%2' }
126 - { reg: '$x13', virtual-reg: '%3' }
127 body: |
128 bb.0:
129 liveins: $x10, $x11, $x12, $x13
130
131 ; RV32I-LABEL: name: cmov_interleaved_debug_value
132 ; RV32I: successors: %bb.1, %bb.2
133 ; RV32I: liveins: $x10, $x11, $x12, $x13
134 ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
135 ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
136 ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
137 ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
138 ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
139 ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
140 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
141 ; RV32I: DBG_VALUE [[ADDI]], $noreg, !DIExpression(), !DIExpression()
142 ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
143 ; RV32I: .1:
144 ; RV32I: .2:
145 ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
146 ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
147 ; RV32I: DBG_VALUE [[PHI]], $noreg, !DIExpression(), !DIExpression()
148 ; RV32I: DBG_VALUE [[PHI1]], $noreg, !DIExpression(), !DIExpression()
149 ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
150 ; RV32I: $x10 = COPY [[ADD]]
151 ; RV32I: PseudoRET implicit $x10
152 ; RV64I-LABEL: name: cmov_interleaved_debug_value
153 ; RV64I: successors: %bb.1, %bb.2
154 ; RV64I: liveins: $x10, $x11, $x12, $x13
155 ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
156 ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
157 ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
158 ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
159 ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
160 ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
161 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
162 ; RV64I: DBG_VALUE [[ADDI]], $noreg, !DIExpression(), !DIExpression()
163 ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
164 ; RV64I: .1:
165 ; RV64I: .2:
166 ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
167 ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
168 ; RV64I: DBG_VALUE [[PHI]], $noreg, !DIExpression(), !DIExpression()
169 ; RV64I: DBG_VALUE [[PHI1]], $noreg, !DIExpression(), !DIExpression()
170 ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
171 ; RV64I: $x10 = COPY [[ADD]]
172 ; RV64I: PseudoRET implicit $x10
173 %3:gpr = COPY $x13
174 %2:gpr = COPY $x12
175 %1:gpr = COPY $x11
176 %0:gpr = COPY $x10
177 %5:gpr = ANDI %0, 1
178 %6:gpr = COPY $x0
179 %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
180 DBG_VALUE %7, $noreg, !1, !1
181 %8:gpr = ADDI %0, 1
182 DBG_VALUE %8, $noreg, !1, !1
183 %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %3, %2
184 DBG_VALUE %9, $noreg, !1, !1
185 %10:gpr = ADD %7, killed %9
186 $x10 = COPY %10
187 PseudoRET implicit $x10
188
189 ...
190 ---