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[X86] Add patterns to fold EVEX store with EVEX encoded vcvtps2ph instructions. Remove bad pattern that had vf432 vcvtps2ph storing 128-bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317662 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 1 year, 11 months ago
2 changed file(s) with 27 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
72247224 (X86cvtps2ph (_src.VT _src.RC:$src1),
72257225 (i32 imm:$src2)),
72267226 NoItinerary, 0, 0>, AVX512AIi8Base;
7227 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
7228 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
7229 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7230 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
7231 (i32 imm:$src2))),
7232 addr:$dst)]>;
7233 let hasSideEffects = 0, mayStore = 1 in
7234 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
7235 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
7236 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
7237 []>, EVEX_K;
7227 let hasSideEffects = 0, mayStore = 1 in {
7228 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
7229 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
7230 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7231 []>;
7232 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
7233 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
7234 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
7235 []>, EVEX_K;
7236 }
72387237 }
72397238 multiclass avx512_cvtps2ph_sae {
72407239 let hasSideEffects = 0 in
72547253 defm VCVTPS2PHZ128 : avx512_cvtps2ph,
72557254 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
72567255 }
7256
7257 def : Pat<(store (f64 (extractelt
7258 (bc_v2f64 (v8i16 (X86cvtps2ph VR128X:$src1, i32:$src2))),
7259 (iPTR 0))), addr:$dst),
7260 (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, imm:$src2)>;
7261 def : Pat<(store (i64 (extractelt
7262 (bc_v2i64 (v8i16 (X86cvtps2ph VR128X:$src1, i32:$src2))),
7263 (iPTR 0))), addr:$dst),
7264 (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, imm:$src2)>;
7265 def : Pat<(store (v8i16 (X86cvtps2ph VR256X:$src1, i32:$src2)), addr:$dst),
7266 (VCVTPS2PHZ256mr addr:$dst, VR256X:$src1, imm:$src2)>;
7267 def : Pat<(store (v16i16 (X86cvtps2ph VR512:$src1, i32:$src2)), addr:$dst),
7268 (VCVTPS2PHZmr addr:$dst, VR512:$src1, imm:$src2)>;
72577269 }
72587270
72597271 // Patterns for matching conversions from float to half-float and vice versa.
302302 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_128_m2:
303303 ; X32-AVX512VL: # BB#0: # %entry
304304 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
305 ; X32-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0xc0,0x03]
306 ; X32-AVX512VL-NEXT: vmovlps %xmm0, (%eax) # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x13,0x00]
305 ; X32-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, (%eax) # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0x00,0x03]
307306 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3]
308307 ;
309308 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_128_m2:
310309 ; X64-AVX512VL: # BB#0: # %entry
311 ; X64-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0xc0,0x03]
312 ; X64-AVX512VL-NEXT: vmovlps %xmm0, (%rdi) # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x13,0x07]
310 ; X64-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, (%rdi) # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0x07,0x03]
313311 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
314312 entry:
315313 %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4x32, i32 3)
334332 ; X32-AVX512VL-LABEL: test_x86_vcvtps2ph_128_m3:
335333 ; X32-AVX512VL: # BB#0: # %entry
336334 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
337 ; X32-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0xc0,0x03]
338 ; X32-AVX512VL-NEXT: vmovlps %xmm0, (%eax) # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x13,0x00]
335 ; X32-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, (%eax) # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0x00,0x03]
339336 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3]
340337 ;
341338 ; X64-AVX512VL-LABEL: test_x86_vcvtps2ph_128_m3:
342339 ; X64-AVX512VL: # BB#0: # %entry
343 ; X64-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0xc0,0x03]
344 ; X64-AVX512VL-NEXT: vmovlps %xmm0, (%rdi) # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x13,0x07]
340 ; X64-AVX512VL-NEXT: vcvtps2ph $3, %xmm0, (%rdi) # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0x07,0x03]
345341 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
346342 entry:
347343 %0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4x32, i32 3)