llvm.org GIT mirror llvm / d4d9616
This patch fixes 8 out of 20 unexpected failures in "make check" when run on an Intel Atom processor. The failures have arisen due to changes elsewhere in the trunk over the past 8 weeks or so. These failures were not detected by the Atom buildbot because the CPU on the Atom buildbot was not being detected as an Atom CPU. The fix for this problem is in Host.cpp and X86Subtarget.cpp, but shall remain commented out until the current set of Atom test failures are fixed. Patch by Andy Zhang and Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160451 91177308-0d34-0410-b5e6-96231b3b80d8 Preston Gurd 7 years ago
11 changed file(s) with 74 addition(s) and 34 deletion(s). Raw diff Collapse all Expand all
248248 case 28: // Most 45 nm Intel Atom processors
249249 case 38: // 45 nm Atom Lincroft
250250 case 39: // 32 nm Atom Medfield
251 // re-enable when buildbot will pass all atom tests
252 //case 53: // 32 nm Atom Midview
253 //case 54: // 32 nm Atom Midview
251254 return "atom";
252255
253256 default: return (Em64T) ? "x86-64" : "i686";
253253
254254 // Set processor type. Currently only Atom is detected.
255255 if (Family == 6 &&
256 (Model == 28 || Model == 38 || Model == 39)) {
256 (Model == 28 || Model == 38 || Model == 39
257 /*|| Model == 53 || Model == 54*/)) {
257258 X86ProcFamily = IntelAtom;
258259
259260 UseLeaForSP = true;
None ; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck -check-prefix=atom %s
0 ; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck -check-prefix=ATOM %s
11 ; RUN: llc < %s -mcpu=core2 -mtriple=i686-linux | FileCheck %s
22
33 declare void @use_arr(i8*)
44 declare void @many_params(i32, i32, i32, i32, i32, i32)
55
66 define void @test1() nounwind {
7 ; atom: test1:
8 ; atom: leal -1052(%esp), %esp
9 ; atom-NOT: sub
10 ; atom: call
11 ; atom: leal 1052(%esp), %esp
7 ; ATOM: test1:
8 ; ATOM: leal -1052(%esp), %esp
9 ; ATOM-NOT: sub
10 ; ATOM: call
11 ; ATOM: leal 1052(%esp), %esp
1212
1313 ; CHECK: test1:
1414 ; CHECK: subl
2121 }
2222
2323 define void @test2() nounwind {
24 ; atom: test2:
25 ; atom: leal -28(%esp), %esp
26 ; atom: call
27 ; atom: leal 28(%esp), %esp
24 ; ATOM: test2:
25 ; ATOM: leal -28(%esp), %esp
26 ; ATOM: call
27 ; ATOM: leal 28(%esp), %esp
2828
2929 ; CHECK: test2:
3030 ; CHECK-NOT: lea
3333 }
3434
3535 define void @test3() nounwind {
36 ; atom: test3:
37 ; atom: leal -8(%esp), %esp
38 ; atom: leal 8(%esp), %esp
36 ; ATOM: test3:
37 ; ATOM: leal -8(%esp), %esp
38 ; ATOM: leal 8(%esp), %esp
3939
4040 ; CHECK: test3:
4141 ; CHECK-NOT: lea
None ; RUN: llc < %s -march=x86 >%t
1
2 ; RUN: grep "addl \$4," %t | count 3
3 ; RUN: not grep ",%" %t
0 ; RUN: llc < %s -march=x86 -mcpu=generic | FileCheck %s
1 ; RUN: llc < %s -march=x86 -mcpu=atom | FileCheck -check-prefix=ATOM %s
42
53 define void @foo(float* nocapture %A, float* nocapture %B, float* nocapture %C, i32 %N) nounwind {
4 ; ATOM: foo
5 ; ATOM: addl
6 ; ATOM: leal
7 ; ATOM: leal
8
9 ; CHECK: foo
10 ; CHECK: addl
11 ; CHECK: addl
12 ; CEHCK: addl
13
614 entry:
715 %0 = icmp sgt i32 %N, 0 ; [#uses=1]
816 br i1 %0, label %bb, label %return
None ; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast -optimize-regalloc=0 | FileCheck %s
1 ; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast | FileCheck %s
2 ; CHECKed instructions should be the same with or without -O0.
0 ; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -mcpu=generic -regalloc=fast -optimize-regalloc=0 | FileCheck %s
1 ; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -mcpu=generic -regalloc=fast | FileCheck %s
2 ; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -mcpu=atom -regalloc=fast -optimize-regalloc=0 | FileCheck -check-prefix=ATOM %s
3 ; CHECKed instructions should be the same with or without -O0 except on Intel Atom due to instruction scheduling.
34
45 @.str = private constant [12 x i8] c"x + y = %i\0A\00", align 1 ; <[12 x i8]*> [#uses=1]
56
1415 ; CHECK: movl %ebx, 40(%esp)
1516 ; CHECK-NOT: movl
1617 ; CHECK: addl %ebx, %eax
18
19 ; On Intel Atom the scheduler moves a movl instruction
20 ; used for the printf call to follow movl 24(%esp), %eax
21 ; ATOM: movl 24(%esp), %eax
22 ; ATOM: movl
23 ; ATOM: movl %eax, 36(%esp)
24 ; ATOM-NOT: movl
25 ; ATOM: movl 28(%esp), %ebx
26 ; ATOM-NOT: movl
27 ; ATOM: movl %ebx, 40(%esp)
28 ; ATOM-NOT: movl
29 ; ATOM: addl %ebx, %eax
30
1731 %retval = alloca i32 ; [#uses=2]
1832 %"%ebx" = alloca i32 ; [#uses=1]
1933 %"%eax" = alloca i32 ; [#uses=2]
None ; RUN: llc -march=x86 -mattr=+sse < %s | FileCheck %s
0 ; RUN: llc -march=x86 -mcpu=generic -mattr=+sse < %s | FileCheck %s
1 ; RUN: llc -march=x86 -mcpu=atom -mattr=+sse < %s | FileCheck -check-prefix=ATOM %s
12
23 %vec = type <6 x float>
34 ; CHECK: divss
45 ; CHECK: divss
56 ; CHECK: divps
7
8 ; Scheduler causes a different instruction order to be produced on Intel Atom
9 ; ATOM: divps
10 ; ATOM: divss
11 ; ATOM: divss
12
613 define %vec @vecdiv( %vec %p1, %vec %p2)
714 {
815 %result = fdiv %vec %p1, %p2
1515 entry:
1616 ; CHECK: shift1b:
1717 ; CHECK: movd
18 ; CHECK-NEXT: psllq
18 ; CHECK: psllq
1919 %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
2020 %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
2121 %shl = shl <2 x i64> %val, %1
3737 entry:
3838 ; CHECK: shift2b:
3939 ; CHECK: movd
40 ; CHECK-NEXT: pslld
40 ; CHECK: pslld
4141 %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
4242 %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
4343 %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
1515 entry:
1616 ; CHECK: shift1b:
1717 ; CHECK: movd
18 ; CHECK-NEXT: psrlq
18 ; CHECK: psrlq
1919 %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
2020 %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
2121 %lshr = lshr <2 x i64> %val, %1
3636 entry:
3737 ; CHECK: shift2b:
3838 ; CHECK: movd
39 ; CHECK-NEXT: psrld
39 ; CHECK: psrld
4040 %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
4141 %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
4242 %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
6262 ; CHECK: shift3b:
6363 ; CHECK: movzwl
6464 ; CHECK: movd
65 ; CHECK-NEXT: psrlw
65 ; CHECK: psrlw
6666 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
6767 %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
6868 %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
2727 entry:
2828 ; CHECK: shift2b:
2929 ; CHECK: movd
30 ; CHECK-NEXT: psrad
30 ; CHECK: psrad
3131 %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
3232 %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
3333 %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
5151 ; CHECK: shift3b:
5252 ; CHECK: movzwl
5353 ; CHECK: movd
54 ; CHECK-NEXT: psraw
54 ; CHECK: psraw
5555 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
5656 %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
5757 %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
55 entry:
66 ; CHECK: shift5a:
77 ; CHECK: movd
8 ; CHECK-NEXT: pslld
8 ; CHECK: pslld
99 %amt = load i32* %pamt
1010 %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
1111 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
1919 entry:
2020 ; CHECK: shift5b:
2121 ; CHECK: movd
22 ; CHECK-NEXT: psrad
22 ; CHECK: psrad
2323 %amt = load i32* %pamt
2424 %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
2525 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
3333 entry:
3434 ; CHECK: shift5c:
3535 ; CHECK: movd
36 ; CHECK-NEXT: pslld
36 ; CHECK: pslld
3737 %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
3838 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
3939 %shl = shl <4 x i32> %val, %shamt
4646 entry:
4747 ; CHECK: shift5d:
4848 ; CHECK: movd
49 ; CHECK-NEXT: psrad
49 ; CHECK: psrad
5050 %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
5151 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
5252 %shr = ashr <4 x i32> %val, %shamt
None ; RUN: llc -march=x86 -mattr=+sse42 < %s | FileCheck %s
0 ; RUN: llc -march=x86 -mcpu=generic -mattr=+sse42 < %s | FileCheck %s
1 ; RUN: llc -march=x86 -mcpu=atom -mattr=+sse42 < %s | FileCheck -check-prefix=ATOM %s
2
13 ; CHECK: paddd
24 ; CHECK: movl
35 ; CHECK: movlpd
6
7 ; Scheduler causes produce a different instruction order
8 ; ATOM: movl
9 ; ATOM: paddd
10 ; ATOM: movlpd
411
512 ; bitcast a v4i16 to v2i32
613