llvm.org GIT mirror llvm / d4b88df
[X86] Add LZCNT scheduling tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308133 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 3 years ago
1 changed file(s) with 97 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mattr=+lzcnt | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2
7
8 define i16 @test_ctlz_i16(i16 zeroext %a0, i16 *%a1) {
9 ; GENERIC-LABEL: test_ctlz_i16:
10 ; GENERIC: # BB#0:
11 ; GENERIC-NEXT: lzcntw (%rsi), %cx
12 ; GENERIC-NEXT: lzcntw %di, %ax
13 ; GENERIC-NEXT: orl %ecx, %eax
14 ; GENERIC-NEXT: # kill: %AX %AX %EAX
15 ; GENERIC-NEXT: retq
16 ;
17 ; HASWELL-LABEL: test_ctlz_i16:
18 ; HASWELL: # BB#0:
19 ; HASWELL-NEXT: lzcntw (%rsi), %cx
20 ; HASWELL-NEXT: lzcntw %di, %ax
21 ; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
22 ; HASWELL-NEXT: # kill: %AX %AX %EAX
23 ; HASWELL-NEXT: retq # sched: [1:1.00]
24 ;
25 ; BTVER2-LABEL: test_ctlz_i16:
26 ; BTVER2: # BB#0:
27 ; BTVER2-NEXT: lzcntw (%rsi), %cx
28 ; BTVER2-NEXT: lzcntw %di, %ax
29 ; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
30 ; BTVER2-NEXT: # kill: %AX %AX %EAX
31 ; BTVER2-NEXT: retq # sched: [4:1.00]
32 %1 = load i16, i16 *%a1
33 %2 = tail call i16 @llvm.ctlz.i16( i16 %1, i1 false )
34 %3 = tail call i16 @llvm.ctlz.i16( i16 %a0, i1 false )
35 %4 = or i16 %2, %3
36 ret i16 %4
37 }
38 declare i16 @llvm.ctlz.i16(i16, i1)
39
40 define i32 @test_ctlz_i32(i32 %a0, i32 *%a1) {
41 ; GENERIC-LABEL: test_ctlz_i32:
42 ; GENERIC: # BB#0:
43 ; GENERIC-NEXT: lzcntl (%rsi), %ecx
44 ; GENERIC-NEXT: lzcntl %edi, %eax
45 ; GENERIC-NEXT: orl %ecx, %eax
46 ; GENERIC-NEXT: retq
47 ;
48 ; HASWELL-LABEL: test_ctlz_i32:
49 ; HASWELL: # BB#0:
50 ; HASWELL-NEXT: lzcntl (%rsi), %ecx
51 ; HASWELL-NEXT: lzcntl %edi, %eax
52 ; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
53 ; HASWELL-NEXT: retq # sched: [1:1.00]
54 ;
55 ; BTVER2-LABEL: test_ctlz_i32:
56 ; BTVER2: # BB#0:
57 ; BTVER2-NEXT: lzcntl (%rsi), %ecx
58 ; BTVER2-NEXT: lzcntl %edi, %eax
59 ; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
60 ; BTVER2-NEXT: retq # sched: [4:1.00]
61 %1 = load i32, i32 *%a1
62 %2 = tail call i32 @llvm.ctlz.i32( i32 %1, i1 false )
63 %3 = tail call i32 @llvm.ctlz.i32( i32 %a0, i1 false )
64 %4 = or i32 %2, %3
65 ret i32 %4
66 }
67 declare i32 @llvm.ctlz.i32(i32, i1)
68
69 define i64 @test_ctlz_i64(i64 %a0, i64 *%a1) {
70 ; GENERIC-LABEL: test_ctlz_i64:
71 ; GENERIC: # BB#0:
72 ; GENERIC-NEXT: lzcntq (%rsi), %rcx
73 ; GENERIC-NEXT: lzcntq %rdi, %rax
74 ; GENERIC-NEXT: orq %rcx, %rax
75 ; GENERIC-NEXT: retq
76 ;
77 ; HASWELL-LABEL: test_ctlz_i64:
78 ; HASWELL: # BB#0:
79 ; HASWELL-NEXT: lzcntq (%rsi), %rcx
80 ; HASWELL-NEXT: lzcntq %rdi, %rax
81 ; HASWELL-NEXT: orq %rcx, %rax # sched: [1:0.25]
82 ; HASWELL-NEXT: retq # sched: [1:1.00]
83 ;
84 ; BTVER2-LABEL: test_ctlz_i64:
85 ; BTVER2: # BB#0:
86 ; BTVER2-NEXT: lzcntq (%rsi), %rcx
87 ; BTVER2-NEXT: lzcntq %rdi, %rax
88 ; BTVER2-NEXT: orq %rcx, %rax # sched: [1:0.50]
89 ; BTVER2-NEXT: retq # sched: [4:1.00]
90 %1 = load i64, i64 *%a1
91 %2 = tail call i64 @llvm.ctlz.i64( i64 %1, i1 false )
92 %3 = tail call i64 @llvm.ctlz.i64( i64 %a0, i1 false )
93 %4 = or i64 %2, %3
94 ret i64 %4
95 }
96 declare i64 @llvm.ctlz.i64(i64, i1)