llvm.org GIT mirror llvm / d4b4cf5
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as vector shuffles. Temporarily remove the tests for these operations until the new implementation is working. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79579 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
5 changed file(s) with 0 addition(s) and 420 deletion(s). Raw diff Collapse all Expand all
6060 LLVMTruncatedElementVectorType<0>,
6161 LLVMTruncatedElementVectorType<0>],
6262 [IntrNoMem]>;
63 class Neon_2Result_Intrinsic
64 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
65 [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
6663 class Neon_CvtFxToFP_Intrinsic
6764 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
6865 class Neon_CvtFPToFx_Intrinsic
313310 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
314311 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
315312 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
316
317 // Vector Transpose.
318 def int_arm_neon_vtrn : Neon_2Result_Intrinsic;
319
320 // Vector Interleave (vzip).
321 def int_arm_neon_vzip : Neon_2Result_Intrinsic;
322
323 // Vector Deinterleave (vuzp).
324 def int_arm_neon_vuzp : Neon_2Result_Intrinsic;
325313
326314 let TargetPrefix = "arm" in {
327315
14141414 N->getOperand(4), N->getOperand(5), Chain };
14151415 return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
14161416 }
1417
1418 case ISD::INTRINSIC_WO_CHAIN: {
1419 unsigned IntNo = cast(N->getOperand(0))->getZExtValue();
1420 EVT VT = N->getValueType(0);
1421 unsigned Opc = 0;
1422
1423 // Match intrinsics that return multiple values.
1424 switch (IntNo) {
1425 default: break;
1426
1427 case Intrinsic::arm_neon_vtrn:
1428 switch (VT.getSimpleVT().SimpleTy) {
1429 default: return NULL;
1430 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1431 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1432 case MVT::v2f32:
1433 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1434 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1435 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1436 case MVT::v4f32:
1437 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1438 }
1439 return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
1440 N->getOperand(2));
1441
1442 case Intrinsic::arm_neon_vuzp:
1443 switch (VT.getSimpleVT().SimpleTy) {
1444 default: return NULL;
1445 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1446 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1447 case MVT::v2f32:
1448 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1449 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1450 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1451 case MVT::v4f32:
1452 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1453 }
1454 return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
1455 N->getOperand(2));
1456
1457 case Intrinsic::arm_neon_vzip:
1458 switch (VT.getSimpleVT().SimpleTy) {
1459 default: return NULL;
1460 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1461 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1462 case MVT::v2f32:
1463 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1464 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1465 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1466 case MVT::v4f32:
1467 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1468 }
1469 return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
1470 N->getOperand(2));
1471 }
1472 break;
1473 }
14741417 }
14751418
14761419 return SelectCode(Op);
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test/CodeGen/ARM/vtrn.ll less more
None ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
1
2 %struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
3 %struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
4 %struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
5 %struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
6
7 %struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
8 %struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
9 %struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
10 %struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
11
12 define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
13 ;CHECK: vtrni8:
14 ;CHECK: vtrn.8
15 %tmp1 = load <8 x i8>* %A
16 %tmp2 = load <8 x i8>* %B
17 %tmp3 = call %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vtrn.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
18 %tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 0
19 %tmp5 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 1
20 %tmp6 = add <8 x i8> %tmp4, %tmp5
21 ret <8 x i8> %tmp6
22 }
23
24 define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
25 ;CHECK: vtrni16:
26 ;CHECK: vtrn.16
27 %tmp1 = load <4 x i16>* %A
28 %tmp2 = load <4 x i16>* %B
29 %tmp3 = call %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vtrn.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
30 %tmp4 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 0
31 %tmp5 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 1
32 %tmp6 = add <4 x i16> %tmp4, %tmp5
33 ret <4 x i16> %tmp6
34 }
35
36 define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
37 ;CHECK: vtrni32:
38 ;CHECK: vtrn.32
39 %tmp1 = load <2 x i32>* %A
40 %tmp2 = load <2 x i32>* %B
41 %tmp3 = call %struct.__builtin_neon_v2si2 @llvm.arm.neon.vtrn.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
42 %tmp4 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 0
43 %tmp5 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 1
44 %tmp6 = add <2 x i32> %tmp4, %tmp5
45 ret <2 x i32> %tmp6
46 }
47
48 define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
49 ;CHECK: vtrnf:
50 ;CHECK: vtrn.32
51 %tmp1 = load <2 x float>* %A
52 %tmp2 = load <2 x float>* %B
53 %tmp3 = call %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vtrn.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
54 %tmp4 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 0
55 %tmp5 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 1
56 %tmp6 = add <2 x float> %tmp4, %tmp5
57 ret <2 x float> %tmp6
58 }
59
60 define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
61 ;CHECK: vtrnQi8:
62 ;CHECK: vtrn.8
63 %tmp1 = load <16 x i8>* %A
64 %tmp2 = load <16 x i8>* %B
65 %tmp3 = call %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vtrn.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
66 %tmp4 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 0
67 %tmp5 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 1
68 %tmp6 = add <16 x i8> %tmp4, %tmp5
69 ret <16 x i8> %tmp6
70 }
71
72 define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
73 ;CHECK: vtrnQi16:
74 ;CHECK: vtrn.16
75 %tmp1 = load <8 x i16>* %A
76 %tmp2 = load <8 x i16>* %B
77 %tmp3 = call %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vtrn.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
78 %tmp4 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 0
79 %tmp5 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 1
80 %tmp6 = add <8 x i16> %tmp4, %tmp5
81 ret <8 x i16> %tmp6
82 }
83
84 define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
85 ;CHECK: vtrnQi32:
86 ;CHECK: vtrn.32
87 %tmp1 = load <4 x i32>* %A
88 %tmp2 = load <4 x i32>* %B
89 %tmp3 = call %struct.__builtin_neon_v4si2 @llvm.arm.neon.vtrn.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
90 %tmp4 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 0
91 %tmp5 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 1
92 %tmp6 = add <4 x i32> %tmp4, %tmp5
93 ret <4 x i32> %tmp6
94 }
95
96 define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
97 ;CHECK: vtrnQf:
98 ;CHECK: vtrn.32
99 %tmp1 = load <4 x float>* %A
100 %tmp2 = load <4 x float>* %B
101 %tmp3 = call %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vtrn.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
102 %tmp4 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 0
103 %tmp5 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 1
104 %tmp6 = add <4 x float> %tmp4, %tmp5
105 ret <4 x float> %tmp6
106 }
107
108 declare %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vtrn.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
109 declare %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vtrn.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
110 declare %struct.__builtin_neon_v2si2 @llvm.arm.neon.vtrn.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
111 declare %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vtrn.v2f32(<2 x float>, <2 x float>) nounwind readnone
112
113 declare %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vtrn.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
114 declare %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vtrn.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
115 declare %struct.__builtin_neon_v4si2 @llvm.arm.neon.vtrn.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
116 declare %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vtrn.v4f32(<4 x float>, <4 x float>) nounwind readnone
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test/CodeGen/ARM/vuzp.ll less more
None ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
1
2 %struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
3 %struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
4 %struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
5 %struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
6
7 %struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
8 %struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
9 %struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
10 %struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
11
12 define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
13 ;CHECK: vuzpi8:
14 ;CHECK: vuzp.8
15 %tmp1 = load <8 x i8>* %A
16 %tmp2 = load <8 x i8>* %B
17 %tmp3 = call %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vuzp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
18 %tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 0
19 %tmp5 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 1
20 %tmp6 = add <8 x i8> %tmp4, %tmp5
21 ret <8 x i8> %tmp6
22 }
23
24 define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
25 ;CHECK: vuzpi16:
26 ;CHECK: vuzp.16
27 %tmp1 = load <4 x i16>* %A
28 %tmp2 = load <4 x i16>* %B
29 %tmp3 = call %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vuzp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
30 %tmp4 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 0
31 %tmp5 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 1
32 %tmp6 = add <4 x i16> %tmp4, %tmp5
33 ret <4 x i16> %tmp6
34 }
35
36 define <2 x i32> @vuzpi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
37 ;CHECK: vuzpi32:
38 ;CHECK: vuzp.32
39 %tmp1 = load <2 x i32>* %A
40 %tmp2 = load <2 x i32>* %B
41 %tmp3 = call %struct.__builtin_neon_v2si2 @llvm.arm.neon.vuzp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
42 %tmp4 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 0
43 %tmp5 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 1
44 %tmp6 = add <2 x i32> %tmp4, %tmp5
45 ret <2 x i32> %tmp6
46 }
47
48 define <2 x float> @vuzpf(<2 x float>* %A, <2 x float>* %B) nounwind {
49 ;CHECK: vuzpf:
50 ;CHECK: vuzp.32
51 %tmp1 = load <2 x float>* %A
52 %tmp2 = load <2 x float>* %B
53 %tmp3 = call %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vuzp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
54 %tmp4 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 0
55 %tmp5 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 1
56 %tmp6 = add <2 x float> %tmp4, %tmp5
57 ret <2 x float> %tmp6
58 }
59
60 define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
61 ;CHECK: vuzpQi8:
62 ;CHECK: vuzp.8
63 %tmp1 = load <16 x i8>* %A
64 %tmp2 = load <16 x i8>* %B
65 %tmp3 = call %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vuzp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
66 %tmp4 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 0
67 %tmp5 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 1
68 %tmp6 = add <16 x i8> %tmp4, %tmp5
69 ret <16 x i8> %tmp6
70 }
71
72 define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
73 ;CHECK: vuzpQi16:
74 ;CHECK: vuzp.16
75 %tmp1 = load <8 x i16>* %A
76 %tmp2 = load <8 x i16>* %B
77 %tmp3 = call %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vuzp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
78 %tmp4 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 0
79 %tmp5 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 1
80 %tmp6 = add <8 x i16> %tmp4, %tmp5
81 ret <8 x i16> %tmp6
82 }
83
84 define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
85 ;CHECK: vuzpQi32:
86 ;CHECK: vuzp.32
87 %tmp1 = load <4 x i32>* %A
88 %tmp2 = load <4 x i32>* %B
89 %tmp3 = call %struct.__builtin_neon_v4si2 @llvm.arm.neon.vuzp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
90 %tmp4 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 0
91 %tmp5 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 1
92 %tmp6 = add <4 x i32> %tmp4, %tmp5
93 ret <4 x i32> %tmp6
94 }
95
96 define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
97 ;CHECK: vuzpQf:
98 ;CHECK: vuzp.32
99 %tmp1 = load <4 x float>* %A
100 %tmp2 = load <4 x float>* %B
101 %tmp3 = call %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vuzp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
102 %tmp4 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 0
103 %tmp5 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 1
104 %tmp6 = add <4 x float> %tmp4, %tmp5
105 ret <4 x float> %tmp6
106 }
107
108 declare %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vuzp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
109 declare %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vuzp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
110 declare %struct.__builtin_neon_v2si2 @llvm.arm.neon.vuzp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
111 declare %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vuzp.v2f32(<2 x float>, <2 x float>) nounwind readnone
112
113 declare %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vuzp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
114 declare %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vuzp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
115 declare %struct.__builtin_neon_v4si2 @llvm.arm.neon.vuzp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
116 declare %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vuzp.v4f32(<4 x float>, <4 x float>) nounwind readnone
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test/CodeGen/ARM/vzip.ll less more
None ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
1
2 %struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
3 %struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
4 %struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
5 %struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
6
7 %struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
8 %struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
9 %struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
10 %struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
11
12 define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
13 ;CHECK: vzipi8:
14 ;CHECK: vzip.8
15 %tmp1 = load <8 x i8>* %A
16 %tmp2 = load <8 x i8>* %B
17 %tmp3 = call %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vzip.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
18 %tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 0
19 %tmp5 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 1
20 %tmp6 = add <8 x i8> %tmp4, %tmp5
21 ret <8 x i8> %tmp6
22 }
23
24 define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
25 ;CHECK: vzipi16:
26 ;CHECK: vzip.16
27 %tmp1 = load <4 x i16>* %A
28 %tmp2 = load <4 x i16>* %B
29 %tmp3 = call %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vzip.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
30 %tmp4 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 0
31 %tmp5 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 1
32 %tmp6 = add <4 x i16> %tmp4, %tmp5
33 ret <4 x i16> %tmp6
34 }
35
36 define <2 x i32> @vzipi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
37 ;CHECK: vzipi32:
38 ;CHECK: vzip.32
39 %tmp1 = load <2 x i32>* %A
40 %tmp2 = load <2 x i32>* %B
41 %tmp3 = call %struct.__builtin_neon_v2si2 @llvm.arm.neon.vzip.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
42 %tmp4 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 0
43 %tmp5 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 1
44 %tmp6 = add <2 x i32> %tmp4, %tmp5
45 ret <2 x i32> %tmp6
46 }
47
48 define <2 x float> @vzipf(<2 x float>* %A, <2 x float>* %B) nounwind {
49 ;CHECK: vzipf:
50 ;CHECK: vzip.32
51 %tmp1 = load <2 x float>* %A
52 %tmp2 = load <2 x float>* %B
53 %tmp3 = call %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vzip.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
54 %tmp4 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 0
55 %tmp5 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 1
56 %tmp6 = add <2 x float> %tmp4, %tmp5
57 ret <2 x float> %tmp6
58 }
59
60 define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
61 ;CHECK: vzipQi8:
62 ;CHECK: vzip.8
63 %tmp1 = load <16 x i8>* %A
64 %tmp2 = load <16 x i8>* %B
65 %tmp3 = call %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vzip.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
66 %tmp4 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 0
67 %tmp5 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 1
68 %tmp6 = add <16 x i8> %tmp4, %tmp5
69 ret <16 x i8> %tmp6
70 }
71
72 define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
73 ;CHECK: vzipQi16:
74 ;CHECK: vzip.16
75 %tmp1 = load <8 x i16>* %A
76 %tmp2 = load <8 x i16>* %B
77 %tmp3 = call %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vzip.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
78 %tmp4 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 0
79 %tmp5 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 1
80 %tmp6 = add <8 x i16> %tmp4, %tmp5
81 ret <8 x i16> %tmp6
82 }
83
84 define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
85 ;CHECK: vzipQi32:
86 ;CHECK: vzip.32
87 %tmp1 = load <4 x i32>* %A
88 %tmp2 = load <4 x i32>* %B
89 %tmp3 = call %struct.__builtin_neon_v4si2 @llvm.arm.neon.vzip.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
90 %tmp4 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 0
91 %tmp5 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 1
92 %tmp6 = add <4 x i32> %tmp4, %tmp5
93 ret <4 x i32> %tmp6
94 }
95
96 define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
97 ;CHECK: vzipQf:
98 ;CHECK: vzip.32
99 %tmp1 = load <4 x float>* %A
100 %tmp2 = load <4 x float>* %B
101 %tmp3 = call %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vzip.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
102 %tmp4 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 0
103 %tmp5 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 1
104 %tmp6 = add <4 x float> %tmp4, %tmp5
105 ret <4 x float> %tmp6
106 }
107
108 declare %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vzip.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
109 declare %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vzip.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
110 declare %struct.__builtin_neon_v2si2 @llvm.arm.neon.vzip.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
111 declare %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vzip.v2f32(<2 x float>, <2 x float>) nounwind readnone
112
113 declare %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vzip.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
114 declare %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vzip.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
115 declare %struct.__builtin_neon_v4si2 @llvm.arm.neon.vzip.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
116 declare %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vzip.v4f32(<4 x float>, <4 x float>) nounwind readnone