llvm.org GIT mirror llvm / d48d215
[ARM] Remove ThumbTargetMachines. (NFC) Summary: Thumb code generation is controlled by ARMSubtarget and the concrete ThumbLETargetMachine and ThumbBETargetMachine are not needed. Eric Christopher suggested removing the unneeded target machines in https://reviews.llvm.org/D33287. I think it still makes sense to keep separate TargetMachines for big and little endian as we probably do not want to have different endianess for difference functions in a single compilation unit. The MIPS backend has two separate TargetMachines for big and little endian as well. Reviewers: echristo, rengolin, kristof.beyls, t.p.northover Reviewed By: echristo Subscribers: aemerson, javed.absar, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D33318 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303733 91177308-0d34-0410-b5e6-96231b3b80d8 Florian Hahn 3 years ago
3 changed file(s) with 15 addition(s) and 114 deletion(s). Raw diff Collapse all Expand all
8484 extern "C" void LLVMInitializeARMTarget() {
8585 // Register the target.
8686 RegisterTargetMachine X(getTheARMLETarget());
87 RegisterTargetMachine A(getTheThumbLETarget());
8788 RegisterTargetMachine Y(getTheARMBETarget());
88 RegisterTargetMachine A(getTheThumbLETarget());
89 RegisterTargetMachine<ThumbBETargetMachine> B(getTheThumbBETarget());
89 RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
9090
9191 PassRegistry &Registry = *PassRegistry::getPassRegistry();
9292 initializeGlobalISel(Registry);
262262 else
263263 this->Options.EABIVersion = EABI::EABI5;
264264 }
265
266 initAsmInfo();
267 if (!Subtarget.isThumb() && !Subtarget.hasARMOps())
268 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
269 "support ARM mode execution!");
265270 }
266271
267272 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
354359 });
355360 }
356361
357 void ARMTargetMachine::anchor() {}
358
359 ARMTargetMachine::ARMTargetMachine(const Target &T, const Triple &TT,
360 StringRef CPU, StringRef FS,
361 const TargetOptions &Options,
362 Optional RM,
363 CodeModel::Model CM, CodeGenOpt::Level OL,
364 bool isLittle)
365 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
366 initAsmInfo();
367 if (!Subtarget.hasARMOps())
368 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
369 "support ARM mode execution!");
370 }
371
372 void ARMLETargetMachine::anchor() {}
373362
374363 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
375364 StringRef CPU, StringRef FS,
377366 Optional RM,
378367 CodeModel::Model CM,
379368 CodeGenOpt::Level OL)
380 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
381
382 void ARMBETargetMachine::anchor() {}
369 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
383370
384371 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
385372 StringRef CPU, StringRef FS,
387374 Optional RM,
388375 CodeModel::Model CM,
389376 CodeGenOpt::Level OL)
390 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
391
392 void ThumbTargetMachine::anchor() {}
393
394 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const Triple &TT,
395 StringRef CPU, StringRef FS,
396 const TargetOptions &Options,
397 Optional RM,
398 CodeModel::Model CM,
399 CodeGenOpt::Level OL, bool isLittle)
400 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
401 initAsmInfo();
402 }
403
404 void ThumbLETargetMachine::anchor() {}
405
406 ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, const Triple &TT,
407 StringRef CPU, StringRef FS,
408 const TargetOptions &Options,
409 Optional RM,
410 CodeModel::Model CM,
411 CodeGenOpt::Level OL)
412 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
413
414 void ThumbBETargetMachine::anchor() {}
415
416 ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, const Triple &TT,
417 StringRef CPU, StringRef FS,
418 const TargetOptions &Options,
419 Optional RM,
420 CodeModel::Model CM,
421 CodeGenOpt::Level OL)
422 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
377 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
423378
424379 namespace {
425380
6161 }
6262 };
6363
64 /// ARM target machine.
64 /// ARM/Thumb little endian target machine.
6565 ///
66 class ARMTargetMachine : public ARMBaseTargetMachine {
67 virtual void anchor();
68
69 public:
70 ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
71 StringRef FS, const TargetOptions &Options,
72 Optional RM, CodeModel::Model CM,
73 CodeGenOpt::Level OL, bool isLittle);
74 };
75
76 /// ARM little endian target machine.
77 ///
78 class ARMLETargetMachine : public ARMTargetMachine {
79 void anchor() override;
80
66 class ARMLETargetMachine : public ARMBaseTargetMachine {
8167 public:
8268 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
8369 StringRef FS, const TargetOptions &Options,
8571 CodeGenOpt::Level OL);
8672 };
8773
88 /// ARM big endian target machine.
74 /// ARM/Thumb big endian target machine.
8975 ///
90 class ARMBETargetMachine : public ARMTargetMachine {
91 void anchor() override;
92
76 class ARMBETargetMachine : public ARMBaseTargetMachine {
9377 public:
9478 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
9579 StringRef FS, const TargetOptions &Options,
9781 CodeGenOpt::Level OL);
9882 };
9983
100 /// Thumb target machine.
101 /// Due to the way architectures are handled, this represents both
102 /// Thumb-1 and Thumb-2.
103 ///
104 class ThumbTargetMachine : public ARMBaseTargetMachine {
105 virtual void anchor();
106
107 public:
108 ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
109 StringRef FS, const TargetOptions &Options,
110 Optional RM, CodeModel::Model CM,
111 CodeGenOpt::Level OL, bool isLittle);
112 };
113
114 /// Thumb little endian target machine.
115 ///
116 class ThumbLETargetMachine : public ThumbTargetMachine {
117 void anchor() override;
118
119 public:
120 ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
121 StringRef FS, const TargetOptions &Options,
122 Optional RM, CodeModel::Model CM,
123 CodeGenOpt::Level OL);
124 };
125
126 /// Thumb big endian target machine.
127 ///
128 class ThumbBETargetMachine : public ThumbTargetMachine {
129 void anchor() override;
130
131 public:
132 ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
133 StringRef FS, const TargetOptions &Options,
134 Optional RM, CodeModel::Model CM,
135 CodeGenOpt::Level OL);
136 };
137
13884 } // end namespace llvm
13985
14086 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
2929
3030 void ARMElfTargetObjectFile::Initialize(MCContext &Ctx,
3131 const TargetMachine &TM) {
32 const ARMTargetMachine &ARM_TM = static_cast(TM);
33 bool isAAPCS_ABI = ARM_TM.TargetABI == ARMTargetMachine::ARMABI::ARM_ABI_AAPCS;
32 const ARMBaseTargetMachine &ARM_TM = static_cast(TM);
33 bool isAAPCS_ABI = ARM_TM.TargetABI == ARMBaseTargetMachine::ARMABI::ARM_ABI_AAPCS;
3434 genExecuteOnly = ARM_TM.getSubtargetImpl()->genExecuteOnly();
3535
3636 TargetLoweringObjectFileELF::Initialize(Ctx, TM);