llvm.org GIT mirror llvm / d478be2
Merge 81204 from mainline (with minor tweak). When remat'ing and destination virtual register has a sub-register index. Make sure the sub-register class matches the register class of the remat'ed instruction definition register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81270 91177308-0d34-0410-b5e6-96231b3b80d8 Tanya Lattner 11 years ago
2 changed file(s) with 64 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
631631 if (mri_->getRegClass(DstReg) != RC)
632632 return false;
633633 } else if (!RC->contains(DstReg))
634 return false;
635 }
636
637 // If destination register has a sub-register index on it, make sure it mtches
638 // the instruction register class.
639 if (DstSubIdx) {
640 const TargetInstrDesc &TID = DefMI->getDesc();
641 if (TID.getNumDefs() != 1)
642 return false;
643 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
644 const TargetRegisterClass *DstSubRC =
645 DstRC->getSubRegisterRegClass(DstSubIdx);
646 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
647 if (DefRC == DstRC)
648 DstSubIdx = 0;
649 else if (DefRC != DstSubRC)
634650 return false;
635651 }
636652
0 ; RUN: llvm-as < %s | llc -triple=x86_64-unknown-freebsd7.2 -code-model=kernel | FileCheck %s
1 ; PR4689
2
3 %struct.__s = type { [8 x i8] }
4 %struct.pcb = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i16, i8* }
5 %struct.pcpu = type { i32*, i32*, i32*, i32*, %struct.pcb*, i64, i32, i32, i32, i32 }
6
7 define i64 @hammer_time(i64 %modulep, i64 %physfree) nounwind ssp noredzone noimplicitfloat {
8 ; CHECK: hammer_time:
9 ; CHECK: movq $Xrsvd, %rax
10 ; CHECK: movq $Xrsvd, %rdi
11 ; CHECK: movq $Xrsvd, %r8
12 entry:
13 br i1 undef, label %if.then, label %if.end
14
15 if.then: ; preds = %entry
16 br label %if.end
17
18 if.end: ; preds = %if.then, %entry
19 br label %for.body
20
21 for.body: ; preds = %for.inc, %if.end
22 switch i32 undef, label %if.then76 [
23 i32 9, label %for.inc
24 i32 10, label %for.inc
25 i32 11, label %for.inc
26 i32 12, label %for.inc
27 ]
28
29 if.then76: ; preds = %for.body
30 unreachable
31
32 for.inc: ; preds = %for.body, %for.body, %for.body, %for.body
33 br i1 undef, label %for.end, label %for.body
34
35 for.end: ; preds = %for.inc
36 call void asm sideeffect "mov $1,%gs:$0", "=*m,r,~{dirflag},~{fpsr},~{flags}"(%struct.__s* bitcast (%struct.pcb** getelementptr (%struct.pcpu* null, i32 0, i32 4) to %struct.__s*), i64 undef) nounwind
37 br label %for.body170
38
39 for.body170: ; preds = %for.body170, %for.end
40 store i64 or (i64 and (i64 or (i64 ptrtoint (void (i32, i32, i32, i32)* @Xrsvd to i64), i64 2097152), i64 2162687), i64 or (i64 or (i64 and (i64 shl (i64 ptrtoint (void (i32, i32, i32, i32)* @Xrsvd to i64), i64 32), i64 -281474976710656), i64 140737488355328), i64 15393162788864)), i64* undef
41 br i1 undef, label %for.end175, label %for.body170
42
43 for.end175: ; preds = %for.body170
44 unreachable
45 }
46
47 declare void @Xrsvd(i32, i32, i32, i32) ssp noredzone noimplicitfloat