llvm.org GIT mirror llvm / d457e6e
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
7 changed file(s) with 83 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
1313 #include "ARMBaseInstrInfo.h"
1414 #include "ARM.h"
1515 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
1617 #include "ARMGenInstrInfo.inc"
1718 #include "ARMMachineFunctionInfo.h"
1819 #include "ARMRegisterInfo.h"
1920 #include "llvm/ADT/STLExtras.h"
2021 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
2123 #include "llvm/CodeGen/MachineFrameInfo.h"
2224 #include "llvm/CodeGen/MachineInstrBuilder.h"
2325 #include "llvm/CodeGen/MachineJumpTableInfo.h"
894896 return false;
895897 }
896898
899 bool ARMBaseInstrInfo::isIdentical(const MachineInstr *MI0,
900 const MachineInstr *MI1,
901 const MachineRegisterInfo *MRI) const {
902 int Opcode = MI0->getOpcode();
903 if (Opcode == ARM::t2LDRpci_pic || Opcode == ARM::tLDRpci_pic) {
904 if (MI1->getOpcode() != Opcode)
905 return false;
906 if (MI0->getNumOperands() != MI1->getNumOperands())
907 return false;
908
909 const MachineOperand &MO0 = MI0->getOperand(1);
910 const MachineOperand &MO1 = MI1->getOperand(1);
911 if (MO0.getOffset() != MO1.getOffset())
912 return false;
913
914 const MachineFunction *MF = MI0->getParent()->getParent();
915 const MachineConstantPool *MCP = MF->getConstantPool();
916 int CPI0 = MO0.getIndex();
917 int CPI1 = MO1.getIndex();
918 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
919 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
920 ARMConstantPoolValue *ACPV0 =
921 static_cast(MCPE0.Val.MachineCPVal);
922 ARMConstantPoolValue *ACPV1 =
923 static_cast(MCPE1.Val.MachineCPVal);
924 return ACPV0->hasSameValue(ACPV1);
925 }
926
927 return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI);
928 }
929
897930 /// getInstrPredicate - If instruction is predicated, returns its predicate
898931 /// condition, otherwise returns AL. It also returns the condition code
899932 /// register by reference.
262262 MachineInstr* MI,
263263 const SmallVectorImpl &Ops,
264264 MachineInstr* LoadMI) const;
265
266 virtual bool isIdentical(const MachineInstr *MI, const MachineInstr *Other,
267 const MachineRegisterInfo *MRI) const;
265268 };
266269
267270 static inline
590590 //===---------------------------------------------------------------------===//
591591
592592 Make use of the "rbit" instruction.
593
594 //===---------------------------------------------------------------------===//
595
596 Take a look at test/CodeGen/Thumb2/machine-licm.ll. ARM should be taught how
597 to licm and cse the unnecessary load from cp#1.
174174 NewMI->getOperand(0).setSubReg(SubIdx);
175175 }
176176
177 bool Thumb2InstrInfo::isIdentical(const MachineInstr *MI0,
178 const MachineInstr *MI1,
179 const MachineRegisterInfo *MRI) const {
180 unsigned Opcode = MI0->getOpcode();
181 if (Opcode == ARM::t2LDRpci_pic) {
182 const MachineOperand &MO0 = MI0->getOperand(1);
183 const MachineOperand &MO1 = MI1->getOperand(1);
184 if (MO0.getOffset() != MO1.getOffset())
185 return false;
186
187 const MachineFunction *MF = MI0->getParent()->getParent();
188 const MachineConstantPool *MCP = MF->getConstantPool();
189 int CPI0 = MO0.getIndex();
190 int CPI1 = MO1.getIndex();
191 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
192 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
193 ARMConstantPoolValue *ACPV0 =
194 static_cast(MCPE0.Val.MachineCPVal);
195 ARMConstantPoolValue *ACPV1 =
196 static_cast(MCPE1.Val.MachineCPVal);
197 return ACPV0->hasSameValue(ACPV1);
198 }
199
200 return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI);
201 }
202
203177 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
204178 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
205179 unsigned DestReg, unsigned BaseReg, int NumBytes,
5353 unsigned DestReg, unsigned SubIdx,
5454 const MachineInstr *Orig) const;
5555
56 bool isIdentical(const MachineInstr *MI,
57 const MachineInstr *Other,
58 const MachineRegisterInfo *MRI) const;
59
6056 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
6157 /// such, whenever a client has an instance of instruction info, it should
6258 /// always be able to get register info as well (through this method).
0 ; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s
1 ; rdar://7353541
2 ; rdar://7354376
3
4 ; The generated code is no where near ideal. It's not recognizing the two
5 ; constantpool entries being loaded can be merged into one.
6
7 @GV = external global i32 ; [#uses=2]
8
9 define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind {
10 entry:
11 ; CHECK: t:
12 %0 = icmp eq i32 %c, 0 ; [#uses=1]
13 br i1 %0, label %return, label %bb.nph
14
15 bb.nph: ; preds = %entry
16 ; CHECK: BB#1
17 ; CHECK: ldr.n r2, LCPI1_0
18 ; CHECK: add r2, pc
19 ; CHECK: ldr r{{[0-9]+}}, [r2]
20 ; CHECK: LBB1_2
21 ; CHECK: LCPI1_0:
22 ; CHECK-NOT: LCPI1_1:
23 ; CHECK: .section
24 %.pre = load i32* @GV, align 4 ; [#uses=1]
25 br label %bb
26
27 bb: ; preds = %bb, %bb.nph
28 %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; [#uses=1]
29 %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; [#uses=2]
30 %scevgep = getelementptr i32* %vals, i32 %i.03 ; [#uses=1]
31 %2 = load i32* %scevgep, align 4 ; [#uses=1]
32 %3 = add nsw i32 %1, %2 ; [#uses=2]
33 store i32 %3, i32* @GV, align 4
34 %4 = add i32 %i.03, 1 ; [#uses=2]
35 %exitcond = icmp eq i32 %4, %c ; [#uses=1]
36 br i1 %exitcond, label %return, label %bb
37
38 return: ; preds = %bb, %entry
39 ret void
40 }
0 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s
11 ; rdar://7353541
2 ; rdar://7354376
23
34 ; The generated code is no where near ideal. It's not recognizing the two
45 ; constantpool entries being loaded can be merged into one.