llvm.org GIT mirror llvm / d3fe603
[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0 According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0. This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified. Differential Revision: https://reviews.llvm.org/D32880 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302834 91177308-0d34-0410-b5e6-96231b3b80d8 Guozhi Wei 3 years ago
4 changed file(s) with 44 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
203203 PPC::X28, PPC::X29, PPC::X30, PPC::X31
204204 };
205205
206 static const unsigned G80Regs[] = {
207 PPC::ZERO8, PPC::X1, PPC::X2, PPC::X3,
208 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
209 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
210 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
211 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
212 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
213 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
214 PPC::X28, PPC::X29, PPC::X30, PPC::X31
215 };
216
206217 static const unsigned QFRegs[] = {
207218 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
208219 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
298309 uint64_t Address,
299310 const void *Decoder) {
300311 return decodeRegisterClass(Inst, RegNo, G8Regs);
312 }
313
314 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
315 uint64_t Address,
316 const void *Decoder) {
317 return decodeRegisterClass(Inst, RegNo, G80Regs);
301318 }
302319
303320 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
14351435 def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA),
14361436 "mtvsrws $XT, $rA", IIC_VecGeneral, []>;
14371437
1438 def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
1438 def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$rA, g8rc:$rB),
14391439 "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
14401440 []>, Requires<[In64BitMode]>;
14411441
0 ; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
1 ; RUN: < %s | FileCheck %s
2
3 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
4
5 define <2 x i64> @const0(i64 %a) {
6 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
7 %vecinit1 = insertelement <2 x i64> %vecinit, i64 0, i32 1
8 ret <2 x i64> %vecinit1
9 ; CHECK-LABEL: const0
10 ; CHECK: mtvsrdd v2, 0, r3
11 }
12
13 define <2 x i64> @noconst0(i64* %a, i64* %b) {
14 %1 = load i64, i64* %a, align 8
15 %2 = load i64, i64* %b, align 8
16 %vecinit = insertelement <2 x i64> undef, i64 %2, i32 0
17 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
18 ret <2 x i64> %vecinit1
19 ; CHECK-LABEL: noconst0
20 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
21 }
0 # RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck %s
1
2 # CHECK: mtvsrdd 6, 0, 3
3 0x66 0x1b 0xc0 0x7c