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[ARM] Rename MVE instructions in Tablegen for consistency. Summary: Their names began with a mishmash of `MVE_`, `t2` and no prefix at all. Now they all start with `MVE_`, which seems like a reasonable choice on the grounds that (a) NEON is the thing they're most at risk of being confused with, and (b) MVE implies Thumb-2, so a prefix indicating MVE is strictly more specific than one indicating Thumb-2. Reviewers: ostannard, SjoerdMeijer, dmgreen Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63492 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363690 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
6 changed file(s) with 303 addition(s) and 290 deletion(s). Raw diff Collapse all Expand all
477477 }
478478
479479 static inline bool isVPTOpcode(int Opc) {
480 return Opc == ARM::t2VPTv16i8 || Opc == ARM::t2VPTv16u8 ||
481 Opc == ARM::t2VPTv16s8 || Opc == ARM::t2VPTv8i16 ||
482 Opc == ARM::t2VPTv8u16 || Opc == ARM::t2VPTv8s16 ||
483 Opc == ARM::t2VPTv4i32 || Opc == ARM::t2VPTv4u32 ||
484 Opc == ARM::t2VPTv4s32 || Opc == ARM::t2VPTv4f32 ||
485 Opc == ARM::t2VPTv8f16 || Opc == ARM::t2VPTv16i8r ||
486 Opc == ARM::t2VPTv16u8r || Opc == ARM::t2VPTv16s8r ||
487 Opc == ARM::t2VPTv8i16r || Opc == ARM::t2VPTv8u16r ||
488 Opc == ARM::t2VPTv8s16r || Opc == ARM::t2VPTv4i32r ||
489 Opc == ARM::t2VPTv4u32r || Opc == ARM::t2VPTv4s32r ||
490 Opc == ARM::t2VPTv4f32r || Opc == ARM::t2VPTv8f16r ||
491 Opc == ARM::t2VPST;
480 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
481 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
482 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
483 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
484 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
485 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
486 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
487 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
488 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
489 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
490 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
491 Opc == ARM::MVE_VPST;
492492 }
493493
494494 static inline
112112 let DecoderNamespace = "MVE";
113113 }
114114
115 class t2MVEShift
115 class MVE_ScalarShift
116116 list pattern=[]>
117117 : MVE_MI_with_pred {
118118 let Inst{31-20} = 0b111010100101;
120120
121121 }
122122
123 class t2MVEShiftSingleReg
123 class MVE_ScalarShiftSingleReg
124124 list pattern=[]>
125 : t2MVEShift {
125 : MVE_ScalarShift {
126126 bits<4> RdaDest;
127127
128128 let Inst{19-16} = RdaDest{3-0};
129129 }
130130
131 class t2MVEShiftSRegImm op5_4, list pattern=[]>
132 : t2MVEShiftSingleReg
131 class MVE_ScalarShiftSRegImm op5_4, list pattern=[]>
132 : MVE_ScalarShiftSingleReg
133133 "$RdaSrc, $imm", "$RdaDest = $RdaSrc", pattern> {
134134 bits<5> imm;
135135
141141 let Inst{3-0} = 0b1111;
142142 }
143143
144 def t2SQSHL : t2MVEShiftSRegImm<"sqshl", 0b11>;
145 def t2SRSHR : t2MVEShiftSRegImm<"srshr", 0b10>;
146 def t2UQSHL : t2MVEShiftSRegImm<"uqshl", 0b00>;
147 def t2URSHR : t2MVEShiftSRegImm<"urshr", 0b01>;
148
149 class t2MVEShiftSRegReg op5_4, list pattern=[]>
150 : t2MVEShiftSingleReg
144 def MVE_SQSHL : MVE_ScalarShiftSRegImm<"sqshl", 0b11>;
145 def MVE_SRSHR : MVE_ScalarShiftSRegImm<"srshr", 0b10>;
146 def MVE_UQSHL : MVE_ScalarShiftSRegImm<"uqshl", 0b00>;
147 def MVE_URSHR : MVE_ScalarShiftSRegImm<"urshr", 0b01>;
148
149 class MVE_ScalarShiftSRegReg op5_4, list pattern=[]>
150 : MVE_ScalarShiftSingleReg
151151 "$RdaSrc, $Rm", "$RdaDest = $RdaSrc", pattern> {
152152 bits<4> Rm;
153153
158158 let Inst{3-0} = 0b1101;
159159 }
160160
161 def t2SQRSHR : t2MVEShiftSRegReg<"sqrshr", 0b10>;
162 def t2UQRSHL : t2MVEShiftSRegReg<"uqrshl", 0b00>;
163
164 class t2MVEShiftDoubleReg
165 list pattern=[]>
166 : t2MVEShift
167 pattern> {
161 def MVE_SQRSHR : MVE_ScalarShiftSRegReg<"sqrshr", 0b10>;
162 def MVE_UQRSHL : MVE_ScalarShiftSRegReg<"uqrshl", 0b00>;
163
164 class MVE_ScalarShiftDoubleReg
165 string cstr, list pattern=[]>
166 : MVE_ScalarShift
167 iops, asm, cstr, pattern> {
168168 bits<4> RdaLo;
169169 bits<4> RdaHi;
170170
172172 let Inst{11-9} = RdaHi{3-1};
173173 }
174174
175 class t2MVEShiftDRegImm op5_4, bit op16, list pattern=[]>
176 : t2MVEShiftDoubleReg
177 long_shift:$imm), "$RdaLo, $RdaHi, $imm",
178 "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src", pattern> {
175 class MVE_ScalarShiftDRegImm op5_4, bit op16,
176 list pattern=[]>
177 : MVE_ScalarShiftDoubleReg<
178 iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, long_shift:$imm),
179 "$RdaLo, $RdaHi, $imm", "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
180 pattern> {
179181 bits<5> imm;
180182
181183 let Inst{16} = op16;
186188 let Inst{3-0} = 0b1111;
187189 }
188190
189 class t2MVEShiftDRegReg pattern=[]>
190 : t2MVEShiftDoubleReg
191 "$RdaLo, $RdaHi, $Rm",
192 "@earlyclobber $RdaHi,@earlyclobber $RdaLo,$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
193 pattern> {
191 class MVE_ScalarShiftDRegReg
192 list pattern=[]>
193 : MVE_ScalarShiftDoubleReg<
194 iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm),
195 "$RdaLo, $RdaHi, $Rm", "@earlyclobber $RdaHi,@earlyclobber $RdaLo,"
196 "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
197 pattern> {
194198 bits<4> Rm;
195199
196200 let Inst{16} = op16;
208212 let DecoderMethod = "DecodeMVEOverlappingLongShift";
209213 }
210214
211 def t2ASRLr : t2MVEShiftDRegReg<"asrl", 0b1, 0b0>;
212 def t2ASRLi : t2MVEShiftDRegImm<"asrl", 0b10, ?>;
213 def t2LSLLr : t2MVEShiftDRegReg<"lsll", 0b0, 0b0>;
214 def t2LSLLi : t2MVEShiftDRegImm<"lsll", 0b00, ?>;
215 def t2LSRL : t2MVEShiftDRegImm<"lsrl", 0b01, ?>;
216
217 def t2SQRSHRL : t2MVEShiftDRegReg<"sqrshrl", 0b1, 0b1>;
218 def t2SQSHLL : t2MVEShiftDRegImm<"sqshll", 0b11, 0b1>;
219 def t2SRSHRL : t2MVEShiftDRegImm<"srshrl", 0b10, 0b1>;
220
221 def t2UQRSHLL : t2MVEShiftDRegReg<"uqrshll", 0b0, 0b1>;
222 def t2UQSHLL : t2MVEShiftDRegImm<"uqshll", 0b00, 0b1>;
223 def t2URSHRL : t2MVEShiftDRegImm<"urshrl", 0b01, 0b1>;
215 def MVE_ASRLr : MVE_ScalarShiftDRegReg<"asrl", 0b1, 0b0>;
216 def MVE_ASRLi : MVE_ScalarShiftDRegImm<"asrl", 0b10, ?>;
217 def MVE_LSLLr : MVE_ScalarShiftDRegReg<"lsll", 0b0, 0b0>;
218 def MVE_LSLLi : MVE_ScalarShiftDRegImm<"lsll", 0b00, ?>;
219 def MVE_LSRL : MVE_ScalarShiftDRegImm<"lsrl", 0b01, ?>;
220
221 def MVE_SQRSHRL : MVE_ScalarShiftDRegReg<"sqrshrl", 0b1, 0b1>;
222 def MVE_SQSHLL : MVE_ScalarShiftDRegImm<"sqshll", 0b11, 0b1>;
223 def MVE_SRSHRL : MVE_ScalarShiftDRegImm<"srshrl", 0b10, 0b1>;
224
225 def MVE_UQRSHLL : MVE_ScalarShiftDRegReg<"uqrshll", 0b0, 0b1>;
226 def MVE_UQSHLL : MVE_ScalarShiftDRegImm<"uqshll", 0b00, 0b1>;
227 def MVE_URSHRL : MVE_ScalarShiftDRegImm<"urshrl", 0b01, 0b1>;
224228
225229 // start of mve_rDest instructions
226230
227 class MVE_rDest string iname, string suffix,
231 class MVE_rDest
232 string iname, string suffix,
228233 string ops, string cstr, list pattern=[]>
229234 // Always use vpred_n and not vpred_r: with the output register being
230235 // a GPR and not a vector register, there can't be any question of
236241 let Inst{4} = 0b0;
237242 }
238243
239 class t2VABAV size, list pattern=[]>
244 class MVE_VABAV size, list pattern=[]>
240245 : MVE_rDest<(outs rGPR:$Rda), (ins rGPR:$Rda_src, MQPR:$Qn, MQPR:$Qm),
241246 NoItinerary, "vabav", suffix, "$Rda, $Qn, $Qm", "$Rda = $Rda_src",
242247 pattern> {
258263 let Inst{0} = 0b1;
259264 }
260265
261 def VABAVs8 : t2VABAV<"s8", 0b0, 0b00>;
262 def VABAVs16 : t2VABAV<"s16", 0b0, 0b01>;
263 def VABAVs32 : t2VABAV<"s32", 0b0, 0b10>;
264 def VABAVu8 : t2VABAV<"u8", 0b1, 0b00>;
265 def VABAVu16 : t2VABAV<"u16", 0b1, 0b01>;
266 def VABAVu32 : t2VABAV<"u32", 0b1, 0b10>;
267
268 class t2VADDV
266 def MVE_VABAVs8 : MVE_VABAV<"s8", 0b0, 0b00>;
267 def MVE_VABAVs16 : MVE_VABAV<"s16", 0b0, 0b01>;
268 def MVE_VABAVs32 : MVE_VABAV<"s32", 0b0, 0b10>;
269 def MVE_VABAVu8 : MVE_VABAV<"u8", 0b1, 0b00>;
270 def MVE_VABAVu16 : MVE_VABAV<"u16", 0b1, 0b01>;
271 def MVE_VABAVu32 : MVE_VABAV<"u32", 0b1, 0b10>;
272
273 class MVE_VADDV
269274 bit A, bit U, bits<2> size, list pattern=[]>
270275 : MVE_rDest<(outs tGPREven:$Rda), iops, NoItinerary,
271276 iname, suffix, "$Rda, $Qm", cstr, pattern> {
284289 let Inst{0} = 0b0;
285290 }
286291
287 multiclass t2VADDV_A size, list pattern=[]> {
288 def acc : t2VADDV<"vaddva", suffix,
289 (ins tGPREven:$Rda_src, MQPR:$Qm), "$Rda = $Rda_src",
290 0b1, U, size, pattern>;
291 def no_acc : t2VADDV<"vaddv", suffix,
292 (ins MQPR:$Qm), "",
293 0b0, U, size, pattern>;
294 }
295
296 defm VADDVs8 : t2VADDV_A<"s8", 0b0, 0b00>;
297 defm VADDVs16 : t2VADDV_A<"s16", 0b0, 0b01>;
298 defm VADDVs32 : t2VADDV_A<"s32", 0b0, 0b10>;
299 defm VADDVu8 : t2VADDV_A<"u8", 0b1, 0b00>;
300 defm VADDVu16 : t2VADDV_A<"u16", 0b1, 0b01>;
301 defm VADDVu32 : t2VADDV_A<"u32", 0b1, 0b10>;
302
303 class t2VADDLV,
292 multiclass MVE_VADDV_A size,
293 list pattern=[]> {
294 def acc : MVE_VADDV<"vaddva", suffix,
295 (ins tGPREven:$Rda_src, MQPR:$Qm), "$Rda = $Rda_src",
296 0b1, U, size, pattern>;
297 def no_acc : MVE_VADDV<"vaddv", suffix,
298 (ins MQPR:$Qm), "",
299 0b0, U, size, pattern>;
300 }
301
302 defm MVE_VADDVs8 : MVE_VADDV_A<"s8", 0b0, 0b00>;
303 defm MVE_VADDVs16 : MVE_VADDV_A<"s16", 0b0, 0b01>;
304 defm MVE_VADDVs32 : MVE_VADDV_A<"s32", 0b0, 0b10>;
305 defm MVE_VADDVu8 : MVE_VADDV_A<"u8", 0b1, 0b00>;
306 defm MVE_VADDVu16 : MVE_VADDV_A<"u16", 0b1, 0b01>;
307 defm MVE_VADDVu32 : MVE_VADDV_A<"u32", 0b1, 0b10>;
308
309 class MVE_VADDLV
304310 bit A, bit U, list pattern=[]>
305311 : MVE_rDest<(outs tGPREven:$RdaLo, tGPROdd:$RdaHi), iops, NoItinerary, iname,
306312 suffix, "$RdaLo, $RdaHi, $Qm", cstr, pattern> {
320326 let Inst{0} = 0b0;
321327 }
322328
323 multiclass t2VADDLV_A pattern=[]> {
324 def acc : t2VADDLV<"vaddlva", suffix,
329 multiclass MVE_VADDLV_A pattern=[]> {
330 def acc : MVE_VADDLV<"vaddlva", suffix,
325331 (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, MQPR:$Qm),
326332 "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
327333 0b1, U, pattern>;
328 def no_acc : t2VADDLV<"vaddlv", suffix,
334 def no_acc : MVE_VADDLV<"vaddlv", suffix,
329335 (ins MQPR:$Qm), "",
330336 0b0, U, pattern>;
331337 }
332338
333339
334 defm VADDLVs32 : t2VADDLV_A<"s32", 0b0>;
335 defm VADDLVu32 : t2VADDLV_A<"u32", 0b1>;
336
337 class t2VMINMAXNMV
338 list pattern=[]>
340 defm MVE_VADDLVs32 : MVE_VADDLV_A<"s32", 0b0>;
341 defm MVE_VADDLVu32 : MVE_VADDLV_A<"u32", 0b1>;
342
343 class MVE_VMINMAXNMV
344 bit bit_17, bit bit_7, list pattern=[]>
339345 : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm),
340346 NoItinerary, iname, suffix, "$RdaSrc, $Qm",
341347 "$RdaDest = $RdaSrc", pattern> {
357363 let Predicates = [HasMVEFloat];
358364 }
359365
360 multiclass t2VMINMAXNMV_fty pattern=[]> {
361 def f32 : t2VMINMAXNMV;
362 def f16 : t2VMINMAXNMV;
363 }
364
365 defm VMINNMV : t2VMINMAXNMV_fty<"vminnmv", 0b1>;
366 defm VMAXNMV : t2VMINMAXNMV_fty<"vmaxnmv", 0b0>;
367
368 multiclass t2VMINMAXNMAV_fty pattern=[]> {
369 def f32 : t2VMINMAXNMV;
370 def f16 : t2VMINMAXNMV;
371 }
372
373 defm VMINNMAV : t2VMINMAXNMAV_fty<"vminnmav", 0b1>;
374 defm VMAXNMAV : t2VMINMAXNMAV_fty<"vmaxnmav", 0b0>;
375
376 class t2VMINMAXV size,
366 multiclass MVE_VMINMAXNMV_fty pattern=[]> {
367 def f32 : MVE_VMINMAXNMV;
368 def f16 : MVE_VMINMAXNMV;
369 }
370
371 defm MVE_VMINNMV : MVE_VMINMAXNMV_fty<"vminnmv", 0b1>;
372 defm MVE_VMAXNMV : MVE_VMINMAXNMV_fty<"vmaxnmv", 0b0>;
373
374 multiclass MVE_VMINMAXNMAV_fty pattern=[]> {
375 def f32 : MVE_VMINMAXNMV;
376 def f16 : MVE_VMINMAXNMV;
377 }
378
379 defm MVE_VMINNMAV : MVE_VMINMAXNMAV_fty<"vminnmav", 0b1>;
380 defm MVE_VMAXNMAV : MVE_VMINMAXNMAV_fty<"vmaxnmav", 0b0>;
381
382 class MVE_VMINMAXV size,
377383 bit bit_17, bit bit_7, list pattern=[]>
378384 : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm), NoItinerary,
379385 iname, suffix, "$RdaSrc, $Qm", "$RdaDest = $RdaSrc", pattern> {
393399 let Inst{0} = 0b0;
394400 }
395401
396 multiclass t2VMINMAXV_ty pattern=[]> {
397 def s8 : t2VMINMAXV;
398 def s16 : t2VMINMAXV;
399 def s32 : t2VMINMAXV;
400 def u8 : t2VMINMAXV;
401 def u16 : t2VMINMAXV;
402 def u32 : t2VMINMAXV;
403 }
404
405 // Prefixed with MVE to prevent conflict with A57 scheduler.
406 defm MVE_VMINV : t2VMINMAXV_ty<"vminv", 0b1>;
407 defm MVE_VMAXV : t2VMINMAXV_ty<"vmaxv", 0b0>;
408
409 multiclass t2VMINMAXAV_ty pattern=[]> {
410 def s8 : t2VMINMAXV;
411 def s16 : t2VMINMAXV;
412 def s32 : t2VMINMAXV;
413 }
414
415 defm MVE_VMINAV : t2VMINMAXAV_ty<"vminav", 0b1>;
416 defm MVE_VMAXAV : t2VMINMAXAV_ty<"vmaxav", 0b0>;
417
418 class t2VMLAMLSDAV
402 multiclass MVE_VMINMAXV_ty pattern=[]> {
403 def s8 : MVE_VMINMAXV;
404 def s16 : MVE_VMINMAXV;
405 def s32 : MVE_VMINMAXV;
406 def u8 : MVE_VMINMAXV;
407 def u16 : MVE_VMINMAXV;
408 def u32 : MVE_VMINMAXV;
409 }
410
411 defm MVE_VMINV : MVE_VMINMAXV_ty<"vminv", 0b1>;
412 defm MVE_VMAXV : MVE_VMINMAXV_ty<"vmaxv", 0b0>;
413
414 multiclass MVE_VMINMAXAV_ty pattern=[]> {
415 def s8 : MVE_VMINMAXV;
416 def s16 : MVE_VMINMAXV;
417 def s32 : MVE_VMINMAXV;
418 }
419
420 defm MVE_VMINAV : MVE_VMINMAXAV_ty<"vminav", 0b1>;
421 defm MVE_VMAXAV : MVE_VMINMAXAV_ty<"vmaxav", 0b0>;
422
423 class MVE_VMLAMLSDAV
419424 bit sz, bit bit_28, bit A, bit X, bit bit_8, bit bit_0,
420425 list pattern=[]>
421426 : MVE_rDest<(outs tGPREven:$RdaDest), iops, NoItinerary, iname, suffix,
437442 let Inst{0} = bit_0;
438443 }
439444
440 multiclass t2VMLAMLSDAV_X
445 multiclass MVE_VMLAMLSDAV_X
441446 bit sz, bit bit_28, bit A, bit bit_8, bit bit_0,
442447 list pattern=[]> {
443 def _noexch : t2VMLAMLSDAV
448 def _noexch : MVE_VMLAMLSDAV
444449 bit_28, A, 0b0, bit_8, bit_0, pattern>;
445 def _exch : t2VMLAMLSDAV
450 def _exch : MVE_VMLAMLSDAV
446451 bit_28, A, 0b1, bit_8, bit_0, pattern>;
447452 }
448453
449 multiclass t2VMLAMLSDAV_XA
454 multiclass MVE_VMLAMLSDAV_XA
450455 bit bit_8, bit bit_0, list pattern=[]> {
451 defm _noacc : t2VMLAMLSDAV_X
456 defm _noacc : MVE_VMLAMLSDAV_X
452457 sz, bit_28, 0b0, bit_8, bit_0, pattern>;
453 defm _acc : t2VMLAMLSDAV_X
458 defm _acc : MVE_VMLAMLSDAV_X
454459 (ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
455460 "$RdaDest = $RdaSrc",
456461 sz, bit_28, 0b1, bit_8, bit_0, pattern>;
457462 }
458463
459 multiclass t2VMLADAV_multi
464 multiclass MVE_VMLADAV_multi
460465 list pattern=[]> {
461 defm "" : t2VMLAMLSDAV_XA<"vmladav", suffix, sz, U, bit_8, 0b0, pattern>;
462 }
463
464 defm VMLADAVs16 : t2VMLADAV_multi<"s16", 0b0, 0b0, 0b0>;
465 defm VMLADAVs32 : t2VMLADAV_multi<"s32", 0b1, 0b0, 0b0>;
466 defm VMLADAVu16 : t2VMLADAV_multi<"u16", 0b0, 0b1, 0b0>;
467 defm VMLADAVu32 : t2VMLADAV_multi<"u32", 0b1, 0b1, 0b0>;
468
469 defm VMLADAVs8 : t2VMLADAV_multi<"s8", 0b0, 0b0, 0b1>;
470 defm VMLADAVu8 : t2VMLADAV_multi<"u8", 0b0, 0b1, 0b1>;
466 defm "" : MVE_VMLAMLSDAV_XA<"vmladav", suffix, sz, U, bit_8, 0b0, pattern>;
467 }
468
469 defm MVE_VMLADAVs16 : MVE_VMLADAV_multi<"s16", 0b0, 0b0, 0b0>;
470 defm MVE_VMLADAVs32 : MVE_VMLADAV_multi<"s32", 0b1, 0b0, 0b0>;
471 defm MVE_VMLADAVu16 : MVE_VMLADAV_multi<"u16", 0b0, 0b1, 0b0>;
472 defm MVE_VMLADAVu32 : MVE_VMLADAV_multi<"u32", 0b1, 0b1, 0b0>;
473
474 defm MVE_VMLADAVs8 : MVE_VMLADAV_multi<"s8", 0b0, 0b0, 0b1>;
475 defm MVE_VMLADAVu8 : MVE_VMLADAV_multi<"u8", 0b0, 0b1, 0b1>;
471476
472477 // vmlav aliases vmladav
473478 foreach acc = ["_acc", "_noacc"] in {
474479 foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in {
475480 def : MVEInstAlias
476481 "${vp}.", suffix, "\t$RdaDest, $Qn, $Qm"),
477 (!cast(!strconcat("VMLADAV", suffix, acc, "_noexch")) tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
482 (!cast("MVE_VMLADAV"#suffix#acc#"_noexch")
483 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
478484 }
479485 }
480486
481 multiclass t2VMLSDAV_multi
487 multiclass MVE_VMLSDAV_multi
482488 list pattern=[]> {
483 defm "" : t2VMLAMLSDAV_XA<"vmlsdav", suffix, sz, bit_28, 0b0, 0b1, pattern>;
484 }
485
486 defm t2VMLSDAVs8 : t2VMLSDAV_multi<"s8", 0, 0b1>;
487 defm t2VMLSDAVs16 : t2VMLSDAV_multi<"s16", 0, 0b0>;
488 defm t2VMLSDAVs32 : t2VMLSDAV_multi<"s32", 1, 0b0>;
489 defm "" : MVE_VMLAMLSDAV_XA<"vmlsdav", suffix, sz, bit_28, 0b0, 0b1, pattern>;
490 }
491
492 defm MVE_VMLSDAVs8 : MVE_VMLSDAV_multi<"s8", 0, 0b1>;
493 defm MVE_VMLSDAVs16 : MVE_VMLSDAV_multi<"s16", 0, 0b0>;
494 defm MVE_VMLSDAVs32 : MVE_VMLSDAV_multi<"s32", 1, 0b0>;
489495
490496 // Base class for VMLALDAV and VMLSLDAV, VRMLALDAVH, VRMLSLDAVH
491 class t2VMLALDAVBase
492 bit bit_28, bit A, bit X, bit bit_8, bit bit_0,
493 list pattern=[]>
497 class MVE_VMLALDAVBase
498 bit sz, bit bit_28, bit A, bit X, bit bit_8, bit bit_0,
499 list pattern=[]>
494500 : MVE_rDest<(outs tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest), iops, NoItinerary,
495501 iname, suffix, "$RdaLoDest, $RdaHiDest, $Qn, $Qm", cstr, pattern> {
496502 bits<4> RdaLoDest;
511517 let Inst{0} = bit_0;
512518 }
513519
514 multiclass t2VMLALDAVBase_X
515 bit sz, bit bit_28, bit A, bit bit_8, bit bit_0,
516 list pattern=[]> {
517 def _noexch : t2VMLALDAVBase,
520 multiclass MVE_VMLALDAVBase_X,
521 string cstr, bit sz, bit bit_28, bit A,
522 bit bit_8, bit bit_0, list pattern=[]> {
523 def _noexch : MVE_VMLALDAVBase
518524 bit_28, A, 0b0, bit_8, bit_0, pattern>;
519 def _exch : t2VMLALDAVBase
525 def _exch : MVE_VMLALDAVBase
520526 bit_28, A, 0b1, bit_8, bit_0, pattern>;
521527 }
522528
523 multiclass t2VMLALDAVBase_XA
529 multiclass MVE_VMLALDAVBase_XA
524530 bit bit_8, bit bit_0, list pattern=[]> {
525 defm _noacc : t2VMLALDAVBase_X
526 (ins MQPR:$Qn, MQPR:$Qm), "",
527 sz, bit_28, 0b0, bit_8, bit_0, pattern>;
528 defm _acc : t2VMLALDAVBase_X
529 (ins tGPREven:$RdaLoSrc, tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm),
530 "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
531 sz, bit_28, 0b1, bit_8, bit_0, pattern>;
532 }
533
534 multiclass t2VRMLALDAVH_multi pattern=[]> {
535 defm "" : t2VMLALDAVBase_XA<"vrmlaldavh", suffix, 0b0, U, 0b1, 0b0, pattern>;
536 }
537
538 defm t2VRMLALDAVHs32 : t2VRMLALDAVH_multi<"s32", 0>;
539 defm t2VRMLALDAVHu32 : t2VRMLALDAVH_multi<"u32", 1>;
531 defm _noacc : MVE_VMLALDAVBase_X<
532 iname, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
533 sz, bit_28, 0b0, bit_8, bit_0, pattern>;
534 defm _acc : MVE_VMLALDAVBase_X<
535 iname # "a", suffix, (ins tGPREven:$RdaLoSrc, tGPROdd:$RdaHiSrc,
536 MQPR:$Qn, MQPR:$Qm),
537 "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
538 sz, bit_28, 0b1, bit_8, bit_0, pattern>;
539 }
540
541 multiclass MVE_VRMLALDAVH_multi pattern=[]> {
542 defm "" : MVE_VMLALDAVBase_XA<
543 "vrmlaldavh", suffix, 0b0, U, 0b1, 0b0, pattern>;
544 }
545
546 defm MVE_VRMLALDAVHs32 : MVE_VRMLALDAVH_multi<"s32", 0>;
547 defm MVE_VRMLALDAVHu32 : MVE_VRMLALDAVH_multi<"u32", 1>;
540548
541549 // vrmlalvh aliases for vrmlaldavh
542550 def : MVEInstAlias<"vrmlalvh${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
543 (t2VRMLALDAVHs32_noacc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
551 (MVE_VRMLALDAVHs32_noacc_noexch
552 tGPREven:$RdaLo, tGPROdd:$RdaHi,
544553 MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
545554 def : MVEInstAlias<"vrmlalvha${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
546 (t2VRMLALDAVHs32_acc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
555 (MVE_VRMLALDAVHs32_acc_noexch
556 tGPREven:$RdaLo, tGPROdd:$RdaHi,
547557 MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
548558 def : MVEInstAlias<"vrmlalvh${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
549 (t2VRMLALDAVHu32_noacc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
559 (MVE_VRMLALDAVHu32_noacc_noexch
560 tGPREven:$RdaLo, tGPROdd:$RdaHi,
550561 MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
551562 def : MVEInstAlias<"vrmlalvha${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
552 (t2VRMLALDAVHu32_acc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
563 (MVE_VRMLALDAVHu32_acc_noexch
564 tGPREven:$RdaLo, tGPROdd:$RdaHi,
553565 MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
554566
555 multiclass t2VMLALDAV_multi pattern=[]> {
556 defm "" : t2VMLALDAVBase_XA<"vmlaldav", suffix, sz, U, 0b0, 0b0, pattern>;
557 }
558
559 defm VMLALDAVs16 : t2VMLALDAV_multi<"s16", 0b0, 0b0>;
560 defm VMLALDAVs32 : t2VMLALDAV_multi<"s32", 0b1, 0b0>;
561 defm VMLALDAVu16 : t2VMLALDAV_multi<"u16", 0b0, 0b1>;
562 defm VMLALDAVu32 : t2VMLALDAV_multi<"u32", 0b1, 0b1>;
567 multiclass MVE_VMLALDAV_multi
568 list pattern=[]> {
569 defm "" : MVE_VMLALDAVBase_XA<"vmlaldav", suffix, sz, U, 0b0, 0b0, pattern>;
570 }
571
572 defm MVE_VMLALDAVs16 : MVE_VMLALDAV_multi<"s16", 0b0, 0b0>;
573 defm MVE_VMLALDAVs32 : MVE_VMLALDAV_multi<"s32", 0b1, 0b0>;
574 defm MVE_VMLALDAVu16 : MVE_VMLALDAV_multi<"u16", 0b0, 0b1>;
575 defm MVE_VMLALDAVu32 : MVE_VMLALDAV_multi<"u32", 0b1, 0b1>;
563576
564577 // vmlalv aliases vmlaldav
565578 foreach acc = ["_acc", "_noacc"] in {
566579 foreach suffix = ["s16", "s32", "u16", "u32"] in {
567580 def : MVEInstAlias
568581 "${vp}.", suffix, "\t$RdaLoDest, $RdaHiDest, $Qn, $Qm"),
569 (!cast(!strconcat("VMLALDAV", suffix, acc, "_noexch"))
582 (!cast("MVE_VMLALDAV"#suffix#acc#"_noexch")
570583 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest,
571584 MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
572585 }
573586 }
574587
575 multiclass t2VMLSLDAV_multi
588 multiclass MVE_VMLSLDAV_multi
576589 bit bit_28, list pattern=[]> {
577 defm "" : t2VMLALDAVBase_XA;
578 }
579
580 defm t2VMLSLDAVs16 : t2VMLSLDAV_multi<"vmlsldav", "s16", 0b0, 0b0>;
581 defm t2VMLSLDAVs32 : t2VMLSLDAV_multi<"vmlsldav", "s32", 0b1, 0b0>;
582 defm t2VRMLSLDAVHs32 : t2VMLSLDAV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
590 defm "" : MVE_VMLALDAVBase_XA>;
591 }
592
593 defm MVE_VMLSLDAVs16 : MVE_VMLSLDAV_multi<"vmlsldav", "s16", 0b0, 0b0>;
594 defm MVE_VMLSLDAVs32 : MVE_VMLSLDAV_multi<"vmlsldav", "s32", 0b1, 0b0>;
595 defm MVE_VRMLSLDAVHs32 : MVE_VMLSLDAV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
583596
584597 // end of mve_rDest instructions
585598
605618 let Inst{0} = 0b0;
606619 }
607620
608 class VMINMAXNM
621 class MVE_VMINMAXNM
609622 list pattern=[]>
610623 : MVE_comp {
611624
622635 let Predicates = [HasMVEFloat];
623636 }
624637
625 def VMAXNMf32 : VMINMAXNM<"vmaxnm", "f32", 0b0, 0b0>;
626 def VMAXNMf16 : VMINMAXNM<"vmaxnm", "f16", 0b1, 0b0>;
627
628 def VMINNMf32 : VMINMAXNM<"vminnm", "f32", 0b0, 0b1>;
629 def VMINNMf16 : VMINMAXNM<"vminnm", "f16", 0b1, 0b1>;
638 def MVE_VMAXNMf32 : MVE_VMINMAXNM<"vmaxnm", "f32", 0b0, 0b0>;
639 def MVE_VMAXNMf16 : MVE_VMINMAXNM<"vmaxnm", "f16", 0b1, 0b0>;
640
641 def MVE_VMINNMf32 : MVE_VMINMAXNM<"vminnm", "f32", 0b0, 0b1>;
642 def MVE_VMINNMf16 : MVE_VMINMAXNM<"vminnm", "f16", 0b1, 0b1>;
630643
631644 // end of mve_comp instructions
632645
633 class t2VPT size, dag iops, string asm, list pattern=[]>
646 class MVE_VPT size, dag iops, string asm, list pattern=[]>
634647 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
635648 bits<3> fc;
636649 bits<4> Mk;
650663 let Defs = [VPR, P0];
651664 }
652665
653 class t2VPTt1 size, dag iops>
654 : t2VPT {
666 class MVE_VPTt1 size, dag iops>
667 : MVE_VPT {
655668 bits<4> Qm;
656669 bits<4> Mk;
657670
661674 let Inst{0} = fc{1};
662675 }
663676
664 class t2VPTt1i size>
665 : t2VPTt1
677 class MVE_VPTt1i size>
678 : MVE_VPTt1
666679 (ins vpt_mask:$Mk, pred_basic_i:$fc, MQPR:$Qn, MQPR:$Qm)> {
667680 let Inst{12} = 0b0;
668681 let Inst{0} = 0b0;
669682 }
670683
671 def t2VPTv4i32 : t2VPTt1i<"i32", 0b10>;
672 def t2VPTv8i16 : t2VPTt1i<"i16", 0b01>;
673 def t2VPTv16i8 : t2VPTt1i<"i8", 0b00>;
674
675 class t2VPTt1u size>
676 : t2VPTt1
684 def MVE_VPTv4i32 : MVE_VPTt1i<"i32", 0b10>;
685 def MVE_VPTv8i16 : MVE_VPTt1i<"i16", 0b01>;
686 def MVE_VPTv16i8 : MVE_VPTt1i<"i8", 0b00>;
687
688 class MVE_VPTt1u size>
689 : MVE_VPTt1
677690 (ins vpt_mask:$Mk, pred_basic_u:$fc, MQPR:$Qn, MQPR:$Qm)> {
678691 let Inst{12} = 0b0;
679692 let Inst{0} = 0b1;
680693 }
681694
682 def t2VPTv4u32 : t2VPTt1u<"u32", 0b10>;
683 def t2VPTv8u16 : t2VPTt1u<"u16", 0b01>;
684 def t2VPTv16u8 : t2VPTt1u<"u8", 0b00>;
685
686 class t2VPTt1s size>
687 : t2VPTt1
695 def MVE_VPTv4u32 : MVE_VPTt1u<"u32", 0b10>;
696 def MVE_VPTv8u16 : MVE_VPTt1u<"u16", 0b01>;
697 def MVE_VPTv16u8 : MVE_VPTt1u<"u8", 0b00>;
698
699 class MVE_VPTt1s size>
700 : MVE_VPTt1
688701 (ins vpt_mask:$Mk, pred_basic_s:$fc, MQPR:$Qn, MQPR:$Qm)> {
689702 let Inst{12} = 0b1;
690703 }
691704
692 def t2VPTv4s32 : t2VPTt1s<"s32", 0b10>;
693 def t2VPTv8s16 : t2VPTt1s<"s16", 0b01>;
694 def t2VPTv16s8 : t2VPTt1s<"s8", 0b00>;
695
696 class t2VPTt2 size, dag iops>
697 : t2VPT
705 def MVE_VPTv4s32 : MVE_VPTt1s<"s32", 0b10>;
706 def MVE_VPTv8s16 : MVE_VPTt1s<"s16", 0b01>;
707 def MVE_VPTv16s8 : MVE_VPTt1s<"s8", 0b00>;
708
709 class MVE_VPTt2 size, dag iops>
710 : MVE_VPT
698711 "$fc, $Qn, $Rm"> {
699712 bits<4> Rm;
700713 bits<3> fc;
705718 let Inst{3-0} = Rm{3-0};
706719 }
707720
708 class t2VPTt2i size>
709 : t2VPTt2
721 class MVE_VPTt2i size>
722 : MVE_VPTt2
710723 (ins vpt_mask:$Mk, pred_basic_i:$fc, MQPR:$Qn, GPRwithZR:$Rm)> {
711724 let Inst{12} = 0b0;
712725 let Inst{5} = 0b0;
713726 }
714727
715 def t2VPTv4i32r : t2VPTt2i<"i32", 0b10>;
716 def t2VPTv8i16r : t2VPTt2i<"i16", 0b01>;
717 def t2VPTv16i8r : t2VPTt2i<"i8", 0b00>;
718
719 class t2VPTt2u size>
720 : t2VPTt2
728 def MVE_VPTv4i32r : MVE_VPTt2i<"i32", 0b10>;
729 def MVE_VPTv8i16r : MVE_VPTt2i<"i16", 0b01>;
730 def MVE_VPTv16i8r : MVE_VPTt2i<"i8", 0b00>;
731
732 class MVE_VPTt2u size>
733 : MVE_VPTt2
721734 (ins vpt_mask:$Mk, pred_basic_u:$fc, MQPR:$Qn, GPRwithZR:$Rm)> {
722735 let Inst{12} = 0b0;
723736 let Inst{5} = 0b1;
724737 }
725738
726 def t2VPTv4u32r : t2VPTt2u<"u32", 0b10>;
727 def t2VPTv8u16r : t2VPTt2u<"u16", 0b01>;
728 def t2VPTv16u8r : t2VPTt2u<"u8", 0b00>;
729
730 class t2VPTt2s size>
731 : t2VPTt2
739 def MVE_VPTv4u32r : MVE_VPTt2u<"u32", 0b10>;
740 def MVE_VPTv8u16r : MVE_VPTt2u<"u16", 0b01>;
741 def MVE_VPTv16u8r : MVE_VPTt2u<"u8", 0b00>;
742
743 class MVE_VPTt2s size>
744 : MVE_VPTt2
732745 (ins vpt_mask:$Mk, pred_basic_s:$fc, MQPR:$Qn, GPRwithZR:$Rm)> {
733746 let Inst{12} = 0b1;
734747 }
735748
736 def t2VPTv4s32r : t2VPTt2s<"s32", 0b10>;
737 def t2VPTv8s16r : t2VPTt2s<"s16", 0b01>;
738 def t2VPTv16s8r : t2VPTt2s<"s8", 0b00>;
739
740
741 class t2VPTf pattern=[]>
749 def MVE_VPTv4s32r : MVE_VPTt2s<"s32", 0b10>;
750 def MVE_VPTv8s16r : MVE_VPTt2s<"s16", 0b01>;
751 def MVE_VPTv16s8r : MVE_VPTt2s<"s8", 0b00>;
752
753
754 class MVE_VPTf pattern=[]>
742755 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm,
743756 "", pattern> {
744757 bits<3> fc;
762775 let Predicates = [HasMVEFloat];
763776 }
764777
765 class t2VPTft1
766 : t2VPTf
778 class MVE_VPTft1
779 : MVE_VPTf
767780 "$fc, $Qn, $Qm"> {
768781 bits<3> fc;
769782 bits<4> Qm;
774787 let Inst{0} = fc{1};
775788 }
776789
777 def t2VPTv4f32 : t2VPTft1<"f32", 0b0>;
778 def t2VPTv8f16 : t2VPTft1<"f16", 0b1>;
779
780 class t2VPTft2
781 : t2VPTf
790 def MVE_VPTv4f32 : MVE_VPTft1<"f32", 0b0>;
791 def MVE_VPTv8f16 : MVE_VPTft1<"f16", 0b1>;
792
793 class MVE_VPTft2
794 : MVE_VPTf
782795 "$fc, $Qn, $Rm"> {
783796 bits<3> fc;
784797 bits<4> Rm;
788801 let Inst{3-0} = Rm{3-0};
789802 }
790803
791 def t2VPTv4f32r : t2VPTft2<"f32", 0b0>;
792 def t2VPTv8f16r : t2VPTft2<"f16", 0b1>;
793
794 def t2VPST : MVE_MI<(outs ), (ins vpt_mask:$Mk), NoItinerary,
804 def MVE_VPTv4f32r : MVE_VPTft2<"f32", 0b0>;
805 def MVE_VPTv8f16r : MVE_VPTft2<"f16", 0b1>;
806
807 def MVE_VPST : MVE_MI<(outs ), (ins vpt_mask:$Mk), NoItinerary,
795808 !strconcat("vpst", "${Mk}"), "", "", []> {
796809 bits<4> Mk;
797810
95899589 return true;
95909590 }
95919591 return false;
9592 case ARM::t2VPST:
9593 case ARM::t2VPTv16i8:
9594 case ARM::t2VPTv8i16:
9595 case ARM::t2VPTv4i32:
9596 case ARM::t2VPTv16u8:
9597 case ARM::t2VPTv8u16:
9598 case ARM::t2VPTv4u32:
9599 case ARM::t2VPTv16s8:
9600 case ARM::t2VPTv8s16:
9601 case ARM::t2VPTv4s32:
9602 case ARM::t2VPTv4f32:
9603 case ARM::t2VPTv8f16:
9604 case ARM::t2VPTv16i8r:
9605 case ARM::t2VPTv8i16r:
9606 case ARM::t2VPTv4i32r:
9607 case ARM::t2VPTv16u8r:
9608 case ARM::t2VPTv8u16r:
9609 case ARM::t2VPTv4u32r:
9610 case ARM::t2VPTv16s8r:
9611 case ARM::t2VPTv8s16r:
9612 case ARM::t2VPTv4s32r:
9613 case ARM::t2VPTv4f32r:
9614 case ARM::t2VPTv8f16r: {
9592 case ARM::MVE_VPST:
9593 case ARM::MVE_VPTv16i8:
9594 case ARM::MVE_VPTv8i16:
9595 case ARM::MVE_VPTv4i32:
9596 case ARM::MVE_VPTv16u8:
9597 case ARM::MVE_VPTv8u16:
9598 case ARM::MVE_VPTv4u32:
9599 case ARM::MVE_VPTv16s8:
9600 case ARM::MVE_VPTv8s16:
9601 case ARM::MVE_VPTv4s32:
9602 case ARM::MVE_VPTv4f32:
9603 case ARM::MVE_VPTv8f16:
9604 case ARM::MVE_VPTv16i8r:
9605 case ARM::MVE_VPTv8i16r:
9606 case ARM::MVE_VPTv4i32r:
9607 case ARM::MVE_VPTv16u8r:
9608 case ARM::MVE_VPTv8u16r:
9609 case ARM::MVE_VPTv4u32r:
9610 case ARM::MVE_VPTv16s8r:
9611 case ARM::MVE_VPTv8s16r:
9612 case ARM::MVE_VPTv4s32r:
9613 case ARM::MVE_VPTv4f32r:
9614 case ARM::MVE_VPTv8f16r: {
96159615 assert(!inVPTBlock() && "Nested VPT blocks are not allowed");
96169616 MCOperand &MO = Inst.getOperand(0);
96179617 VPTState.Mask = MO.getImm();
60416041 unsigned Rda = fieldFromInstruction(Insn, 16, 4);
60426042
60436043 switch (Inst.getOpcode()) {
6044 case ARM::t2ASRLr:
6045 case ARM::t2SQRSHRL:
6046 Inst.setOpcode(ARM::t2SQRSHR);
6044 case ARM::MVE_ASRLr:
6045 case ARM::MVE_SQRSHRL:
6046 Inst.setOpcode(ARM::MVE_SQRSHR);
60476047 break;
6048 case ARM::t2LSLLr:
6049 case ARM::t2UQRSHLL:
6050 Inst.setOpcode(ARM::t2UQRSHL);
6048 case ARM::MVE_LSLLr:
6049 case ARM::MVE_UQRSHLL:
6050 Inst.setOpcode(ARM::MVE_UQRSHL);
60516051 break;
60526052 default:
60536053 llvm_unreachable("Unexpected starting opcode!");
386386 }
387387
388388 MachineInstrBuilder MIBuilder =
389 BuildMI(Block, MBIter, dl, TII->get(ARM::t2VPST));
389 BuildMI(Block, MBIter, dl, TII->get(ARM::MVE_VPST));
390390 MachineInstr *LastMI = MI;
391391 MachineBasicBlock::iterator InsertPos = MIBuilder.getInstr();
392392
6060 bb.0.entry:
6161 liveins: $q0, $q1, $q2, $r0
6262
63 ; CHECK: VPST 8, implicit-def $p0
64 ; CHECK-NEXT: $q0 = nnan ninf nsz VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
63 ; CHECK: MVE_VPST 8, implicit-def $p0
64 ; CHECK-NEXT: $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
6565
6666 $vpr = VMSR_P0 killed $r0, 14, $noreg
67 renamable $q0 = nnan ninf nsz VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
67 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
6868 tBX_RET 14, $noreg, implicit $q0
6969
7070 ...