llvm.org GIT mirror llvm / d3df5f3
McARM: Always keep an offset expression, if used (instead of assuming == 0 if used but not present), and simplify logic. Also, clean up various non-sensicalisms in isMemModeRegThumb() and isMemModeImmThumb(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123738 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Dunbar 9 years ago
1 changed file(s) with 29 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
233233 Mem.Writeback || Mem.Negative)
234234 return false;
235235
236 // If there is an offset expression, make sure it's valid.
237 if (!Mem.Offset) return true;
238
239236 const MCConstantExpr *CE = dyn_cast(Mem.Offset);
240237 if (!CE) return false;
241238
244241 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
245242 }
246243 bool isMemModeRegThumb() const {
247 if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
244 if (!isMemory() || !Mem.OffsetIsReg || Mem.Writeback)
248245 return false;
249 return !Mem.Offset || !isa(Mem.Offset);
246 return true;
250247 }
251248 bool isMemModeImmThumb() const {
252 if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
249 if (!isMemory() || Mem.OffsetIsReg || Mem.Writeback)
253250 return false;
254
255 if (!Mem.Offset) return false;
256251
257252 const MCConstantExpr *CE = dyn_cast(Mem.Offset);
258253 if (!CE) return false;
318313
319314 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
320315 // the difference?
321 if (Mem.Offset) {
322 const MCConstantExpr *CE = dyn_cast(Mem.Offset);
323 assert(CE && "Non-constant mode 5 offset operand!");
324
325 // The MCInst offset operand doesn't include the low two bits (like
326 // the instruction encoding).
327 int64_t Offset = CE->getValue() / 4;
328 if (Offset >= 0)
329 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
330 Offset)));
331 else
332 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
333 -Offset)));
334 } else {
335 Inst.addOperand(MCOperand::CreateImm(0));
336 }
316 const MCConstantExpr *CE = dyn_cast(Mem.Offset);
317 assert(CE && "Non-constant mode 5 offset operand!");
318
319 // The MCInst offset operand doesn't include the low two bits (like
320 // the instruction encoding).
321 int64_t Offset = CE->getValue() / 4;
322 if (Offset >= 0)
323 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
324 Offset)));
325 else
326 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
327 -Offset)));
337328 }
338329
339330 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
423414 "OffsetRegNum must imply OffsetIsReg!");
424415 assert((!OffsetRegShifted || OffsetIsReg) &&
425416 "OffsetRegShifted must imply OffsetIsReg!");
417 assert((Offset || OffsetIsReg) &&
418 "Offset must exists unless register offset is used!");
426419 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
427420 "Cannot have shift amount without shifted register offset!");
428421 assert((!Offset || !OffsetIsReg) &&
754747 Parser.Lex(); // Eat exclaim token
755748 }
756749
750 // Force Offset to exist if used.
751 if (!OffsetIsReg) {
752 if (!Offset)
753 Offset = MCConstantExpr::Create(0, getContext());
754 }
755
757756 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
758757 OffsetRegNum, OffsetRegShifted,
759758 ShiftType, ShiftAmount, Preindexed,
794793 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
795794 E))
796795 return true;
796 }
797
798 // Force Offset to exist if used.
799 if (!OffsetIsReg) {
800 if (!Offset)
801 Offset = MCConstantExpr::Create(0, getContext());
797802 }
798803
799804 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,