llvm.org GIT mirror llvm / d36f5af
Set correct <def,undef> flags when lowering REG_SEQUENCE. A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148879 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
3 changed file(s) with 90 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
16451645 }
16461646 }
16471647
1648 // Find the first def of Reg, assuming they are all in the same basic block.
1649 static MachineInstr *findFirstDef(unsigned Reg, MachineRegisterInfo *MRI) {
1650 SmallPtrSet Defs;
1651 MachineInstr *First = 0;
1652 for (MachineRegisterInfo::def_iterator RI = MRI->def_begin(Reg);
1653 MachineInstr *MI = RI.skipInstruction(); Defs.insert(MI))
1654 First = MI;
1655 if (!First)
1656 return 0;
1657
1658 MachineBasicBlock *MBB = First->getParent();
1659 MachineBasicBlock::iterator A = First, B = First;
1660 bool Moving;
1661 do {
1662 Moving = false;
1663 if (A != MBB->begin()) {
1664 Moving = true;
1665 --A;
1666 if (Defs.erase(A)) First = A;
1667 }
1668 if (B != MBB->end()) {
1669 Defs.erase(B);
1670 ++B;
1671 Moving = true;
1672 }
1673 } while (Moving && !Defs.empty());
1674 assert(Defs.empty() && "Instructions outside basic block!");
1675 return First;
1676 }
1677
16481678 /// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are
16491679 /// EXTRACT_SUBREG from the same register and to the same virtual register
16501680 /// with different sub-register indices, attempt to combine the
18731903 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
18741904 }
18751905
1906 // Set flags on the first DstReg def in the basic block.
1907 // It marks the beginning of the live range. All the other defs are
1908 // read-modify-write.
1909 if (MachineInstr *Def = findFirstDef(DstReg, MRI)) {
1910 for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
1911 MachineOperand &MO = Def->getOperand(i);
1912 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
1913 MO.setIsUndef();
1914 }
1915 // Make sure there is a full non-subreg imp-def operand on the
1916 // instruction. This shouldn't be necessary, but it seems that at least
1917 // RAFast requires it.
1918 Def->addRegisterDefined(DstReg, TRI);
1919 DEBUG(dbgs() << "First def: " << *Def);
1920 }
1921
18761922 if (IsImpDef) {
18771923 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
18781924 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1111
1212 ; CHECK: vld1.64 {d16, d17}, [r{{.}}]
1313 ; CHECK-NOT: vld1.64 {d16, d17}
14 ; CHECK: vmov.f64 d19, d16
14 ; CHECK: vmov.f64
1515
1616 define i32 @test(i8* %arg) nounwind {
1717 entry:
0 ; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs -verify-coalescing
1 ; PR11841
2 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
3 target triple = "armv7-none-linux-eabi"
4
5 ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
6 define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 {
7 bb:
8 %tmp = load <2 x float>* undef, align 8, !tbaa !0
9 %tmp2 = extractelement <2 x float> %tmp, i32 0
10 %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0
11 %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1
12 %tmp5 = insertelement <4 x float> %tmp4, float 0.000000e+00, i32 2
13 %tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 3
14 %tmp7 = extractelement <2 x float> %tmp, i32 1
15 %tmp8 = insertelement <4 x float> %tmp3, float %tmp7, i32 1
16 %tmp9 = insertelement <4 x float> %tmp8, float 0.000000e+00, i32 2
17 %tmp10 = insertelement <4 x float> %tmp9, float 0.000000e+00, i32 3
18 %tmp11 = bitcast <4 x float> %tmp6 to <2 x i64>
19 %tmp12 = shufflevector <2 x i64> %tmp11, <2 x i64> undef, <1 x i32> zeroinitializer
20 %tmp13 = bitcast <1 x i64> %tmp12 to <2 x float>
21 %tmp14 = shufflevector <2 x float> %tmp13, <2 x float> undef, <4 x i32> zeroinitializer
22 %tmp15 = bitcast <4 x float> %tmp14 to <2 x i64>
23 %tmp16 = shufflevector <2 x i64> %tmp15, <2 x i64> undef, <1 x i32> zeroinitializer
24 %tmp17 = bitcast <1 x i64> %tmp16 to <2 x float>
25 %tmp18 = extractelement <2 x float> %tmp17, i32 0
26 tail call arm_aapcs_vfpcc void @bar(i8* undef, float %tmp18, float undef, float 0.000000e+00) nounwind
27 %tmp19 = bitcast <4 x float> %tmp10 to <2 x i64>
28 %tmp20 = shufflevector <2 x i64> %tmp19, <2 x i64> undef, <1 x i32> zeroinitializer
29 %tmp21 = bitcast <1 x i64> %tmp20 to <2 x float>
30 %tmp22 = shufflevector <2 x float> %tmp21, <2 x float> undef, <4 x i32>
31 %tmp23 = bitcast <4 x float> %tmp22 to <2 x i64>
32 %tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitializer
33 %tmp25 = bitcast <1 x i64> %tmp24 to <2 x float>
34 %tmp26 = extractelement <2 x float> %tmp25, i32 0
35 tail call arm_aapcs_vfpcc void @bar(i8* undef, float undef, float %tmp26, float 0.000000e+00) nounwind
36 ret void
37 }
38
39 declare arm_aapcs_vfpcc void @bar(i8*, float, float, float)
40
41 !0 = metadata !{metadata !"omnipotent char", metadata !1}
42 !1 = metadata !{metadata !"Simple C/C++ TBAA", null}