llvm.org GIT mirror llvm / d350e47
switch CMOVBE to the multipattern: 21 insertions(+), 53 deletions(-) Moar change coming before I switch the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 10 years ago
4 changed file(s) with 21 addition(s) and 53 deletion(s). Raw diff Collapse all Expand all
15371537 case X86::CMOVB16rr: case X86::CMOVB16rm:
15381538 case X86::CMOVB32rr: case X86::CMOVB32rm:
15391539 case X86::CMOVB64rr: case X86::CMOVB64rm:
1540 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1541 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1542 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1540 case X86::CMOVBErr16: case X86::CMOVBErm16:
1541 case X86::CMOVBErr32: case X86::CMOVBErm32:
1542 case X86::CMOVBErr64: case X86::CMOVBErm64:
15431543 case X86::CMOVE16rr: case X86::CMOVE16rm:
15441544 case X86::CMOVE32rr: case X86::CMOVE32rm:
15451545 case X86::CMOVE64rr: case X86::CMOVE64rm:
4949 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
5050 } // end multiclass
5151
52 //defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
52
53 // Conditional Moves.
54 defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
5355
5456
5557 let Constraints = "$src1 = $dst" in {
107109 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
108110 X86_COND_NE, EFLAGS))]>,
109111 TB;
110 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
111 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
112 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
113 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
114 X86_COND_BE, EFLAGS))]>,
115 TB, OpSize;
116 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
117 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
118 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
119 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
120 X86_COND_BE, EFLAGS))]>,
121 TB;
122112 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
123113 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
124114 "cmova{w}\t{$src2, $dst|$dst, $src2}",
300290 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
301291 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
302292 X86_COND_NE, EFLAGS))]>,
303 TB;
304 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
305 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
306 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
307 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
308 X86_COND_BE, EFLAGS))]>,
309 TB, OpSize;
310 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
311 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
312 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
313 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
314 X86_COND_BE, EFLAGS))]>,
315293 TB;
316294 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
317295 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
522500 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
523501 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
524502 X86_COND_NE, EFLAGS))]>, TB;
525 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
526 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
527 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
528 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
529 X86_COND_BE, EFLAGS))]>, TB;
530503 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
531504 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
532505 "cmova{q}\t{$src2, $dst|$dst, $src2}",
604577 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
605578 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
606579 X86_COND_NE, EFLAGS))]>, TB;
607 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
608 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
609 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
610 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
611 X86_COND_BE, EFLAGS))]>, TB;
612580 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
613581 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
614582 "cmova{q}\t{$src2, $dst|$dst, $src2}",
870870 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
871871 (CMOVA32rm GR32:$src2, addr:$src1)>;
872872 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
873 (CMOVBE16rm GR16:$src2, addr:$src1)>;
873 (CMOVBErm16 GR16:$src2, addr:$src1)>;
874874 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
875 (CMOVBE32rm GR32:$src2, addr:$src1)>;
875 (CMOVBErm32 GR32:$src2, addr:$src1)>;
876876 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
877877 (CMOVGE16rm GR16:$src2, addr:$src1)>;
878878 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
925925 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
926926 (CMOVA64rm GR64:$src2, addr:$src1)>;
927927 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
928 (CMOVBE64rm GR64:$src2, addr:$src1)>;
928 (CMOVBErm64 GR64:$src2, addr:$src1)>;
929929 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
930930 (CMOVGE64rm GR64:$src2, addr:$src1)>;
931931 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
481481 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
482482 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
483483 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
484 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
485 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
486 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
484 { X86::CMOVBErr16, X86::CMOVBErm16, 0 },
485 { X86::CMOVBErr32, X86::CMOVBErm32, 0 },
486 { X86::CMOVBErr64, X86::CMOVBErm64, 0 },
487487 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
488488 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
489489 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
14441444 case X86::CMOVNE16rr:
14451445 case X86::CMOVNE32rr:
14461446 case X86::CMOVNE64rr:
1447 case X86::CMOVBE16rr:
1448 case X86::CMOVBE32rr:
1449 case X86::CMOVBE64rr:
1447 case X86::CMOVBErr16:
1448 case X86::CMOVBErr32:
1449 case X86::CMOVBErr64:
14501450 case X86::CMOVA16rr:
14511451 case X86::CMOVA32rr:
14521452 case X86::CMOVA64rr:
14951495 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
14961496 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
14971497 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1498 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1499 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1500 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1501 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1502 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1503 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1498 case X86::CMOVBErr16: Opc = X86::CMOVA16rr; break;
1499 case X86::CMOVBErr32: Opc = X86::CMOVA32rr; break;
1500 case X86::CMOVBErr64: Opc = X86::CMOVA64rr; break;
1501 case X86::CMOVA16rr: Opc = X86::CMOVBErr16; break;
1502 case X86::CMOVA32rr: Opc = X86::CMOVBErr32; break;
1503 case X86::CMOVA64rr: Opc = X86::CMOVBErr64; break;
15041504 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
15051505 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
15061506 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;