llvm.org GIT mirror llvm / d336de3
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias (movzx/movsx) because they give more information. Revert that part of the patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 8 years ago
29 changed file(s) with 122 addition(s) and 131 deletion(s). Raw diff Collapse all Expand all
15451545 def : InstAlias<"movsd", (MOVSD)>;
15461546
15471547 // movsx aliases
1548 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>;
1549 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>;
1550 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src)>;
1551 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src)>;
1552 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src)>;
1553 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src)>;
1554 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src)>;
1548 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src), 0>;
1549 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src), 0>;
1550 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1551 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1552 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1553 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1554 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
15551555
15561556 // movzx aliases
1557 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8W GR16:$dst, GR8:$src)>;
1558 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8W GR16:$dst, i8mem:$src)>;
1559 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src)>;
1560 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src)>;
1561 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src)>;
1562 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>;
1557 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8W GR16:$dst, GR8:$src), 0>;
1558 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8W GR16:$dst, i8mem:$src), 0>;
1559 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1560 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1561 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1562 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
15631563 // Note: No GR32->GR64 movzx form.
15641564
15651565 // outb %dx -> outb %al, %dx
0 ; RUN: llc < %s -march=x86-64 > %t
11 ; RUN: grep movb %t | count 2
2 ; RUN: grep {movzx} %t
2 ; RUN: grep {movzb\[wl\]} %t
33
44
55 define void @handle_vector_size_attribute() nounwind {
None ; RUN: llc < %s -march=x86 | grep {movsx}
0 ; RUN: llc < %s -march=x86 | grep {movsbl}
11
22 @X = global i32 0 ; [#uses=1]
33
None ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movzbl
11
22 define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {
33 entry:
4 ; CHECK: movzx
5 tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone
6 ret i32 %0
4 tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone
5 ret i32 %0
76 }
87
98 declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
None ; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 > %t1
1 ; RUN: grep movzwl %t1 | count 2
2 ; RUN: grep movzbl %t1 | count 2
3 ; RUN: grep movd %t1 | count 4
14
25 define <4 x i16> @a(i32* %x1) nounwind {
3 ; CHECK: movzx
4 ; CHECK-NEXT: movd
56 %x2 = load i32* %x1
67 %x3 = lshr i32 %x2, 1
78 %x = trunc i32 %x3 to i16
1011 }
1112
1213 define <8 x i16> @b(i32* %x1) nounwind {
13 ; CHECK: movzx
14 ; CHECK-NEXT: movd
1514 %x2 = load i32* %x1
1615 %x3 = lshr i32 %x2, 1
1716 %x = trunc i32 %x3 to i16
2019 }
2120
2221 define <8 x i8> @c(i32* %x1) nounwind {
23 ; CHECK: movzx
24 ; CHECK-NEXT: movd
2522 %x2 = load i32* %x1
2623 %x3 = lshr i32 %x2, 1
2724 %x = trunc i32 %x3 to i8
3027 }
3128
3229 define <16 x i8> @d(i32* %x1) nounwind {
33 ; CHECK: movzx
34 ; CHECK-NEXT: movd
3530 %x2 = load i32* %x1
3631 %x3 = lshr i32 %x2, 1
3732 %x = trunc i32 %x3 to i8
None ; RUN: llc < %s -march=x86-64 | FileCheck %s
0 ; RUN: llc < %s -march=x86-64 | grep movzbl | count 2
11
2 ; Use movzbl (aliased as movzx) to avoid partial-register updates.
2 ; Use movzbl to avoid partial-register updates.
33
44 define i32 @foo(i32 %p, i8 zeroext %x) nounwind {
5 ; CHECK: movzx %dil, %eax
6 ; CHECK: movzx %al, %eax
75 %q = trunc i32 %p to i8
86 %r = udiv i8 %q, %x
97 %s = zext i8 %r to i32
7474 define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) {
7575 ; CHECK: vcomisd
7676 ; CHECK: sete
77 ; CHECK: movzx
77 ; CHECK: movzbl
7878 %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
7979 ret i32 %res
8080 }
8484 define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) {
8585 ; CHECK: vcomisd
8686 ; CHECK: setae
87 ; CHECK: movzx
87 ; CHECK: movzbl
8888 %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
8989 ret i32 %res
9090 }
9494 define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) {
9595 ; CHECK: vcomisd
9696 ; CHECK: seta
97 ; CHECK: movzx
97 ; CHECK: movzbl
9898 %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
9999 ret i32 %res
100100 }
104104 define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) {
105105 ; CHECK: vcomisd
106106 ; CHECK: setbe
107 ; CHECK: movzx
107 ; CHECK: movzbl
108108 %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
109109 ret i32 %res
110110 }
124124 define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) {
125125 ; CHECK: vcomisd
126126 ; CHECK: setne
127 ; CHECK: movzx
127 ; CHECK: movzbl
128128 %res = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
129129 ret i32 %res
130130 }
785785 define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) {
786786 ; CHECK: vucomisd
787787 ; CHECK: sete
788 ; CHECK: movzx
788 ; CHECK: movzbl
789789 %res = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
790790 ret i32 %res
791791 }
795795 define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) {
796796 ; CHECK: vucomisd
797797 ; CHECK: setae
798 ; CHECK: movzx
798 ; CHECK: movzbl
799799 %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
800800 ret i32 %res
801801 }
805805 define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) {
806806 ; CHECK: vucomisd
807807 ; CHECK: seta
808 ; CHECK: movzx
808 ; CHECK: movzbl
809809 %res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
810810 ret i32 %res
811811 }
815815 define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) {
816816 ; CHECK: vucomisd
817817 ; CHECK: setbe
818 ; CHECK: movzx
818 ; CHECK: movzbl
819819 %res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
820820 ret i32 %res
821821 }
834834 define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) {
835835 ; CHECK: vucomisd
836836 ; CHECK: setne
837 ; CHECK: movzx
837 ; CHECK: movzbl
838838 %res = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
839839 ret i32 %res
840840 }
11911191 define i32 @test_x86_sse41_ptestnzc(<4 x float> %a0, <4 x float> %a1) {
11921192 ; CHECK: vptest
11931193 ; CHECK: seta
1194 ; CHECK: movzx
1194 ; CHECK: movzbl
11951195 %res = call i32 @llvm.x86.sse41.ptestnzc(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
11961196 ret i32 %res
11971197 }
12011201 define i32 @test_x86_sse41_ptestz(<4 x float> %a0, <4 x float> %a1) {
12021202 ; CHECK: vptest
12031203 ; CHECK: sete
1204 ; CHECK: movzx
1204 ; CHECK: movzbl
12051205 %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
12061206 ret i32 %res
12071207 }
14131413 define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1) {
14141414 ; CHECK: vcomiss
14151415 ; CHECK: sete
1416 ; CHECK: movzx
1416 ; CHECK: movzbl
14171417 %res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
14181418 ret i32 %res
14191419 }
14231423 define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) {
14241424 ; CHECK: vcomiss
14251425 ; CHECK: setae
1426 ; CHECK: movzx
1426 ; CHECK: movzbl
14271427 %res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
14281428 ret i32 %res
14291429 }
14331433 define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) {
14341434 ; CHECK: vcomiss
14351435 ; CHECK: seta
1436 ; CHECK: movzx
1436 ; CHECK: movzbl
14371437 %res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
14381438 ret i32 %res
14391439 }
14431443 define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) {
14441444 ; CHECK: vcomiss
14451445 ; CHECK: setbe
1446 ; CHECK: movzx
1446 ; CHECK: movzbl
14471447 %res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
14481448 ret i32 %res
14491449 }
14621462 define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1) {
14631463 ; CHECK: vcomiss
14641464 ; CHECK: setne
1465 ; CHECK: movzx
1465 ; CHECK: movzbl
14661466 %res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
14671467 ret i32 %res
14681468 }
16541654 define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1) {
16551655 ; CHECK: vucomiss
16561656 ; CHECK: sete
1657 ; CHECK: movzx
1657 ; CHECK: movzbl
16581658 %res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
16591659 ret i32 %res
16601660 }
16641664 define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) {
16651665 ; CHECK: vucomiss
16661666 ; CHECK: setae
1667 ; CHECK: movzx
1667 ; CHECK: movzbl
16681668 %res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
16691669 ret i32 %res
16701670 }
16741674 define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) {
16751675 ; CHECK: vucomiss
16761676 ; CHECK: seta
1677 ; CHECK: movzx
1677 ; CHECK: movzbl
16781678 %res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
16791679 ret i32 %res
16801680 }
16841684 define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) {
16851685 ; CHECK: vucomiss
16861686 ; CHECK: setbe
1687 ; CHECK: movzx
1687 ; CHECK: movzbl
16881688 %res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
16891689 ret i32 %res
16901690 }
17031703 define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) {
17041704 ; CHECK: vucomiss
17051705 ; CHECK: setne
1706 ; CHECK: movzx
1706 ; CHECK: movzbl
17071707 %res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
17081708 ret i32 %res
17091709 }
21782178 define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) {
21792179 ; CHECK: vptest
21802180 ; CHECK: seta
2181 ; CHECK: movzx
2181 ; CHECK: movzbl
21822182 %res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1) ; [#uses=1]
21832183 ret i32 %res
21842184 }
21882188 define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) {
21892189 ; CHECK: vptest
21902190 ; CHECK: sete
2191 ; CHECK: movzx
2191 ; CHECK: movzbl
21922192 %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1) ; [#uses=1]
21932193 ret i32 %res
21942194 }
24822482 define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) {
24832483 ; CHECK: vtestpd
24842484 ; CHECK: seta
2485 ; CHECK: movzx
2485 ; CHECK: movzbl
24862486 %res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
24872487 ret i32 %res
24882488 }
24922492 define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) {
24932493 ; CHECK: vtestpd
24942494 ; CHECK: seta
2495 ; CHECK: movzx
2495 ; CHECK: movzbl
24962496 %res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1) ; [#uses=1]
24972497 ret i32 %res
24982498 }
25022502 define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) {
25032503 ; CHECK: vtestps
25042504 ; CHECK: seta
2505 ; CHECK: movzx
2505 ; CHECK: movzbl
25062506 %res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
25072507 ret i32 %res
25082508 }
25122512 define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) {
25132513 ; CHECK: vtestps
25142514 ; CHECK: seta
2515 ; CHECK: movzx
2515 ; CHECK: movzbl
25162516 %res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1) ; [#uses=1]
25172517 ret i32 %res
25182518 }
25222522 define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) {
25232523 ; CHECK: vtestpd
25242524 ; CHECK: sete
2525 ; CHECK: movzx
2525 ; CHECK: movzbl
25262526 %res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1]
25272527 ret i32 %res
25282528 }
25322532 define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) {
25332533 ; CHECK: vtestpd
25342534 ; CHECK: sete
2535 ; CHECK: movzx
2535 ; CHECK: movzbl
25362536 %res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1) ; [#uses=1]
25372537 ret i32 %res
25382538 }
25422542 define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) {
25432543 ; CHECK: vtestps
25442544 ; CHECK: sete
2545 ; CHECK: movzx
2545 ; CHECK: movzbl
25462546 %res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x float> %a1) ; [#uses=1]
25472547 ret i32 %res
25482548 }
25522552 define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) {
25532553 ; CHECK: vtestps
25542554 ; CHECK: sete
2555 ; CHECK: movzx
2555 ; CHECK: movzbl
25562556 %res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1) ; [#uses=1]
25572557 ret i32 %res
25582558 }
0 ; RUN: llc < %s -march=x86-64 | FileCheck %s
11
22 ; CHECK: @bar1
3 ; CHECK: movzx
3 ; CHECK: movzbl
44 ; CHECK: callq
55 define void @bar1(i1 zeroext %v1) nounwind ssp {
66 entry:
1010 }
1111
1212 ; CHECK: @bar2
13 ; CHECK-NOT: movzx
13 ; CHECK-NOT: movzbl
1414 ; CHECK: callq
1515 define void @bar2(i8 zeroext %v1) nounwind ssp {
1616 entry:
2121
2222 ; CHECK: @bar3
2323 ; CHECK: callq
24 ; CHECK-NOT: movzx
24 ; CHECK-NOT: movzbl
2525 ; CHECK-NOT: and
2626 ; CHECK: ret
2727 define zeroext i1 @bar3() nounwind ssp {
120120 entry:
121121 ; CHECK: test5:
122122 ; CHECK: setg %al
123 ; CHECK: movzx %al, %eax
123 ; CHECK: movzbl %al, %eax
124124 ; CHECK: orl $-2, %eax
125125 ; CHECK: ret
126126
134134 entry:
135135 ; CHECK: test6:
136136 ; CHECK: setl %al
137 ; CHECK: movzx %al, %eax
137 ; CHECK: movzbl %al, %eax
138138 ; CHECK: leal 4(%rax,%rax,8), %eax
139139 ; CHECK: ret
140140 %0 = load i32* %P, align 4 ; [#uses=1]
3737 ; CHECK: test3:
3838 ; CHECK: testq %rdi, %rdi
3939 ; CHECK: sete %al
40 ; CHECK: movzx %al, %eax
40 ; CHECK: movzbl %al, %eax
4141 ; CHECK: ret
4242 }
4343
4848 ; CHECK: test4:
4949 ; CHECK: testq %rdi, %rdi
5050 ; CHECK: setle %al
51 ; CHECK: movzx %al, %eax
51 ; CHECK: movzbl %al, %eax
5252 ; CHECK: ret
5353 }
5454
1313 ; X32: ret
1414
1515 ; X64: test1:
16 ; X64: movsx %e[[A0:di|cx]], %rax
16 ; X64: movslq %e[[A0:di|cx]], %rax
1717 ; X64: movl (%r[[A1:si|dx]],%rax,4), %eax
1818 ; X64: ret
1919
8080 %v11 = add i64 %B, %v10
8181 ret i64 %v11
8282 ; X64: test5:
83 ; X64: movsx %e[[A1]], %rax
83 ; X64: movslq %e[[A1]], %rax
8484 ; X64-NEXT: movq (%r[[A0]],%rax), %rax
8585 ; X64-NEXT: addq %{{rdx|r8}}, %rax
8686 ; X64-NEXT: ret
None ; RUN: llc < %s -march=x86 | grep {movzx %\[abcd\]h,} | count 7
0 ; RUN: llc < %s -march=x86 | grep {movzbl %\[abcd\]h,} | count 7
11
22 ; Use h-register extract and zero-extend.
33
6969 ; WIN64: movzbl %ch, %eax
7070
7171 ; X86-32: qux64:
72 ; X86-32: movzx %ah, %eax
72 ; X86-32: movzbl %ah, %eax
7373 %t0 = lshr i64 %x, 8
7474 %t1 = and i64 %t0, 255
7575 ret i64 %t1
8484 ; WIN64: movzbl %ch, %eax
8585
8686 ; X86-32: qux32:
87 ; X86-32: movzx %ah, %eax
87 ; X86-32: movzbl %ah, %eax
8888 %t0 = lshr i32 %x, 8
8989 %t1 = and i32 %t0, 255
9090 ret i32 %t1
9999 ; WIN64: movzbl %ch, %eax
100100
101101 ; X86-32: qux16:
102 ; X86-32: movzx %ah, %eax
102 ; X86-32: movzbl %ah, %eax
103103 %t0 = lshr i16 %x, 8
104104 ret i16 %t0
105105 }
0 ; RUN: llc < %s -march=x86 > %t
1 ; RUN: grep {movzx %\[abcd\]h,} %t | count 1
1 ; RUN: grep {movzbl %\[abcd\]h,} %t | count 1
22 ; RUN: grep {shll \$3,} %t | count 1
33
44 ; Use an h register, but don't omit the explicit shift for
0 ; PR2094
1 ; RUN: llc < %s -march=x86-64 | grep movsx
1 ; RUN: llc < %s -march=x86-64 | grep movslq
22 ; RUN: llc < %s -march=x86-64 | grep addps
33 ; RUN: llc < %s -march=x86-64 | grep paddd
44 ; RUN: llc < %s -march=x86-64 | not grep movq
0 ; RUN: llc < %s -march=x86-64 > %t
11 ; RUN: grep and %t | count 6
2 ; RUN: grep movzx %t | count 6
2 ; RUN: grep movzb %t | count 6
33 ; RUN: grep sar %t | count 12
44
55 ; Don't optimize away zext-inreg and sext-inreg on the loop induction
None ; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | FileCheck %s
0 ; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | grep movzbl
11 ; PR3366
22
3 ; CHECK: movzx
43 define void @_ada_c34002a() nounwind {
54 entry:
65 %0 = load i8* null, align 1
66 ; ISel doesn't yet know how to eliminate this extra zero-extend. But until
77 ; it knows how to do so safely, it shouldn;t eliminate it.
88 ; CHECK: movzbl (%rdi), %eax
9 ; CHECK: movzx %ax, %eax
9 ; CHECK: movzwl %ax, %eax
1010
1111 define i64 @_ZL5matchPKtPKhiR9MatchData(i8* %tmp13) nounwind {
1212 entry:
33 entry:
44 ; CHECK: foo:
55 ; CHECK: movzwl 4(%esp), %eax
6 ; CHECK: xorl $21998, %eax
7 ; CHECK: movsx %ax, %eax
6 ; CHECK: xorl $21998, %eax
7 ; CHECK: movswl %ax, %eax
88 %0 = xor i16 %x, 21998
99 ret i16 %0
1010 }
2929 ret i32 0
3030 ; CHECK: test2:
3131 ; CHECK: movnew
32 ; CHECK: movsx
32 ; CHECK: movswl
3333 }
3434
3535 declare i1 @return_false()
77 entry:
88 ; CHECK: t1:
99 ; CHECK: seta %al
10 ; CHECK: movzx %al, %eax
10 ; CHECK: movzbl %al, %eax
1111 ; CHECK: shll $5, %eax
1212 %0 = icmp ugt i16 %x, 26 ; [#uses=1]
1313 %iftmp.1.0 = select i1 %0, i16 32, i16 0 ; [#uses=1]
None ; RUN: llc < %s -march=x86 | grep movzx | count 1
0 ; RUN: llc < %s -march=x86 | grep movzbl | count 1
11 ; rdar://6699246
22
33 define signext i8 @t1(i8* %A) nounwind readnone ssp {
22
33 define i64 @t(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
44 ; CHECK: t:
5 ; CHECK: movsx %e{{.*}}, %rax
5 ; CHECK: movslq %e{{.*}}, %rax
66 ; CHECK: movq %rax
77 ; CHECK: movl %eax
88 %C = add i64 %A, %B
0 ; RUN: llc < %s -march=x86 | grep {movl 8(.esp), %eax}
11 ; RUN: llc < %s -march=x86 | grep {shrl .eax}
2 ; RUN: llc < %s -march=x86 | grep {movsx .ax, .eax}
2 ; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax}
33
44 define i32 @test1(i64 %a) nounwind {
55 %tmp29 = lshr i64 %a, 24 ; [#uses=1]
88 ; CHECK: a:
99 ; CHECK: mull
1010 ; CHECK: seto %al
11 ; CHECK: movzx %al, %eax
11 ; CHECK: movzbl %al, %eax
1212 ; CHECK: ret
1313 }
5656 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
5757 entry:
5858 ; CHECK: shift3a:
59 ; CHECK: movzx
59 ; CHECK: movzwl
6060 ; CHECK: psllw
6161 %shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32>
6262 %shl = shl <8 x i16> %val, %shamt
0 ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
1 ; CHECK: movsx
2 ; CHECK: movsx
1 ; CHECK: movswl
2 ; CHECK: movswl
33
44 ; sign extension v2i32 to v2i16
55
None ; RUN: llc < %s | grep movsx
0 ; RUN: llc < %s | grep movswl
11
22 target datalayout = "e-p:64:64"
33 target triple = "x86_64-apple-darwin8"
680680 // CHECK: encoding: [0x48,0x0f,0xba,0xe2,0x01]
681681
682682 //rdar://8017633
683 // CHECK: movzx %al, %esi
683 // CHECK: movzbl %al, %esi
684684 // CHECK: encoding: [0x0f,0xb6,0xf0]
685685 movzx %al, %esi
686686
687 // CHECK: movzx %al, %rsi
687 // CHECK: movzbq %al, %rsi
688688 // CHECK: encoding: [0x48,0x0f,0xb6,0xf0]
689689 movzx %al, %rsi
690690
691 // CHECK: movsx %al, %ax
691 // CHECK: movsbw %al, %ax
692692 // CHECK: encoding: [0x66,0x0f,0xbe,0xc0]
693 movsx %al, %ax
694
695 // CHECK: movsx %al, %eax
693 movsx %al, %ax
694
695 // CHECK: movsbl %al, %eax
696696 // CHECK: encoding: [0x0f,0xbe,0xc0]
697 movsx %al, %eax
698
699 // CHECK: movsx %ax, %eax
697 movsx %al, %eax
698
699 // CHECK: movswl %ax, %eax
700700 // CHECK: encoding: [0x0f,0xbf,0xc0]
701 movsx %ax, %eax
702
703 // CHECK: movsx %bl, %rax
701 movsx %ax, %eax
702
703 // CHECK: movsbq %bl, %rax
704704 // CHECK: encoding: [0x48,0x0f,0xbe,0xc3]
705 movsx %bl, %rax
706
707 // CHECK: movsx %cx, %rax
705 movsx %bl, %rax
706
707 // CHECK: movswq %cx, %rax
708708 // CHECK: encoding: [0x48,0x0f,0xbf,0xc1]
709 movsx %cx, %rax
710
711 // CHECK: movsx %edi, %rax
709 movsx %cx, %rax
710
711 // CHECK: movslq %edi, %rax
712712 // CHECK: encoding: [0x48,0x63,0xc7]
713 movsx %edi, %rax
714
715 // CHECK: movzx %al, %ax
713 movsx %edi, %rax
714
715 // CHECK: movzbw %al, %ax
716716 // CHECK: encoding: [0x66,0x0f,0xb6,0xc0]
717 movzx %al, %ax
718
719 // CHECK: movzx %al, %eax
717 movzx %al, %ax
718
719 // CHECK: movzbl %al, %eax
720720 // CHECK: encoding: [0x0f,0xb6,0xc0]
721 movzx %al, %eax
722
723 // CHECK: movzx %ax, %eax
721 movzx %al, %eax
722
723 // CHECK: movzwl %ax, %eax
724724 // CHECK: encoding: [0x0f,0xb7,0xc0]
725 movzx %ax, %eax
726
727 // CHECK: movzx %bl, %rax
725 movzx %ax, %eax
726
727 // CHECK: movzbq %bl, %rax
728728 // CHECK: encoding: [0x48,0x0f,0xb6,0xc3]
729 movzx %bl, %rax
730
731 // CHECK: movzx %cx, %rax
729 movzx %bl, %rax
730
731 // CHECK: movzwq %cx, %rax
732732 // CHECK: encoding: [0x48,0x0f,0xb7,0xc1]
733 movzx %cx, %rax
733 movzx %cx, %rax
734734
735735 // CHECK: movsbw (%rax), %ax
736736 // CHECK: encoding: [0x66,0x0f,0xbe,0x00]
737 movsx (%rax), %ax
737 movsx (%rax), %ax
738738
739739 // CHECK: movzbw (%rax), %ax
740740 // CHECK: encoding: [0x66,0x0f,0xb6,0x00]
741 movzx (%rax), %ax
741 movzx (%rax), %ax
742742
743743
744744 // rdar://7873482