llvm.org GIT mirror llvm / d32868d
Thread MCSubtargetInfo through Target::createMCAsmBackend Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend. D20830 threaded an MCSubtargetInfo reference through MCAsmBackend::relaxInstruction, but this isn't the only function that would benefit from access. This patch removes the Triple and CPUString arguments from createMCAsmBackend and replaces them with MCSubtargetInfo. This patch just changes the interface without making any intentional functional changes. Once in, several cleanups are possible: * Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend * Support 16-bit instructions when valid in MipsAsmBackend::writeNopData * Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl * Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221) This change initially exposed PR35686, which has since been resolved in r321026. Differential Revision: https://reviews.llvm.org/D41349 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321692 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 2 years ago
30 changed file(s) with 122 addition(s) and 107 deletion(s). Raw diff Collapse all Expand all
122122 using AsmPrinterCtorTy = AsmPrinter *(*)(
123123 TargetMachine &TM, std::unique_ptr &&Streamer);
124124 using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T,
125 const MCSubtargetInfo &STI,
125126 const MCRegisterInfo &MRI,
126 const Triple &TT, StringRef CPU,
127127 const MCTargetOptions &Options);
128128 using MCAsmParserCtorTy = MCTargetAsmParser *(*)(
129129 const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
382382 /// createMCAsmBackend - Create a target specific assembly parser.
383383 ///
384384 /// \param TheTriple The target triple string.
385 MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
386 StringRef TheTriple, StringRef CPU,
387 const MCTargetOptions &Options)
388 const {
385 MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI,
386 const MCRegisterInfo &MRI,
387 const MCTargetOptions &Options) const {
389388 if (!MCAsmBackendCtorFn)
390389 return nullptr;
391 return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU, Options);
390 return MCAsmBackendCtorFn(*this, STI, MRI, Options);
392391 }
393392
394393 /// createMCAsmParser - Create a target specific assembly parser.
11051104 }
11061105
11071106 private:
1108 static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI,
1109 const Triple &TheTriple, StringRef CPU,
1107 static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI,
1108 const MCRegisterInfo &MRI,
11101109 const MCTargetOptions &Options) {
1111 return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);
1110 return new MCAsmBackendImpl(T, STI, MRI);
11121111 }
11131112 };
11141113
135135 MCE = getTarget().createMCCodeEmitter(MII, MRI, Context);
136136
137137 MCAsmBackend *MAB =
138 getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
139 Options.MCOptions);
138 getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
140139 auto FOut = llvm::make_unique(Out);
141140 MCStreamer *S = getTarget().createAsmStreamer(
142141 Context, std::move(FOut), Options.MCOptions.AsmVerbose,
150149 // emission fails.
151150 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, Context);
152151 MCAsmBackend *MAB =
153 getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
154 Options.MCOptions);
152 getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
155153 if (!MCE || !MAB)
156154 return true;
157155
224222
225223 // Create the code emitter for the target if it exists. If not, .o file
226224 // emission fails.
225 const MCSubtargetInfo &STI = *getMCSubtargetInfo();
227226 const MCRegisterInfo &MRI = *getMCRegisterInfo();
228227 MCCodeEmitter *MCE =
229228 getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
230229 MCAsmBackend *MAB =
231 getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
232 Options.MCOptions);
230 getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
233231 if (!MCE || !MAB)
234232 return true;
235233
236234 const Triple &T = getTargetTriple();
237 const MCSubtargetInfo &STI = *getMCSubtargetInfo();
238235 std::unique_ptr AsmStreamer(getTarget().createMCObjectStreamer(
239236 T, *Ctx, std::unique_ptr(MAB), Out,
240237 std::unique_ptr(MCE), STI, Options.MCOptions.MCRelaxAll,
604604 }
605605
606606 MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
607 const MCSubtargetInfo &STI,
607608 const MCRegisterInfo &MRI,
608 const Triple &TheTriple,
609 StringRef CPU,
610609 const MCTargetOptions &Options) {
610 const Triple &TheTriple = STI.getTargetTriple();
611611 if (TheTriple.isOSBinFormatMachO())
612612 return new DarwinAArch64AsmBackend(T, TheTriple, MRI);
613613
623623 }
624624
625625 MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
626 const MCSubtargetInfo &STI,
626627 const MCRegisterInfo &MRI,
627 const Triple &TheTriple,
628 StringRef CPU,
629628 const MCTargetOptions &Options) {
629 const Triple &TheTriple = STI.getTargetTriple();
630630 assert(TheTriple.isOSBinFormatELF() &&
631631 "Big endian is only supported for ELF targets!");
632632 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
4444 const MCRegisterInfo &MRI,
4545 MCContext &Ctx);
4646 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
47 const MCSubtargetInfo &STI,
4748 const MCRegisterInfo &MRI,
48 const Triple &TT, StringRef CPU,
4949 const MCTargetOptions &Options);
5050 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
51 const MCSubtargetInfo &STI,
5152 const MCRegisterInfo &MRI,
52 const Triple &TT, StringRef CPU,
5353 const MCTargetOptions &Options);
5454
5555 std::unique_ptr
197197 } // end anonymous namespace
198198
199199 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
200 const MCSubtargetInfo &STI,
200201 const MCRegisterInfo &MRI,
201 const Triple &TT, StringRef CPU,
202202 const MCTargetOptions &Options) {
203203 // Use 64-bit ELF for amdgcn
204 return new ELFAMDGPUAsmBackend(T, TT);
205 }
204 return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple());
205 }
4444 const MCRegisterInfo &MRI,
4545 MCContext &Ctx);
4646
47 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
48 const Triple &TT, StringRef CPU,
47 MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
48 const MCSubtargetInfo &STI,
49 const MCRegisterInfo &MRI,
4950 const MCTargetOptions &Options);
5051
5152 std::unique_ptr
11751175 }
11761176
11771177 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
1178 const MCSubtargetInfo &STI,
11781179 const MCRegisterInfo &MRI,
1179 const Triple &TT, StringRef CPU,
11801180 const MCTargetOptions &Options) {
1181 return createARMAsmBackend(T, MRI, TT, CPU, Options, true);
1181 return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
1182 Options, true);
11821183 }
11831184
11841185 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
1186 const MCSubtargetInfo &STI,
11851187 const MCRegisterInfo &MRI,
1186 const Triple &TT, StringRef CPU,
11871188 const MCTargetOptions &Options) {
1188 return createARMAsmBackend(T, MRI, TT, CPU, Options, false);
1189 return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
1190 Options, false);
11891191 }
11901192
11911193 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
1194 const MCSubtargetInfo &STI,
11921195 const MCRegisterInfo &MRI,
1193 const Triple &TT, StringRef CPU,
11941196 const MCTargetOptions &Options) {
1195 return createARMAsmBackend(T, MRI, TT, CPU, Options, true);
1197 return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
1198 Options, true);
11961199 }
11971200
11981201 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
1202 const MCSubtargetInfo &STI,
11991203 const MCRegisterInfo &MRI,
1200 const Triple &TT, StringRef CPU,
12011204 const MCTargetOptions &Options) {
1202 return createARMAsmBackend(T, MRI, TT, CPU, Options, false);
1203 }
1205 return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
1206 Options, false);
1207 }
7272 const MCTargetOptions &Options,
7373 bool IsLittleEndian);
7474
75 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
76 const Triple &TT, StringRef CPU,
75 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
76 const MCRegisterInfo &MRI,
7777 const MCTargetOptions &Options);
7878
79 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
80 const Triple &TT, StringRef CPU,
79 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
80 const MCRegisterInfo &MRI,
8181 const MCTargetOptions &Options);
8282
8383 MCAsmBackend *createThumbLEAsmBackend(const Target &T,
84 const MCSubtargetInfo &STI,
8485 const MCRegisterInfo &MRI,
85 const Triple &TT, StringRef CPU,
8686 const MCTargetOptions &Options);
8787
8888 MCAsmBackend *createThumbBEAsmBackend(const Target &T,
89 const MCSubtargetInfo &STI,
8990 const MCRegisterInfo &MRI,
90 const Triple &TT, StringRef CPU,
9191 const MCTargetOptions &Options);
9292
9393 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
103103 }
104104
105105 MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
106 const MCSubtargetInfo &STI,
106107 const MCRegisterInfo &MRI,
107 const Triple &TT, StringRef CPU,
108 const MCTargetOptions&) {
108 const MCTargetOptions &) {
109109 return new BPFAsmBackend(/*IsLittleEndian=*/true);
110110 }
111111
112112 MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
113 const MCSubtargetInfo &STI,
113114 const MCRegisterInfo &MRI,
114 const Triple &TT, StringRef CPU,
115 const MCTargetOptions&) {
115 const MCTargetOptions &) {
116116 return new BPFAsmBackend(/*IsLittleEndian=*/false);
117117 }
4444 const MCRegisterInfo &MRI,
4545 MCContext &Ctx);
4646
47 MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
48 const Triple &TT, StringRef CPU,
47 MCAsmBackend *createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI,
48 const MCRegisterInfo &MRI,
4949 const MCTargetOptions &Options);
50 MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
51 const Triple &TT, StringRef CPU,
50 MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI,
51 const MCRegisterInfo &MRI,
5252 const MCTargetOptions &Options);
5353
5454 std::unique_ptr createBPFELFObjectWriter(raw_pwrite_stream &OS,
764764
765765 // MCAsmBackend
766766 MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
767 MCRegisterInfo const & /*MRI*/,
768 const Triple &TT, StringRef CPU,
769 const MCTargetOptions &Options) {
767 const MCSubtargetInfo &STI,
768 MCRegisterInfo const & /*MRI*/,
769 const MCTargetOptions &Options) {
770 const Triple &TT = STI.getTargetTriple();
770771 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
771772
772 StringRef CPUString = Hexagon_MC::selectHexagonCPU(CPU);
773 StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU());
773774 return new HexagonAsmBackend(T, TT, OSABI, CPUString);
774775 }
6060 MCContext &MCT);
6161
6262 MCAsmBackend *createHexagonAsmBackend(const Target &T,
63 const MCSubtargetInfo &STI,
6364 const MCRegisterInfo &MRI,
64 const Triple &TT, StringRef CPU,
6565 const MCTargetOptions &Options);
6666
6767 std::unique_ptr
164164 } // namespace
165165
166166 MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T,
167 const MCSubtargetInfo &STI,
167168 const MCRegisterInfo & /*MRI*/,
168 const Triple &TT, StringRef /*CPU*/,
169169 const MCTargetOptions & /*Options*/) {
170 const Triple &TT = STI.getTargetTriple();
170171 if (!TT.isOSBinFormatELF())
171172 llvm_unreachable("OS not supported");
172173
3737 const MCRegisterInfo &MRI,
3838 MCContext &Ctx);
3939
40 MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCRegisterInfo &MRI,
41 const Triple &TheTriple, StringRef CPU,
40 MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI,
41 const MCRegisterInfo &MRI,
4242 const MCTargetOptions &Options);
4343
4444 std::unique_ptr
475475 }
476476
477477 MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
478 const MCSubtargetInfo &STI,
478479 const MCRegisterInfo &MRI,
479 const Triple &TT, StringRef CPU,
480480 const MCTargetOptions &Options) {
481 return new MipsAsmBackend(T, MRI, TT, CPU, Options.ABIName == "n32");
482 }
481 return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
482 Options.ABIName == "n32");
483 }
4444 const MCRegisterInfo &MRI,
4545 MCContext &Ctx);
4646
47 MCAsmBackend *createMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI,
48 const Triple &TT, StringRef CPU,
47 MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,
48 const MCRegisterInfo &MRI,
4949 const MCTargetOptions &Options);
5050
5151 std::unique_ptr
1717 #include "llvm/MC/MCMachObjectWriter.h"
1818 #include "llvm/MC/MCObjectWriter.h"
1919 #include "llvm/MC/MCSectionMachO.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
2021 #include "llvm/MC/MCSymbolELF.h"
2122 #include "llvm/MC/MCValue.h"
2223 #include "llvm/Support/ErrorHandling.h"
230231 } // end anonymous namespace
231232
232233 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
234 const MCSubtargetInfo &STI,
233235 const MCRegisterInfo &MRI,
234 const Triple &TT, StringRef CPU,
235236 const MCTargetOptions &Options) {
237 const Triple &TT = STI.getTargetTriple();
236238 if (TT.isOSDarwin())
237239 return new DarwinPPCAsmBackend(T);
238240
2828 class MCInstrInfo;
2929 class MCObjectWriter;
3030 class MCRegisterInfo;
31 class MCSubtargetInfo;
3132 class MCTargetOptions;
3233 class Target;
3334 class Triple;
4243 const MCRegisterInfo &MRI,
4344 MCContext &Ctx);
4445
45 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
46 const Triple &TT, StringRef CPU,
46 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
47 const MCRegisterInfo &MRI,
4748 const MCTargetOptions &Options);
4849
4950 /// Construct an PPC ELF object writer.
229229 } // end anonymous namespace
230230
231231 MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
232 const MCSubtargetInfo &STI,
232233 const MCRegisterInfo &MRI,
233 const Triple &TT, StringRef CPU,
234234 const MCTargetOptions &Options) {
235 const Triple &TT = STI.getTargetTriple();
235236 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
236237 return new RISCVAsmBackend(OSABI, TT.isArch64Bit());
237238 }
3939 const MCRegisterInfo &MRI,
4040 MCContext &Ctx);
4141
42 MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCRegisterInfo &MRI,
43 const Triple &TT, StringRef CPU,
42 MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
43 const MCRegisterInfo &MRI,
4444 const MCTargetOptions &Options);
4545
4646 std::unique_ptr
1313 #include "llvm/MC/MCExpr.h"
1414 #include "llvm/MC/MCFixupKindInfo.h"
1515 #include "llvm/MC/MCObjectWriter.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
1617 #include "llvm/MC/MCValue.h"
1718 #include "llvm/Support/TargetRegistry.h"
1819
300301 } // end anonymous namespace
301302
302303 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
304 const MCSubtargetInfo &STI,
303305 const MCRegisterInfo &MRI,
304 const Triple &TT, StringRef CPU,
305306 const MCTargetOptions &Options) {
306 return new ELFSparcAsmBackend(T, TT.getOS());
307 return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS());
307308 }
3939 MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
4040 const MCRegisterInfo &MRI,
4141 MCContext &Ctx);
42 MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,
43 const Triple &TT, StringRef CPU,
42 MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI,
43 const MCRegisterInfo &MRI,
4444 const MCTargetOptions &Options);
4545 std::unique_ptr
4646 createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
1313 #include "llvm/MC/MCFixupKindInfo.h"
1414 #include "llvm/MC/MCInst.h"
1515 #include "llvm/MC/MCObjectWriter.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
1617
1718 using namespace llvm;
1819
121122 }
122123
123124 MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
125 const MCSubtargetInfo &STI,
124126 const MCRegisterInfo &MRI,
125 const Triple &TT, StringRef CPU,
126127 const MCTargetOptions &Options) {
127 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
128 uint8_t OSABI =
129 MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
128130 return new SystemZMCAsmBackend(OSABI);
129131 }
8888 MCContext &Ctx);
8989
9090 MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
91 const MCSubtargetInfo &STI,
9192 const MCRegisterInfo &MRI,
92 const Triple &TT, StringRef CPU,
9393 const MCTargetOptions &Options);
9494
9595 std::unique_ptr createSystemZObjectWriter(raw_pwrite_stream &OS,
842842 } // end anonymous namespace
843843
844844 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
845 const MCSubtargetInfo &STI,
845846 const MCRegisterInfo &MRI,
846 const Triple &TheTriple,
847 StringRef CPU,
848847 const MCTargetOptions &Options) {
848 const Triple &TheTriple = STI.getTargetTriple();
849 StringRef CPU = STI.getCPU();
850 llvm::errs() << "create x86-32 backend with CPU: " << CPU << "\n";
849851 if (TheTriple.isOSBinFormatMachO())
850852 return new DarwinX86_32AsmBackend(T, MRI, CPU);
851853
861863 }
862864
863865 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
866 const MCSubtargetInfo &STI,
864867 const MCRegisterInfo &MRI,
865 const Triple &TheTriple,
866 StringRef CPU,
867868 const MCTargetOptions &Options) {
869 const Triple &TheTriple = STI.getTargetTriple();
870 StringRef CPU = STI.getCPU();
868871 if (TheTriple.isOSBinFormatMachO()) {
869872 MachO::CPUSubTypeX86 CS =
870873 StringSwitch(TheTriple.getArchName())
6969 const MCRegisterInfo &MRI,
7070 MCContext &Ctx);
7171
72 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
73 const Triple &TT, StringRef CPU,
72 MCAsmBackend *createX86_32AsmBackend(const Target &T,
73 const MCSubtargetInfo &STI,
74 const MCRegisterInfo &MRI,
7475 const MCTargetOptions &Options);
75 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
76 const Triple &TT, StringRef CPU,
76 MCAsmBackend *createX86_64AsmBackend(const Target &T,
77 const MCSubtargetInfo &STI,
78 const MCRegisterInfo &MRI,
7779 const MCTargetOptions &Options);
7880
7981 /// Implements X86-only directives for assembly emission.
671671 MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
672672 MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, *MC);
673673
674 MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
675 if (!MSTI)
676 return error("no subtarget info for target " + TripleName, Context);
677
674678 MCTargetOptions Options;
675 MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", Options);
679 MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, Options);
676680 if (!MAB)
677681 return error("no asm backend for target " + TripleName, Context);
678682
679683 MII.reset(TheTarget->createMCInstrInfo());
680684 if (!MII)
681685 return error("no instr info info for target " + TripleName, Context);
682
683 MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
684 if (!MSTI)
685 return error("no subtarget info for target " + TripleName, Context);
686686
687687 MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
688688 if (!MCE)
672672 MCContext MC(MAI.get(), MRI.get(), &MOFI);
673673 MOFI.InitMCObjectFileInfo(TheTriple, /*PIC*/ false, MC);
674674
675 MCTargetOptions Options;
676 auto MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", Options);
677 if (!MAB)
678 return error("no asm backend for target " + TripleName, Context);
679
680 std::unique_ptr MII(TheTarget->createMCInstrInfo());
681 if (!MII)
682 return error("no instr info info for target " + TripleName, Context);
683
684675 std::unique_ptr MSTI(
685676 TheTarget->createMCSubtargetInfo(TripleName, "", ""));
686677 if (!MSTI)
687678 return error("no subtarget info for target " + TripleName, Context);
679
680 MCTargetOptions Options;
681 auto MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, Options);
682 if (!MAB)
683 return error("no asm backend for target " + TripleName, Context);
684
685 std::unique_ptr MII(TheTarget->createMCInstrInfo());
686 if (!MII)
687 return error("no instr info info for target " + TripleName, Context);
688688
689689 MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, MC);
690690 if (!MCE)
566566 MCAsmBackend *MAB = nullptr;
567567 if (ShowEncoding) {
568568 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
569 MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU, MCOptions);
569 MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
570570 }
571571 auto FOut = llvm::make_unique(*OS);
572572 Str.reset(TheTarget->createAsmStreamer(
587587 }
588588
589589 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
590 MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU,
591 MCOptions);
590 MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
592591 Str.reset(TheTarget->createMCObjectStreamer(
593592 TheTriple, Ctx, std::unique_ptr(MAB), *OS,
594593 std::unique_ptr(CE), *STI, MCOptions.MCRelaxAll,
151151 MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
152152 MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, *MC);
153153
154 MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
155 if (!MSTI)
156 return make_error("no subtarget info for target " + TripleName,
157 inconvertibleErrorCode());
158
154159 MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
155 MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", MCOptions);
160 MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, MCOptions);
156161 if (!MAB)
157162 return make_error("no asm backend for target " + TripleName,
158163 inconvertibleErrorCode());
161166 if (!MII)
162167 return make_error("no instr info info for target " +
163168 TripleName,
164 inconvertibleErrorCode());
165
166 MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
167 if (!MSTI)
168 return make_error("no subtarget info for target " + TripleName,
169169 inconvertibleErrorCode());
170170
171171 MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);