llvm.org GIT mirror llvm / d30a98e
Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8 Johnny Chen 9 years ago
33 changed file(s) with 9192 addition(s) and 171 deletion(s). Raw diff Collapse all Expand all
16121612 $(ObjDir)/%GenIntrinsics.inc.tmp : %.td $(ObjDir)/.dir
16131613 $(Echo) "Building $(
16141614 $(Verb) $(TableGen) -gen-tgt-intrinsic -o $(call SYSPATH, $@) $<
1615
1616 $(ObjDir)/ARMDisassemblerTables.inc.tmp : ARM.td $(ObjDir)/.dir
1617 $(Echo) "Building ARM disassembly tables with tblgen"
1618 $(Verb) $(TableGen) -gen-risc-disassembler -o $(call SYSPATH, $@) $<
1619
16151620
16161621 clean-local::
16171622 -$(Verb) $(RM) -f $(INCFiles)
3434 add = '+', sub = '-'
3535 };
3636
37 static inline const char *getAddrOpcStr(AddrOpc Op) {
38 return Op == sub ? "-" : "";
39 }
40
3741 static inline const char *getShiftOpcStr(ShiftOpc Op) {
3842 switch (Op) {
3943 default: assert(0 && "Unknown shift opc!");
126130 return (Imm >> 8) * 2;
127131 }
128132
133 /// getSOImmValOneRotate - Try to handle Imm with an immediate shifter
134 /// operand, computing the rotate amount to use. If this immediate value
135 /// cannot be handled with a single shifter-op, return 0.
136 static inline unsigned getSOImmValOneRotate(unsigned Imm) {
137 // A5.2.4 Constants with multiple encodings
138 // The lowest unsigned value of rotation wins!
139 for (unsigned R = 1; R <= 15; ++R)
140 if ((Imm & rotr32(~255U, 2*R)) == 0)
141 return 2*R;
142
143 // Failed to find a suitable rotate amount.
144 return 0;
145 }
146
129147 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
130148 /// computing the rotate amount to use. If this immediate value cannot be
131149 /// handled with a single shifter-op, determine a good rotate amount that will
178196 // of zero.
179197 if ((Arg & ~255U) == 0) return Arg;
180198
181 unsigned RotAmt = getSOImmValRotate(Arg);
199 unsigned RotAmt = getSOImmValOneRotate(Arg);
182200
183201 // If this cannot be handled with a single shifter_op, bail out.
184202 if (rotr32(~255U, RotAmt) & Arg)
14631463 // ARM NEON Instruction templates.
14641464 //
14651465
1466 // NSFormat specifies further details of a NEON instruction. This is used by
1467 // the disassembler to classify NEONFrm instructions for disassembly purpose.
1468 class NSFormat val> {
1469 bits<5> Value = val;
1470 }
1471 def NSFormatNone : NSFormat<0>;
1472 def VLDSTLaneFrm : NSFormat<1>;
1473 def VLDSTLaneDblFrm : NSFormat<2>;
1474 def VLDSTRQFrm : NSFormat<3>;
1475 def NVdImmFrm : NSFormat<4>;
1476 def NVdVmImmFrm : NSFormat<5>;
1477 def NVdVmImmVCVTFrm : NSFormat<6>;
1478 def NVdVmImmVDupLaneFrm : NSFormat<7>;
1479 def NVdVmImmVSHLLFrm : NSFormat<8>;
1480 def NVectorShuffleFrm : NSFormat<9>;
1481 def NVectorShiftFrm : NSFormat<10>;
1482 def NVectorShift2Frm : NSFormat<11>;
1483 def NVdVnVmImmFrm : NSFormat<12>;
1484 def NVdVnVmImmVectorShiftFrm : NSFormat<13>;
1485 def NVdVnVmImmVectorExtractFrm : NSFormat<14>;
1486 def NVdVnVmImmMulScalarFrm : NSFormat<15>;
1487 def VTBLFrm : NSFormat<16>;
1488
14661489 class NeonI
14671490 string opc, string dt, string asm, string cstr, list pattern>
14681491 : InstARM {
14731496 !strconcat("\t", asm));
14741497 let Pattern = pattern;
14751498 list Predicates = [HasNEON];
1499 NSFormat NSF = NSFormatNone; // For disassembly.
1500 bits<5> NSForm = NSFormatNone.Value; // For disassembly.
14761501 }
14771502
14781503 // Same as NeonI except it does not have a "data type" specifier.
14841509 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm));
14851510 let Pattern = pattern;
14861511 list Predicates = [HasNEON];
1512 NSFormat NSF = NSFormatNone; // For disassembly.
1513 bits<5> NSForm = NSFormatNone.Value; // For disassembly.
14871514 }
14881515
14891516 class NI
14961523 string asm, list pattern>
14971524 : NeonXI
14981525 pattern> {
1526 let NSF = VLDSTRQFrm; // For disassembly.
1527 let NSForm = VLDSTRQFrm.Value; // For disassembly.
14991528 }
15001529
15011530 class NLdSt op21_20, bits<4> op11_8, bits<4> op7_4,
15081537 let Inst{21-20} = op21_20;
15091538 let Inst{11-8} = op11_8;
15101539 let Inst{7-4} = op7_4;
1540 let NSF = VLDSTLaneFrm; // For disassembly.
1541 let NSForm = VLDSTLaneFrm.Value; // For disassembly.
15111542 }
15121543
15131544 class NDataI
15371568 let Inst{6} = op6;
15381569 let Inst{5} = op5;
15391570 let Inst{4} = op4;
1571 let NSF = NVdImmFrm; // For disassembly.
1572 let NSForm = NVdImmFrm.Value; // For disassembly.
15401573 }
15411574
15421575 // NEON 2 vector register format.
15521585 let Inst{11-7} = op11_7;
15531586 let Inst{6} = op6;
15541587 let Inst{4} = op4;
1588 let NSF = NVdVmImmFrm; // For disassembly.
1589 let NSForm = NVdVmImmFrm.Value; // For disassembly.
15551590 }
15561591
15571592 // Same as N2V except it doesn't have a datatype suffix.
15671602 let Inst{11-7} = op11_7;
15681603 let Inst{6} = op6;
15691604 let Inst{4} = op4;
1605 let NSF = NVdVmImmFrm; // For disassembly.
1606 let NSForm = NVdVmImmFrm.Value; // For disassembly.
15701607 }
15711608
15721609 // NEON 2 vector register with immediate.
15801617 let Inst{7} = op7;
15811618 let Inst{6} = op6;
15821619 let Inst{4} = op4;
1620 let NSF = NVdVmImmFrm; // For disassembly.
1621 let NSForm = NVdVmImmFrm.Value; // For disassembly.
15831622 }
15841623
15851624 // NEON 3 vector register format.
15931632 let Inst{11-8} = op11_8;
15941633 let Inst{6} = op6;
15951634 let Inst{4} = op4;
1635 let NSF = NVdVnVmImmFrm; // For disassembly.
1636 let NSForm = NVdVnVmImmFrm.Value; // For disassembly.
15961637 }
15971638
15981639 // Same as N3VX except it doesn't have a data type suffix.
16061647 let Inst{11-8} = op11_8;
16071648 let Inst{6} = op6;
16081649 let Inst{4} = op4;
1650 let NSF = NVdVnVmImmFrm; // For disassembly.
1651 let NSForm = NVdVnVmImmFrm.Value; // For disassembly.
16091652 }
16101653
16111654 // NEON VMOVs between scalar and core registers.
212212 class VLD2Ddbl op7_4, string OpcodeStr, string Dt>
213213 : NLdSt<0,0b10,0b1001,op7_4, (outs DPR:$dst1, DPR:$dst2),
214214 (ins addrmode6:$addr), IIC_VLD2,
215 OpcodeStr, Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
215 OpcodeStr, Dt, "\\{$dst1, $dst2\\}, $addr", "", []> {
216 let NSF = VLDSTLaneDblFrm; // For disassembly.
217 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
218 }
216219
217220 def VLD2d8D : VLD2Ddbl<0b0000, "vld2", "8">;
218221 def VLD2d16D : VLD2Ddbl<0b0100, "vld2", "16">;
227230 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
228231 (ins addrmode6:$addr), IIC_VLD3,
229232 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3\\}, $addr",
230 "$addr.addr = $wb", []>;
233 "$addr.addr = $wb", []> {
234 let NSF = VLDSTLaneDblFrm; // For disassembly.
235 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
236 }
231237
232238 def VLD3d8 : VLD3D<0b0000, "vld3", "8">;
233239 def VLD3d16 : VLD3D<0b0100, "vld3", "16">;
259265 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
260266 (ins addrmode6:$addr), IIC_VLD4,
261267 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
262 "$addr.addr = $wb", []>;
268 "$addr.addr = $wb", []> {
269 let NSF = VLDSTLaneDblFrm; // For disassembly.
270 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
271 }
263272
264273 def VLD4d8 : VLD4D<0b0000, "vld4", "8">;
265274 def VLD4d16 : VLD4D<0b0100, "vld4", "16">;
296305 def VLD2LNd32 : VLD2LN<0b1001, "vld2", "32"> { let Inst{6} = 0; }
297306
298307 // vld2 to double-spaced even registers.
299 def VLD2LNq16a: VLD2LN<0b0101, "vld2", "16"> { let Inst{5} = 1; }
300 def VLD2LNq32a: VLD2LN<0b1001, "vld2", "32"> { let Inst{6} = 1; }
308 def VLD2LNq16a: VLD2LN<0b0101, "vld2", "16"> {
309 let Inst{5} = 1;
310 let NSF = VLDSTLaneDblFrm; // For disassembly.
311 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
312 }
313 def VLD2LNq32a: VLD2LN<0b1001, "vld2", "32"> {
314 let Inst{6} = 1;
315 let NSF = VLDSTLaneDblFrm; // For disassembly.
316 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
317 }
301318
302319 // vld2 to double-spaced odd registers.
303 def VLD2LNq16b: VLD2LN<0b0101, "vld2", "16"> { let Inst{5} = 1; }
304 def VLD2LNq32b: VLD2LN<0b1001, "vld2", "32"> { let Inst{6} = 1; }
320 def VLD2LNq16b: VLD2LN<0b0101, "vld2", "16"> {
321 let Inst{5} = 1;
322 let NSF = VLDSTLaneDblFrm; // For disassembly.
323 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
324 }
325 def VLD2LNq32b: VLD2LN<0b1001, "vld2", "32"> {
326 let Inst{6} = 1;
327 let NSF = VLDSTLaneDblFrm; // For disassembly.
328 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
329 }
305330
306331 // VLD3LN : Vector Load (single 3-element structure to one lane)
307332 class VLD3LN op11_8, string OpcodeStr, string Dt>
317342 def VLD3LNd32 : VLD3LN<0b1010, "vld3", "32"> { let Inst{6-4} = 0b000; }
318343
319344 // vld3 to double-spaced even registers.
320 def VLD3LNq16a: VLD3LN<0b0110, "vld3", "16"> { let Inst{5-4} = 0b10; }
345 def VLD3LNq16a: VLD3LN<0b0110, "vld3", "16"> {
346 let Inst{5-4} = 0b10;
347 let NSF = VLDSTLaneDblFrm; // For disassembly.
348 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
349 }
321350 def VLD3LNq32a: VLD3LN<0b1010, "vld3", "32"> { let Inst{6-4} = 0b100; }
322351
323352 // vld3 to double-spaced odd registers.
339368 def VLD4LNd32 : VLD4LN<0b1011, "vld4", "32"> { let Inst{6} = 0; }
340369
341370 // vld4 to double-spaced even registers.
342 def VLD4LNq16a: VLD4LN<0b0111, "vld4", "16"> { let Inst{5} = 1; }
343 def VLD4LNq32a: VLD4LN<0b1011, "vld4", "32"> { let Inst{6} = 1; }
371 def VLD4LNq16a: VLD4LN<0b0111, "vld4", "16"> {
372 let Inst{5} = 1;
373 let NSF = VLDSTLaneDblFrm; // For disassembly.
374 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
375 }
376 def VLD4LNq32a: VLD4LN<0b1011, "vld4", "32"> {
377 let Inst{6} = 1;
378 let NSF = VLDSTLaneDblFrm; // For disassembly.
379 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
380 }
344381
345382 // vld4 to double-spaced odd registers.
346 def VLD4LNq16b: VLD4LN<0b0111, "vld4", "16"> { let Inst{5} = 1; }
347 def VLD4LNq32b: VLD4LN<0b1011, "vld4", "32"> { let Inst{6} = 1; }
383 def VLD4LNq16b: VLD4LN<0b0111, "vld4", "16"> {
384 let Inst{5} = 1;
385 let NSF = VLDSTLaneDblFrm; // For disassembly.
386 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
387 }
388 def VLD4LNq32b: VLD4LN<0b1011, "vld4", "32"> {
389 let Inst{6} = 1;
390 let NSF = VLDSTLaneDblFrm; // For disassembly.
391 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
392 }
348393
349394 // VLD1DUP : Vector Load (single element to all lanes)
350395 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
432477 class VST2Ddbl op7_4, string OpcodeStr, string Dt>
433478 : NLdSt<0, 0b00, 0b1001, op7_4, (outs),
434479 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
435 OpcodeStr, Dt, "\\{$src1, $src2\\}, $addr", "", []>;
480 OpcodeStr, Dt, "\\{$src1, $src2\\}, $addr", "", []> {
481 let NSF = VLDSTLaneDblFrm; // For disassembly.
482 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
483 }
436484
437485 def VST2d8D : VST2Ddbl<0b0000, "vst2", "8">;
438486 def VST2d16D : VST2Ddbl<0b0100, "vst2", "16">;
447495 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
448496 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
449497 OpcodeStr, Dt, "\\{$src1, $src2, $src3\\}, $addr",
450 "$addr.addr = $wb", []>;
498 "$addr.addr = $wb", []> {
499 let NSF = VLDSTLaneDblFrm; // For disassembly.
500 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
501 }
451502
452503 def VST3d8 : VST3D<0b0000, "vst3", "8">;
453504 def VST3d16 : VST3D<0b0100, "vst3", "16">;
477528 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
478529 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
479530 IIC_VST, OpcodeStr, Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
480 "$addr.addr = $wb", []>;
531 "$addr.addr = $wb", []> {
532 let NSF = VLDSTLaneDblFrm; // For disassembly.
533 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
534 }
481535
482536 def VST4d8 : VST4D<0b0000, "vst4", "8">;
483537 def VST4d16 : VST4D<0b0100, "vst4", "16">;
514568 def VST2LNd32 : VST2LN<0b1001, "vst2", "32"> { let Inst{6} = 0; }
515569
516570 // vst2 to double-spaced even registers.
517 def VST2LNq16a: VST2LN<0b0101, "vst2", "16"> { let Inst{5} = 1; }
518 def VST2LNq32a: VST2LN<0b1001, "vst2", "32"> { let Inst{6} = 1; }
571 def VST2LNq16a: VST2LN<0b0101, "vst2", "16"> {
572 let Inst{5} = 1;
573 let NSF = VLDSTLaneDblFrm; // For disassembly.
574 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
575 }
576 def VST2LNq32a: VST2LN<0b1001, "vst2", "32"> {
577 let Inst{6} = 1;
578 let NSF = VLDSTLaneDblFrm; // For disassembly.
579 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
580 }
519581
520582 // vst2 to double-spaced odd registers.
521 def VST2LNq16b: VST2LN<0b0101, "vst2", "16"> { let Inst{5} = 1; }
522 def VST2LNq32b: VST2LN<0b1001, "vst2", "32"> { let Inst{6} = 1; }
583 def VST2LNq16b: VST2LN<0b0101, "vst2", "16"> {
584 let Inst{5} = 1;
585 let NSF = VLDSTLaneDblFrm; // For disassembly.
586 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
587 }
588 def VST2LNq32b: VST2LN<0b1001, "vst2", "32"> {
589 let Inst{6} = 1;
590 let NSF = VLDSTLaneDblFrm; // For disassembly.
591 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
592 }
523593
524594 // VST3LN : Vector Store (single 3-element structure from one lane)
525595 class VST3LN op11_8, string OpcodeStr, string Dt>
534604 def VST3LNd32 : VST3LN<0b1010, "vst3", "32"> { let Inst{6-4} = 0b000; }
535605
536606 // vst3 to double-spaced even registers.
537 def VST3LNq16a: VST3LN<0b0110, "vst3", "16"> { let Inst{5-4} = 0b10; }
538 def VST3LNq32a: VST3LN<0b1010, "vst3", "32"> { let Inst{6-4} = 0b100; }
607 def VST3LNq16a: VST3LN<0b0110, "vst3", "16"> {
608 let Inst{5-4} = 0b10;
609 let NSF = VLDSTLaneDblFrm; // For disassembly.
610 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
611 }
612 def VST3LNq32a: VST3LN<0b1010, "vst3", "32"> {
613 let Inst{6-4} = 0b100;
614 let NSF = VLDSTLaneDblFrm; // For disassembly.
615 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
616 }
539617
540618 // vst3 to double-spaced odd registers.
541 def VST3LNq16b: VST3LN<0b0110, "vst3", "16"> { let Inst{5-4} = 0b10; }
542 def VST3LNq32b: VST3LN<0b1010, "vst3", "32"> { let Inst{6-4} = 0b100; }
619 def VST3LNq16b: VST3LN<0b0110, "vst3", "16"> {
620 let Inst{5-4} = 0b10;
621 let NSF = VLDSTLaneDblFrm; // For disassembly.
622 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
623 }
624 def VST3LNq32b: VST3LN<0b1010, "vst3", "32"> {
625 let Inst{6-4} = 0b100;
626 let NSF = VLDSTLaneDblFrm; // For disassembly.
627 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
628 }
543629
544630 // VST4LN : Vector Store (single 4-element structure from one lane)
545631 class VST4LN op11_8, string OpcodeStr, string Dt>
555641 def VST4LNd32 : VST4LN<0b1011, "vst4", "32"> { let Inst{6} = 0; }
556642
557643 // vst4 to double-spaced even registers.
558 def VST4LNq16a: VST4LN<0b0111, "vst4", "16"> { let Inst{5} = 1; }
559 def VST4LNq32a: VST4LN<0b1011, "vst4", "32"> { let Inst{6} = 1; }
644 def VST4LNq16a: VST4LN<0b0111, "vst4", "16"> {
645 let Inst{5} = 1;
646 let NSF = VLDSTLaneDblFrm; // For disassembly.
647 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
648 }
649 def VST4LNq32a: VST4LN<0b1011, "vst4", "32"> {
650 let Inst{6} = 1;
651 let NSF = VLDSTLaneDblFrm; // For disassembly.
652 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
653 }
560654
561655 // vst4 to double-spaced odd registers.
562 def VST4LNq16b: VST4LN<0b0111, "vst4", "16"> { let Inst{5} = 1; }
563 def VST4LNq32b: VST4LN<0b1011, "vst4", "32"> { let Inst{6} = 1; }
656 def VST4LNq16b: VST4LN<0b0111, "vst4", "16"> {
657 let Inst{5} = 1;
658 let NSF = VLDSTLaneDblFrm; // For disassembly.
659 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
660 }
661 def VST4LNq32b: VST4LN<0b1011, "vst4", "32"> {
662 let Inst{6} = 1;
663 let NSF = VLDSTLaneDblFrm; // For disassembly.
664 let NSForm = VLDSTLaneDblFrm.Value; // For disassembly.
665 }
564666
565667 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
566668
667769 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
668770 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
669771 OpcodeStr, Dt, "$dst1, $dst2",
670 "$src1 = $dst1, $src2 = $dst2", []>;
772 "$src1 = $dst1, $src2 = $dst2", []> {
773 let NSF = NVectorShuffleFrm; // For disassembly.
774 let NSForm = NVectorShuffleFrm.Value; // For disassembly.
775 }
671776 class N2VQShuffle op19_18, bits<5> op11_7,
672777 InstrItinClass itin, string OpcodeStr, string Dt>
673778 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
674779 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
675 "$src1 = $dst1, $src2 = $dst2", []>;
780 "$src1 = $dst1, $src2 = $dst2", []> {
781 let NSF = NVectorShuffleFrm; // For disassembly.
782 let NSForm = NVectorShuffleFrm.Value; // For disassembly.
783 }
676784
677785 // Basic 3-register operations: single-, double- and quad-register.
678786 class N3VS op21_20, bits<4> op11_8, bit op4,
714822 (Ty (ShOp (Ty DPR:$src1),
715823 (Ty (NEONvduplane (Ty DPR_VFP2:$src2), imm:$lane)))))]>{
716824 let isCommutable = 0;
825 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
826 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
717827 }
718828 class N3VDSL16 op21_20, bits<4> op11_8,
719829 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
724834 (Ty (ShOp (Ty DPR:$src1),
725835 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
726836 let isCommutable = 0;
837 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
838 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
727839 }
728840
729841 class N3VQ op21_20, bits<4> op11_8, bit op4,
755867 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
756868 imm:$lane)))))]> {
757869 let isCommutable = 0;
870 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
871 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
758872 }
759873 class N3VQSL16 op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
760874 ValueType ResTy, ValueType OpTy, SDNode ShOp>
766880 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
767881 imm:$lane)))))]> {
768882 let isCommutable = 0;
883 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
884 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
769885 }
770886
771887 // Basic 3-register intrinsics, both double- and quad-register.
788904 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
789905 imm:$lane)))))]> {
790906 let isCommutable = 0;
907 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
908 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
791909 }
792910 class N3VDIntSL16 op21_20, bits<4> op11_8, InstrItinClass itin,
793911 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
799917 (Ty (NEONvduplane (Ty DPR_8:$src2),
800918 imm:$lane)))))]> {
801919 let isCommutable = 0;
920 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
921 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
802922 }
803923
804924 class N3VQInt op21_20, bits<4> op11_8, bit op4,
821941 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
822942 imm:$lane)))))]> {
823943 let isCommutable = 0;
944 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
945 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
824946 }
825947 class N3VQIntSL16 op21_20, bits<4> op11_8, InstrItinClass itin,
826948 string OpcodeStr, string Dt,
833955 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
834956 imm:$lane)))))]> {
835957 let isCommutable = 0;
958 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
959 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
836960 }
837961
838962 // Multiply-Add/Sub operations: single-, double- and quad-register.
863987 (Ty (ShOp (Ty DPR:$src1),
864988 (Ty (MulOp DPR:$src2,
865989 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
866 imm:$lane)))))))]>;
990 imm:$lane)))))))]> {
991 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
992 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
993 }
867994 class N3VDMulOpSL16 op21_20, bits<4> op11_8, InstrItinClass itin,
868995 string OpcodeStr, string Dt,
869996 ValueType Ty, SDNode MulOp, SDNode ShOp>
8751002 (Ty (ShOp (Ty DPR:$src1),
8761003 (Ty (MulOp DPR:$src2,
8771004 (Ty (NEONvduplane (Ty DPR_8:$src3),
878 imm:$lane)))))))]>;
1005 imm:$lane)))))))]> {
1006 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
1007 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
1008 }
8791009
8801010 class N3VQMulOp op21_20, bits<4> op11_8, bit op4,
8811011 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
8961026 (ResTy (ShOp (ResTy QPR:$src1),
8971027 (ResTy (MulOp QPR:$src2,
8981028 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
899 imm:$lane)))))))]>;
1029 imm:$lane)))))))]> {
1030 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
1031 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
1032 }
9001033 class N3VQMulOpSL16 op21_20, bits<4> op11_8, InstrItinClass itin,
9011034 string OpcodeStr, string Dt,
9021035 ValueType ResTy, ValueType OpTy,
9091042 (ResTy (ShOp (ResTy QPR:$src1),
9101043 (ResTy (MulOp QPR:$src2,
9111044 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
912 imm:$lane)))))))]>;
1045 imm:$lane)))))))]> {
1046 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
1047 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
1048 }
9131049
9141050 // Neon 3-argument intrinsics, both double- and quad-register.
9151051 // The destination register is also used as the first source operand register.
9951131 [(set (ResTy QPR:$dst),
9961132 (ResTy (IntOp (OpTy DPR:$src1),
9971133 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
998 imm:$lane)))))]>;
1134 imm:$lane)))))]> {
1135 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
1136 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
1137 }
9991138 class N3VLIntSL16 op21_20, bits<4> op11_8,
10001139 InstrItinClass itin, string OpcodeStr, string Dt,
10011140 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
10051144 [(set (ResTy QPR:$dst),
10061145 (ResTy (IntOp (OpTy DPR:$src1),
10071146 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1008 imm:$lane)))))]>;
1147 imm:$lane)))))]> {
1148 let NSF = NVdVnVmImmMulScalarFrm; // For disassembly.
1149 let NSForm = NVdVnVmImmMulScalarFrm.Value; // For disassembly.
1150 }
10091151
10101152 // Wide 3-register intrinsics.
10111153 class N3VWInt op21_20, bits<4> op11_8, bit op4,
10541196 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
10551197 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
10561198
1199 // This is a big let * in block to mark these instructions NVectorShiftFrm to
1200 // help the disassembler.
1201 let NSF = NVectorShiftFrm, NSForm = NVectorShiftFrm.Value in {
1202
10571203 // Shift by immediate,
10581204 // both double- and quad-register.
10591205 class N2VDSh op11_8, bit op7, bit op4,
10711217 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
10721218 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
10731219
1074 // Long shift by immediate.
1075 class N2VLSh op11_8, bit op7, bit op6, bit op4,
1076 string OpcodeStr, string Dt,
1077 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1078 : N2VImm
1079 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1080 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1081 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1082 (i32 imm:$SIMM))))]>;
1083
10841220 // Narrow shift by immediate.
10851221 class N2VNSh op11_8, bit op7, bit op6, bit op4,
10861222 InstrItinClass itin, string OpcodeStr, string Dt,
11231259 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
11241260 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
11251261
1262 } // End of "let NSF = NVectorShiftFrm, ..."
1263
1264 // Long shift by immediate.
1265 class N2VLSh op11_8, bit op7, bit op6, bit op4,
1266 string OpcodeStr, string Dt,
1267 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1268 : N2VImm
1269 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1270 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1271 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1272 (i32 imm:$SIMM))))]> {
1273 // This has a different interpretation of the shift amount encoding than
1274 // NVectorShiftFrm.
1275 let NSF = NVectorShift2Frm; // For disassembly.
1276 let NSForm = NVectorShift2Frm.Value; // For disassembly.
1277 }
1278
11261279 // Convert, with fractional bits immediate,
11271280 // both double- and quad-register.
1281 let NSF = NVdVmImmVCVTFrm, NSForm = NVdVmImmVCVTFrm.Value in {
11281282 class N2VCvtD op11_8, bit op7, bit op4,
11291283 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
11301284 Intrinsic IntOp>
11391293 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
11401294 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
11411295 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1296 }
11421297
11431298 //===----------------------------------------------------------------------===//
11441299 // Multiclasses
13491504 v2i64, v2i64, IntOp, Commutable>;
13501505 }
13511506
1507 // Same as N3VInt_QHSD, except they're for Vector Shift (Register) Instructions.
1508 // D:Vd M:Vm N:Vn (notice that M:Vm is the first operand)
1509 // This helps the disassembler.
1510 let NSF = NVdVnVmImmVectorShiftFrm, NSForm = NVdVnVmImmVectorShiftFrm.Value in {
1511 multiclass N3VInt_HS2 op11_8, bit op4,
1512 InstrItinClass itinD16, InstrItinClass itinD32,
1513 InstrItinClass itinQ16, InstrItinClass itinQ32,
1514 string OpcodeStr, string Dt,
1515 Intrinsic IntOp, bit Commutable = 0> {
1516 // 64-bit vector types.
1517 def v4i16 : N3VDInt
1518 OpcodeStr, !strconcat(Dt, "16"),
1519 v4i16, v4i16, IntOp, Commutable>;
1520 def v2i32 : N3VDInt
1521 OpcodeStr, !strconcat(Dt, "32"),
1522 v2i32, v2i32, IntOp, Commutable>;
1523
1524 // 128-bit vector types.
1525 def v8i16 : N3VQInt
1526 OpcodeStr, !strconcat(Dt, "16"),
1527 v8i16, v8i16, IntOp, Commutable>;
1528 def v4i32 : N3VQInt
1529 OpcodeStr, !strconcat(Dt, "32"),
1530 v4i32, v4i32, IntOp, Commutable>;
1531 }
1532 multiclass N3VInt_QHS2 op11_8, bit op4,
1533 InstrItinClass itinD16, InstrItinClass itinD32,
1534 InstrItinClass itinQ16, InstrItinClass itinQ32,
1535 string OpcodeStr, string Dt,
1536 Intrinsic IntOp, bit Commutable = 0>
1537 : N3VInt_HS2
1538 OpcodeStr, Dt, IntOp, Commutable> {
1539 def v8i8 : N3VDInt
1540 OpcodeStr, !strconcat(Dt, "8"),
1541 v8i8, v8i8, IntOp, Commutable>;
1542 def v16i8 : N3VQInt
1543 OpcodeStr, !strconcat(Dt, "8"),
1544 v16i8, v16i8, IntOp, Commutable>;
1545 }
1546 multiclass N3VInt_QHSD2 op11_8, bit op4,
1547 InstrItinClass itinD16, InstrItinClass itinD32,
1548 InstrItinClass itinQ16, InstrItinClass itinQ32,
1549 string OpcodeStr, string Dt,
1550 Intrinsic IntOp, bit Commutable = 0>
1551 : N3VInt_QHS2
1552 OpcodeStr, Dt, IntOp, Commutable> {
1553 def v1i64 : N3VDInt
1554 OpcodeStr, !strconcat(Dt, "64"),
1555 v1i64, v1i64, IntOp, Commutable>;
1556 def v2i64 : N3VQInt
1557 OpcodeStr, !strconcat(Dt, "64"),
1558 v2i64, v2i64, IntOp, Commutable>;
1559 }
1560 }
13521561
13531562 // Neon Narrowing 3-register vector intrinsics,
13541563 // source operand element sizes of 16, 32 and 64 bits:
16181827 // imm6 = xxxxxx
16191828 }
16201829
1830 // Same as N2VSh_QHSD, except the instructions have a differnt interpretation of
1831 // the shift amount. This helps the disassembler.
1832 let NSF = NVectorShift2Frm, NSForm = NVectorShift2Frm.Value in {
1833 multiclass N2VSh_QHSD2 op11_8, bit op4,
1834 InstrItinClass itin, string OpcodeStr, string Dt,
1835 SDNode OpNode> {
1836 // 64-bit vector types.
1837 def v8i8 : N2VDSh
1838 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1839 let Inst{21-19} = 0b001; // imm6 = 001xxx
1840 }
1841 def v4i16 : N2VDSh
1842 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1843 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1844 }
1845 def v2i32 : N2VDSh
1846 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1847 let Inst{21} = 0b1; // imm6 = 1xxxxx
1848 }
1849 def v1i64 : N2VDSh
1850 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1851 // imm6 = xxxxxx
1852
1853 // 128-bit vector types.
1854 def v16i8 : N2VQSh
1855 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1856 let Inst{21-19} = 0b001; // imm6 = 001xxx
1857 }
1858 def v8i16 : N2VQSh
1859 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1860 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1861 }
1862 def v4i32 : N2VQSh
1863 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1864 let Inst{21} = 0b1; // imm6 = 1xxxxx
1865 }
1866 def v2i64 : N2VQSh
1867 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1868 // imm6 = xxxxxx
1869 }
1870 }
16211871
16221872 // Neon Shift-Accumulate vector operations,
16231873 // element sizes of 8, 16, 32 and 64 bits:
16961946 def v2i64 : N2VQShIns
16971947 OpcodeStr, "64", v2i64, ShOp>;
16981948 // imm6 = xxxxxx
1949 }
1950
1951 // Same as N2VShIns_QHSD, except the instructions have a differnt interpretation
1952 // of the shift amount. This helps the disassembler.
1953 let NSF = NVectorShift2Frm, NSForm = NVectorShift2Frm.Value in {
1954 multiclass N2VShIns_QHSD2 op11_8, bit op4,
1955 string OpcodeStr, SDNode ShOp> {
1956 // 64-bit vector types.
1957 def v8i8 : N2VDShIns
1958 OpcodeStr, "8", v8i8, ShOp> {
1959 let Inst{21-19} = 0b001; // imm6 = 001xxx
1960 }
1961 def v4i16 : N2VDShIns
1962 OpcodeStr, "16", v4i16, ShOp> {
1963 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1964 }
1965 def v2i32 : N2VDShIns
1966 OpcodeStr, "32", v2i32, ShOp> {
1967 let Inst{21} = 0b1; // imm6 = 1xxxxx
1968 }
1969 def v1i64 : N2VDShIns
1970 OpcodeStr, "64", v1i64, ShOp>;
1971 // imm6 = xxxxxx
1972
1973 // 128-bit vector types.
1974 def v16i8 : N2VQShIns
1975 OpcodeStr, "8", v16i8, ShOp> {
1976 let Inst{21-19} = 0b001; // imm6 = 001xxx
1977 }
1978 def v8i16 : N2VQShIns
1979 OpcodeStr, "16", v8i16, ShOp> {
1980 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1981 }
1982 def v4i32 : N2VQShIns
1983 OpcodeStr, "32", v4i32, ShOp> {
1984 let Inst{21} = 0b1; // imm6 = 1xxxxx
1985 }
1986 def v2i64 : N2VQShIns
1987 OpcodeStr, "64", v2i64, ShOp>;
1988 // imm6 = xxxxxx
1989 }
16991990 }
17001991
17011992 // Neon Shift Long operations,
23282619 // Vector Shifts.
23292620
23302621 // VSHL : Vector Shift
2331 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2332 IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
2333 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2334 IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
2622 defm VSHLs : N3VInt_QHSD2<0,0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2623 IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
2624 defm VSHLu : N3VInt_QHSD2<1,0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2625 IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
23352626 // VSHL : Vector Shift Left (Immediate)
2336 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
2627 // (disassembly note: this has a different interpretation of the shift amont)
2628 defm VSHLi : N2VSh_QHSD2<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
23372629 // VSHR : Vector Shift Right (Immediate)
23382630 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
23392631 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
23402632
23412633 // VSHLL : Vector Shift Left Long
2634 // (disassembly note: this has a different interpretation of the shift amont)
23422635 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2636 // (disassembly note: this has a different interpretation of the shift amont)
23432637 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
23442638
23452639 // VSHLL : Vector Shift Left Long (with maximum shift count)
23492643 : N2VLSh
23502644 ResTy, OpTy, OpNode> {
23512645 let Inst{21-16} = op21_16;
2646 let NSF = NVdVmImmVSHLLFrm; // For disassembly.
2647 let NSForm = NVdVmImmVSHLLFrm.Value; // For disassembly.
23522648 }
23532649 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
23542650 v8i16, v8i8, NEONvshlli>;
23622658 NEONvshrn>;
23632659
23642660 // VRSHL : Vector Rounding Shift
2365 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2366 IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
2367 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2368 IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
2661 defm VRSHLs : N3VInt_QHSD2<0,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2662 IIC_VSHLi4Q,"vrshl", "s", int_arm_neon_vrshifts,0>;
2663 defm VRSHLu : N3VInt_QHSD2<1,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2664 IIC_VSHLi4Q,"vrshl", "u", int_arm_neon_vrshiftu,0>;
23692665 // VRSHR : Vector Rounding Shift Right
23702666 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
23712667 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
23752671 NEONvrshrn>;
23762672
23772673 // VQSHL : Vector Saturating Shift
2378 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2379 IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
2380 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2381 IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
2674 defm VQSHLs : N3VInt_QHSD2<0,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2675 IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
2676 defm VQSHLu : N3VInt_QHSD2<1,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2677 IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
23822678 // VQSHL : Vector Saturating Shift Left (Immediate)
2383 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
2384 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
2679 // (disassembly note: this has a different interpretation of the shift amont)
2680 defm VQSHLsi : N2VSh_QHSD2<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
2681 // (disassembly note: this has a different interpretation of the shift amont)
2682 defm VQSHLui : N2VSh_QHSD2<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
23852683 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2386 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D, "vqshlu","s",NEONvqshlsu>;
2684 // (disassembly note: this has a different interpretation of the shift amont)
2685 defm VQSHLsu : N2VSh_QHSD2<1,1,0b0110,1, IIC_VSHLi4D, "vqshlu","s",NEONvqshlsu>;
23872686
23882687 // VQSHRN : Vector Saturating Shift Right and Narrow
23892688 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
23962695 NEONvqshrnsu>;
23972696
23982697 // VQRSHL : Vector Saturating Rounding Shift
2399 defm VQRSHLs : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2400 IIC_VSHLi4Q, "vqrshl", "s",
2401 int_arm_neon_vqrshifts, 0>;
2402 defm VQRSHLu : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2403 IIC_VSHLi4Q, "vqrshl", "u",
2404 int_arm_neon_vqrshiftu, 0>;
2698 defm VQRSHLs : N3VInt_QHSD2<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2699 IIC_VSHLi4Q, "vqrshl", "s",
2700 int_arm_neon_vqrshifts, 0>;
2701 defm VQRSHLu : N3VInt_QHSD2<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2702 IIC_VSHLi4Q, "vqrshl", "u",
2703 int_arm_neon_vqrshiftu, 0>;
24052704
24062705 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
24072706 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
24212720 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
24222721
24232722 // VSLI : Vector Shift Left and Insert
2424 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
2723 // (disassembly note: this has a different interpretation of the shift amont)
2724 defm VSLI : N2VShIns_QHSD2<1, 1, 0b0101, 1, "vsli", NEONvsli>;
24252725 // VSRI : Vector Shift Right and Insert
24262726 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
24272727
25172817
25182818 // VMOV : Vector Move (Register)
25192819
2820 // Mark these instructions as 2-register instructions to help the disassembler.
2821 let NSF = NVdVmImmFrm, NSForm = NVdVmImmFrm.Value in {
25202822 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
25212823 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
25222824 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
25232825 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2826 }
25242827
25252828 // VMOV : Vector Move (Immediate)
25262829
27613064
27623065 // VDUP : Vector Duplicate Lane (from scalar to all elements)
27633066
3067 let NSF = NVdVmImmVDupLaneFrm, NSForm = NVdVmImmVDupLaneFrm.Value in {
27643068 class VDUPLND op19_18, bits<2> op17_16,
27653069 string OpcodeStr, string Dt, ValueType Ty>
27663070 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
27743078 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
27753079 OpcodeStr, Dt, "$dst, $src[$lane]", "",
27763080 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
3081 }
27773082
27783083 // Inst{19-16} is partially specified depending on the element size.
27793084
28423147
28433148 // Vector Conversions.
28443149
3150 let NSF = NVdVmImmVCVTFrm, NSForm = NVdVmImmVCVTFrm.Value in {
3151 class N2VDX op24_23, bits<2> op21_20, bits<2> op19_18,
3152 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
3153 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
3154 : N2VD
3155 ResTy, OpTy, OpNode>;
3156 class N2VQX op24_23, bits<2> op21_20, bits<2> op19_18,
3157 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
3158 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
3159 : N2VQ
3160 ResTy, OpTy, OpNode>;
3161 }
3162
28453163 // VCVT : Vector Convert Between Floating-Point and Integers
2846 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2847 v2i32, v2f32, fp_to_sint>;
2848 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2849 v2i32, v2f32, fp_to_uint>;
2850 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2851 v2f32, v2i32, sint_to_fp>;
2852 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2853 v2f32, v2i32, uint_to_fp>;
2854
2855 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2856 v4i32, v4f32, fp_to_sint>;
2857 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2858 v4i32, v4f32, fp_to_uint>;
2859 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2860 v4f32, v4i32, sint_to_fp>;
2861 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2862 v4f32, v4i32, uint_to_fp>;
3164 def VCVTf2sd : N2VDX<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3165 v2i32, v2f32, fp_to_sint>;
3166 def VCVTf2ud : N2VDX<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3167 v2i32, v2f32, fp_to_uint>;
3168 def VCVTs2fd : N2VDX<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3169 v2f32, v2i32, sint_to_fp>;
3170 def VCVTu2fd : N2VDX<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3171 v2f32, v2i32, uint_to_fp>;
3172
3173 def VCVTf2sq : N2VQX<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3174 v4i32, v4f32, fp_to_sint>;
3175 def VCVTf2uq : N2VQX<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3176 v4i32, v4f32, fp_to_uint>;
3177 def VCVTs2fq : N2VQX<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3178 v4f32, v4i32, sint_to_fp>;
3179 def VCVTu2fq : N2VQX<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3180 v4f32, v4i32, uint_to_fp>;
28633181
28643182 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
28653183 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
29443262
29453263 // VEXT : Vector Extract
29463264
3265 let NSF = NVdVnVmImmVectorExtractFrm,
3266 NSForm = NVdVnVmImmVectorExtractFrm.Value in {
29473267 class VEXTd
29483268 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
29493269 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
29573277 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
29583278 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
29593279 (Ty QPR:$rhs), imm:$index)))]>;
3280 }
29603281
29613282 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
29623283 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
29993320 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
30003321
30013322 // Vector Table Lookup and Table Extension.
3323
3324 let NSF = VTBLFrm, NSForm = VTBLFrm.Value in {
30023325
30033326 // VTBL : Vector Table Lookup
30043327 def VTBL1
30553378 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
30563379 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
30573380 } // hasExtraSrcRegAllocReq = 1
3381
3382 } // End of "let NSF = VTBLFrm, ..."
30583383
30593384 //===----------------------------------------------------------------------===//
30603385 // NEON instructions for single-precision FP math
119119 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
120120 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
121121 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
122 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum) {}
122 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum);
123123 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
124124
125125 void printCPSOptionOperand(const MachineInstr *MI, int OpNum) {}
430430 O << "[" << getRegisterName(MO1.getReg());
431431
432432 if (!MO2.getReg()) {
433 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
433 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
434434 O << ", #"
435 << (char)ARM_AM::getAM2Op(MO3.getImm())
435 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
436436 << ARM_AM::getAM2Offset(MO3.getImm());
437437 O << "]";
438438 return;
439439 }
440440
441441 O << ", "
442 << (char)ARM_AM::getAM2Op(MO3.getImm())
442 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
443443 << getRegisterName(MO2.getReg());
444444
445445 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
457457 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
458458 assert(ImmOffs && "Malformed indexed load / store!");
459459 O << "#"
460 << (char)ARM_AM::getAM2Op(MO2.getImm())
460 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
461461 << ImmOffs;
462462 return;
463463 }
464464
465 O << (char)ARM_AM::getAM2Op(MO2.getImm())
465 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
466466 << getRegisterName(MO1.getReg());
467467
468468 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
489489
490490 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
491491 O << ", #"
492 << (char)ARM_AM::getAM3Op(MO3.getImm())
492 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
493493 << ImmOffs;
494494 O << "]";
495495 }
507507 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
508508 assert(ImmOffs && "Malformed indexed load / store!");
509509 O << "#"
510 << (char)ARM_AM::getAM3Op(MO2.getImm())
510 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
511511 << ImmOffs;
512512 }
513513
557557
558558 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
559559 O << ", #"
560 << (char)ARM_AM::getAM5Op(MO2.getImm())
560 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
561561 << ImmOffs*4;
562562 }
563563 O << "]";
593593
594594 const MachineOperand &MO1 = MI->getOperand(Op);
595595 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
596 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
596 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
597597 }
598598
599599 void
616616 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
617617 // (3 - the number of trailing zeros) is the number of then / else.
618618 unsigned Mask = MI->getOperand(Op).getImm();
619 unsigned CondBit0 = Mask >> 4 & 1;
619620 unsigned NumTZ = CountTrailingZeros_32(Mask);
620621 assert(NumTZ <= 3 && "Invalid IT mask!");
621622 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
622 bool T = (Mask & (1 << Pos)) == 0;
623 bool T = ((Mask >> Pos) & 1) == CondBit0;
623624 if (T)
624625 O << 't';
625626 else
651652 if (MO3.getReg())
652653 O << ", " << getRegisterName(MO3.getReg());
653654 else if (unsigned ImmOffs = MO2.getImm())
654 O << ", #+" << ImmOffs * Scale;
655 O << ", #" << ImmOffs * Scale;
655656 O << "]";
656657 }
657658
673674 const MachineOperand &MO2 = MI->getOperand(Op+1);
674675 O << "[" << getRegisterName(MO1.getReg());
675676 if (unsigned ImmOffs = MO2.getImm())
676 O << ", #+" << ImmOffs*4;
677 O << ", #" << ImmOffs*4;
677678 O << "]";
678679 }
679680
709710
710711 unsigned OffImm = MO2.getImm();
711712 if (OffImm) // Don't print +0.
712 O << ", #+" << OffImm;
713 O << ", #" << OffImm;
713714 O << "]";
714715 }
715716
725726 if (OffImm < 0)
726727 O << ", #-" << -OffImm;
727728 else if (OffImm > 0)
728 O << ", #+" << OffImm;
729 O << ", #" << OffImm;
729730 O << "]";
730731 }
731732
741742 if (OffImm < 0)
742743 O << ", #-" << -OffImm * 4;
743744 else if (OffImm > 0)
744 O << ", #+" << OffImm * 4;
745 O << ", #" << OffImm * 4;
745746 O << "]";
746747 }
747748
753754 if (OffImm < 0)
754755 O << "#-" << -OffImm;
755756 else if (OffImm > 0)
756 O << "#+" << OffImm;
757 O << "#" << OffImm;
758 }
759
760 void ARMAsmPrinter::printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI,
761 int OpNum) {
762 const MachineOperand &MO1 = MI->getOperand(OpNum);
763 int32_t OffImm = (int32_t)MO1.getImm() / 4;
764 // Don't print +0.
765 if (OffImm < 0)
766 O << "#-" << -OffImm * 4;
767 else if (OffImm > 0)
768 O << "#" << OffImm * 4;
757769 }
758770
759771 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
2727 #undef MachineInstr
2828 #undef ARMAsmPrinter
2929
30 void ARMInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
30 static unsigned NextReg(unsigned Reg) {
31 switch (Reg) {
32 case ARM::D0:
33 return ARM::D1;
34 case ARM::D1:
35 return ARM::D2;
36 case ARM::D2:
37 return ARM::D3;
38 case ARM::D3:
39 return ARM::D4;
40 case ARM::D4:
41 return ARM::D5;
42 case ARM::D5:
43 return ARM::D6;
44 case ARM::D6:
45 return ARM::D7;
46 case ARM::D7:
47 return ARM::D8;
48 case ARM::D8:
49 return ARM::D9;
50 case ARM::D9:
51 return ARM::D10;
52 case ARM::D10:
53 return ARM::D11;
54 case ARM::D11:
55 return ARM::D12;
56 case ARM::D12:
57 return ARM::D13;
58 case ARM::D13:
59 return ARM::D14;
60 case ARM::D14:
61 return ARM::D15;
62 case ARM::D15:
63 return ARM::D16;
64 case ARM::D16:
65 return ARM::D17;
66 case ARM::D17:
67 return ARM::D18;
68 case ARM::D18:
69 return ARM::D19;
70 case ARM::D19:
71 return ARM::D20;
72 case ARM::D20:
73 return ARM::D21;
74 case ARM::D21:
75 return ARM::D22;
76 case ARM::D22:
77 return ARM::D23;
78 case ARM::D23:
79 return ARM::D24;
80 case ARM::D24:
81 return ARM::D25;
82 case ARM::D25:
83 return ARM::D26;
84 case ARM::D26:
85 return ARM::D27;
86 case ARM::D27:
87 return ARM::D28;
88 case ARM::D28:
89 return ARM::D29;
90 case ARM::D29:
91 return ARM::D30;
92 case ARM::D30:
93 return ARM::D31;
94
95 default:
96 assert(0 && "Unexpected register enum");
97 }
98 }
99
100 void ARMInstPrinter::printInst(const MCInst *MI) {
101 // Check for MOVs and print canonical forms, instead.
102 if (MI->getOpcode() == ARM::MOVs) {
103 const MCOperand &Dst = MI->getOperand(0);
104 const MCOperand &MO1 = MI->getOperand(1);
105 const MCOperand &MO2 = MI->getOperand(2);
106 const MCOperand &MO3 = MI->getOperand(3);
107
108 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
109 printSBitModifierOperand(MI, 6);
110 printPredicateOperand(MI, 4);
111
112 O << '\t' << getRegisterName(Dst.getReg())
113 << ", " << getRegisterName(MO1.getReg());
114
115 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
116 return;
117
118 O << ", ";
119
120 if (MO2.getReg()) {
121 O << getRegisterName(MO2.getReg());
122 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
123 } else {
124 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
125 }
126 return;
127 }
128
129 // A8.6.123 PUSH
130 if ((MI->getOpcode() == ARM::STM || MI->getOpcode() == ARM::t2STM_UPD) &&
131 MI->getOperand(0).getReg() == ARM::SP) {
132 const unsigned IdxOffset = MI->getOpcode() == ARM::STM ? 0 : 1;
133 const MCOperand &MO1 = MI->getOperand(IdxOffset + 1);
134 if (ARM_AM::getAM4WBFlag(MO1.getImm()) &&
135 ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
136 O << '\t' << "push";
137 printPredicateOperand(MI, IdxOffset + 2);
138 O << '\t';
139 printRegisterList(MI, IdxOffset + 4);
140 return;
141 }
142 }
143
144 // A8.6.122 POP
145 if ((MI->getOpcode() == ARM::LDM || MI->getOpcode() == ARM::t2LDM_UPD) &&
146 MI->getOperand(0).getReg() == ARM::SP) {
147 const unsigned IdxOffset = MI->getOpcode() == ARM::LDM ? 0 : 1;
148 const MCOperand &MO1 = MI->getOperand(IdxOffset + 1);
149 if (ARM_AM::getAM4WBFlag(MO1.getImm()) &&
150 ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
151 O << '\t' << "pop";
152 printPredicateOperand(MI, IdxOffset + 2);
153 O << '\t';
154 printRegisterList(MI, IdxOffset + 4);
155 return;
156 }
157 }
158
159 // A8.6.355 VPUSH
160 if ((MI->getOpcode() == ARM::VSTMS || MI->getOpcode() == ARM::VSTMD) &&
161 MI->getOperand(0).getReg() == ARM::SP) {
162 const MCOperand &MO1 = MI->getOperand(1);
163 if (ARM_AM::getAM5WBFlag(MO1.getImm()) &&
164 ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::db) {
165 O << '\t' << "vpush";
166 printPredicateOperand(MI, 2);
167 O << '\t';
168 printRegisterList(MI, 4);
169 return;
170 }
171 }
172
173 // A8.6.354 VPOP
174 if ((MI->getOpcode() == ARM::VLDMS || MI->getOpcode() == ARM::VLDMD) &&
175 MI->getOperand(0).getReg() == ARM::SP) {
176 const MCOperand &MO1 = MI->getOperand(1);
177 if (ARM_AM::getAM5WBFlag(MO1.getImm()) &&
178 ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::ia) {
179 O << '\t' << "vpop";
180 printPredicateOperand(MI, 2);
181 O << '\t';
182 printRegisterList(MI, 4);
183 return;
184 }
185 }
186
187 printInstruction(MI);
188 }
31189
32190 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
33191 const char *Modifier) {
35193 if (Op.isReg()) {
36194 unsigned Reg = Op.getReg();
37195 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
196 O << '{' << getRegisterName(Reg) << ", "
197 << getRegisterName(NextReg(Reg)) << '}';
198 #if 0
38199 // FIXME: Breaks e.g. ARM/vmul.ll.
39200 assert(0);
40201 /*
43204 O << '{'
44205 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
45206 << '}';*/
207 #endif
46208 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
47209 assert(0);
48210 /*
55217 O << getRegisterName(Reg);
56218 }
57219 } else if (Op.isImm()) {
58 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
220 bool isCallOp = Modifier && !strcmp(Modifier, "call");
221 assert(isCallOp ||
222 ((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"));
59223 O << '#' << Op.getImm();
60224 } else {
61225 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
141305 O << "[" << getRegisterName(MO1.getReg());
142306
143307 if (!MO2.getReg()) {
144 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
308 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
145309 O << ", #"
146 << (char)ARM_AM::getAM2Op(MO3.getImm())
147 << ARM_AM::getAM2Offset(MO3.getImm());
310 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
311 << ARM_AM::getAM2Offset(MO3.getImm());
148312 O << "]";
149313 return;
150314 }
151315
152316 O << ", "
153 << (char)ARM_AM::getAM2Op(MO3.getImm())
154 << getRegisterName(MO2.getReg());
317 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
318 << getRegisterName(MO2.getReg());
155319
156320 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
157321 O << ", "
168332 if (!MO1.getReg()) {
169333 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
170334 assert(ImmOffs && "Malformed indexed load / store!");
171 O << '#' << (char)ARM_AM::getAM2Op(MO2.getImm()) << ImmOffs;
172 return;
173 }
174
175 O << (char)ARM_AM::getAM2Op(MO2.getImm()) << getRegisterName(MO1.getReg());
335 O << '#'
336 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
337 << ImmOffs;
338 return;
339 }
340
341 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
342 << getRegisterName(MO1.getReg());
176343
177344 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
178345 O << ", "
195362
196363 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
197364 O << ", #"
198 << (char)ARM_AM::getAM3Op(MO3.getImm())
199 << ImmOffs;
365 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
366 << ImmOffs;
200367 O << ']';
201368 }
202369
213380
214381 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
215382 assert(ImmOffs && "Malformed indexed load / store!");
216 O << "#"
217 << (char)ARM_AM::getAM3Op(MO2.getImm())
218 << ImmOffs;
383 O << '#'
384 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
385 << ImmOffs;
219386 }
220387
221388
263430
264431 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
265432 O << ", #"
266 << (char)ARM_AM::getAM5Op(MO2.getImm())
433 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
267434 << ImmOffs*4;
268435 }
269436 O << "]";
302469
303470 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) {
304471 O << "{";
305 // Always skip the first operand, it's the optional (and implicit writeback).
306 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
307 if (i != OpNum+1) O << ", ";
472 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
473 if (i != OpNum) O << ", ";
308474 O << getRegisterName(MI->getOperand(i).getReg());
309475 }
310476 O << "}";
477 }
478
479 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum) {
480 const MCOperand &Op = MI->getOperand(OpNum);
481 unsigned option = Op.getImm();
482 unsigned mode = option & 31;
483 bool changemode = option >> 5 & 1;
484 unsigned AIF = option >> 6 & 7;
485 unsigned imod = option >> 9 & 3;
486 if (imod == 2)
487 O << "ie";
488 else if (imod == 3)
489 O << "id";
490 O << '\t';
491 if (imod > 1) {
492 if (AIF & 4) O << 'a';
493 if (AIF & 2) O << 'i';
494 if (AIF & 1) O << 'f';
495 if (AIF > 0 && changemode) O << ", ";
496 }
497 if (changemode)
498 O << '#' << mode;
499 }
500
501 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum) {
502 const MCOperand &Op = MI->getOperand(OpNum);
503 unsigned Mask = Op.getImm();
504 if (Mask) {
505 O << '_';
506 if (Mask & 8) O << 'f';
507 if (Mask & 4) O << 's';
508 if (Mask & 2) O << 'x';
509 if (Mask & 1) O << 'c';
510 }
511 }
512
513 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum){
514 const MCOperand &Op = MI->getOperand(OpNum);
515 O << '#';
516 if (Op.getImm() < 0)
517 O << '-' << (-Op.getImm() - 1);
518 else
519 O << Op.getImm();
311520 }
312521
313522 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum) {
351560 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum) {
352561 O << "#" << MI->getOperand(OpNum).getImm() * 4;
353562 }
563
564 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum) {
565 // (3 - the number of trailing zeros) is the number of then / else.
566 unsigned Mask = MI->getOperand(OpNum).getImm();
567 unsigned CondBit0 = Mask >> 4 & 1;
568 unsigned NumTZ = CountTrailingZeros_32(Mask);
569 assert(NumTZ <= 3 && "Invalid IT mask!");
570 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
571 bool T = ((Mask >> Pos) & 1) == CondBit0;
572 if (T)
573 O << 't';
574 else
575 O << 'e';
576 }
577 }
578
579 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op)
580 {
581 const MCOperand &MO1 = MI->getOperand(Op);
582 const MCOperand &MO2 = MI->getOperand(Op+1);
583 O << "[" << getRegisterName(MO1.getReg());
584 O << ", " << getRegisterName(MO2.getReg()) << "]";
585 }
586
587 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
588 unsigned Scale) {
589 const MCOperand &MO1 = MI->getOperand(Op);
590 const MCOperand &MO2 = MI->getOperand(Op+1);
591 const MCOperand &MO3 = MI->getOperand(Op+2);
592
593 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
594 printOperand(MI, Op);
595 return;
596 }
597
598 O << "[" << getRegisterName(MO1.getReg());
599 if (MO3.getReg())
600 O << ", " << getRegisterName(MO3.getReg());
601 else if (unsigned ImmOffs = MO2.getImm())
602 O << ", #" << ImmOffs * Scale;
603 O << "]";
604 }
605
606 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op)
607 {
608 printThumbAddrModeRI5Operand(MI, Op, 1);
609 }
610
611 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op)
612 {
613 printThumbAddrModeRI5Operand(MI, Op, 2);
614 }
615
616 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op)
617 {
618 printThumbAddrModeRI5Operand(MI, Op, 4);
619 }
620
621 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI,unsigned Op) {
622 const MCOperand &MO1 = MI->getOperand(Op);
623 const MCOperand &MO2 = MI->getOperand(Op+1);
624 O << "[" << getRegisterName(MO1.getReg());
625 if (unsigned ImmOffs = MO2.getImm())
626 O << ", #" << ImmOffs*4;
627 O << "]";
628 }
629
630 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum) {
631 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
632 if (MI->getOpcode() == ARM::t2TBH)
633 O << ", lsl #1";
634 O << ']';
635 }
636
637 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
638 // register with shift forms.
639 // REG 0 0 - e.g. R5
640 // REG IMM, SH_OPC - e.g. R5, LSL #3
641 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum) {
642 const MCOperand &MO1 = MI->getOperand(OpNum);
643 const MCOperand &MO2 = MI->getOperand(OpNum+1);
644
645 unsigned Reg = MO1.getReg();
646 O << getRegisterName(Reg);
647
648 // Print the shift opc.
649 O << ", "
650 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
651 << " ";
652
653 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
654 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
655 }
656
657 void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI,
658 unsigned OpNum) {
659 const MCOperand &MO1 = MI->getOperand(OpNum);
660 const MCOperand &MO2 = MI->getOperand(OpNum+1);
661
662 O << "[" << getRegisterName(MO1.getReg());
663
664 unsigned OffImm = MO2.getImm();
665 if (OffImm) // Don't print +0.
666 O << ", #" << OffImm;
667 O << "]";
668 }
669
670 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
671 unsigned OpNum) {
672 const MCOperand &MO1 = MI->getOperand(OpNum);
673 const MCOperand &MO2 = MI->getOperand(OpNum+1);
674
675 O << "[" << getRegisterName(MO1.getReg());
676
677 int32_t OffImm = (int32_t)MO2.getImm();
678 // Don't print +0.
679 if (OffImm < 0)
680 O << ", #-" << -OffImm;
681 else if (OffImm > 0)
682 O << ", #" << OffImm;
683 O << "]";
684 }
685
686 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
687 unsigned OpNum) {
688 const MCOperand &MO1 = MI->getOperand(OpNum);
689 const MCOperand &MO2 = MI->getOperand(OpNum+1);
690
691 O << "[" << getRegisterName(MO1.getReg());
692
693 int32_t OffImm = (int32_t)MO2.getImm() / 4;
694 // Don't print +0.
695 if (OffImm < 0)
696 O << ", #-" << -OffImm * 4;
697 else if (OffImm > 0)
698 O << ", #" << OffImm * 4;
699 O << "]";
700 }
701
702 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
703 unsigned OpNum) {
704 const MCOperand &MO1 = MI->getOperand(OpNum);
705 int32_t OffImm = (int32_t)MO1.getImm();
706 // Don't print +0.
707 if (OffImm < 0)
708 O << "#-" << -OffImm;
709 else if (OffImm > 0)
710 O << "#" << OffImm;
711 }
712
713 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
714 unsigned OpNum) {
715 const MCOperand &MO1 = MI->getOperand(OpNum);
716 int32_t OffImm = (int32_t)MO1.getImm() / 4;
717 // Don't print +0.
718 if (OffImm < 0)
719 O << "#-" << -OffImm * 4;
720 else if (OffImm > 0)
721 O << "#" << OffImm * 4;
722 }
723
724 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
725 unsigned OpNum) {
726 const MCOperand &MO1 = MI->getOperand(OpNum);
727 const MCOperand &MO2 = MI->getOperand(OpNum+1);
728 const MCOperand &MO3 = MI->getOperand(OpNum+2);
729
730 O << "[" << getRegisterName(MO1.getReg());
731
732 assert(MO2.getReg() && "Invalid so_reg load / store address!");
733 O << ", " << getRegisterName(MO2.getReg());
734
735 unsigned ShAmt = MO3.getImm();
736 if (ShAmt) {
737 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
738 O << ", lsl #" << ShAmt;
739 }
740 O << "]";
741 }
742
743 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum) {
744 O << '#' << MI->getOperand(OpNum).getImm();
745 }
746
747 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum) {
748 O << '#' << MI->getOperand(OpNum).getImm();
749 }
750
5353 void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum);
5454
5555 void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum);
56 void printThumbITMask(const MCInst *MI, unsigned OpNum) {}
57 void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum) {}
56 void printThumbITMask(const MCInst *MI, unsigned OpNum);
57 void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum);
5858 void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum,
59 unsigned Scale) {}
60 void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum) {}
61 void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum) {}
62 void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum) {}
63 void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum) {}
59 unsigned Scale);
60 void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum);
61 void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum);
62 void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum);
63 void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum);
6464
65 void printT2SOOperand(const MCInst *MI, unsigned OpNum) {}
66 void printT2AddrModeImm12Operand(const MCInst *MI, unsigned OpNum) {}
67 void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum) {}
68 void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum) {}
69 void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum) {}
70 void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum) {}
71 void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum) {}
65 void printT2SOOperand(const MCInst *MI, unsigned OpNum);
66 void printT2AddrModeImm12Operand(const MCInst *MI, unsigned OpNum);
67 void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum);
68 void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum);
69 void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum);
70 void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum);
71 void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum);
7272
73 void printCPSOptionOperand(const MCInst *MI, unsigned OpNum) {}
74 void printMSRMaskOperand(const MCInst *MI, unsigned OpNum) {}
75 void printNegZeroOperand(const MCInst *MI, unsigned OpNum) {}
73 void printCPSOptionOperand(const MCInst *MI, unsigned OpNum);
74 void printMSRMaskOperand(const MCInst *MI, unsigned OpNum);
75 void printNegZeroOperand(const MCInst *MI, unsigned OpNum);
7676 void printPredicateOperand(const MCInst *MI, unsigned OpNum);
7777 void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum);
7878 void printSBitModifierOperand(const MCInst *MI, unsigned OpNum);
8181 const char *Modifier);
8282 void printJTBlockOperand(const MCInst *MI, unsigned OpNum) {}
8383 void printJT2BlockOperand(const MCInst *MI, unsigned OpNum) {}
84 void printTBAddrMode(const MCInst *MI, unsigned OpNum) {}
84 void printTBAddrMode(const MCInst *MI, unsigned OpNum);
8585 void printNoHashImmediate(const MCInst *MI, unsigned OpNum);
86 void printVFPf32ImmOperand(const MCInst *MI, int OpNum) {}
87 void printVFPf64ImmOperand(const MCInst *MI, int OpNum) {}
86 void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum);
87 void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum);
8888 void printHex8ImmOperand(const MCInst *MI, int OpNum) {}
8989 void printHex16ImmOperand(const MCInst *MI, int OpNum) {}
9090 void printHex32ImmOperand(const MCInst *MI, int OpNum) {}
0 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the ARM Disassembler.
10 // It contains code to translate the data produced by the decoder into MCInsts.
11 // Documentation for the disassembler can be found in ARMDisassembler.h.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "arm-disassembler"
16
17 #include "ARMDisassembler.h"
18 #include "ARMDisassemblerCore.h"
19
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Target/TargetRegistry.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26
27 /// ARMDisassemblerTables.inc - ARMDisassemblerTables.inc is tblgen'ed from
28 /// RISCDisassemblerEmitter.cpp TableGen backend. It contains:
29 ///
30 /// o Mappings from opcode to ARM/Thumb instruction format
31 ///
32 /// o static uint16_t decodeInstruction(uint32_t insn) - the decoding function
33 /// for an ARM instruction.
34 ///
35 /// o static uint16_t decodeThumbInstruction(field_t insn) - the decoding
36 /// function for a Thumb instruction.
37 ///
38 #include "../ARMGenDisassemblerTables.inc"
39
40 namespace llvm {
41
42 namespace ARMDisassembler {
43
44 /// showBitVector - Use the raw_ostream to log a diagnostic message describing
45 /// the inidividual bits of the instruction. This is a sample output:
46 ///
47 /// 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
48 /// -------------------------------------------------------------------------------------------------
49 /// | 1: 0: 1: 0| 1: 0: 1: 0| 1: 0: 1: 0| 1: 0: 1: 0| 1: 0: 1: 0| 1: 0: 1: 0| 1: 0: 1: 0| 1: 0: 1: 0|
50 /// -------------------------------------------------------------------------------------------------
51 ///
52 static inline void showBitVector(raw_ostream &os, const uint32_t &insn) {
53 os << " 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \n";
54 os << "-------------------------------------------------------------------------------------------------\n";
55 os << '|';
56 for (unsigned i = 32; i != 0; --i) {
57 if (insn >> (i - 1) & 0x01)
58 os << " 1";
59 else
60 os << " 0";
61 os << (i%4 == 1 ? '|' : ':');
62 }
63 os << '\n';
64 os << "-------------------------------------------------------------------------------------------------\n";
65 os << '\n';
66 }
67
68 /// decodeARMInstruction is a decorator function which tries special cases of
69 /// instruction matching before calling the auto-generated decoder function.
70 static unsigned decodeARMInstruction(uint32_t &insn) {
71 if (slice(insn, 31, 28) == 15)
72 goto AutoGenedDecoder;
73
74 // Special case processing, if any, goes here....
75
76 // LLVM combines the offset mode of A8.6.197 & A8.6.198 into STRB.
77 // The insufficient encoding information of the combined instruction confuses
78 // the decoder wrt BFC/BFI. Therefore, we try to recover here.
79 // For BFC, Inst{27-21} = 0b0111110 & Inst{6-0} = 0b0011111.
80 // For BFI, Inst{27-21} = 0b0111110 & Inst{6-4} = 0b001 & Inst{3-0} =! 0b1111.
81 if (slice(insn, 27, 21) == 0x3e && slice(insn, 6, 4) == 1) {
82 if (slice(insn, 3, 0) == 15)
83 return ARM::BFC;
84 else
85 return ARM::BFI;
86 }
87
88 // Ditto for ADDSrs, which is a super-instruction for A8.6.7 & A8.6.8.
89 // As a result, the decoder fails to decode UMULL properly.
90 if (slice(insn, 27, 21) == 0x04 && slice(insn, 7, 4) == 9) {
91 return ARM::UMULL;
92 }
93
94 // Ditto for STR_PRE, which is a super-instruction for A8.6.194 & A8.6.195.
95 // As a result, the decoder fails to decode SBFX properly.
96 if (slice(insn, 27, 21) == 0x3d && slice(insn, 6, 4) == 5)
97 return ARM::SBFX;
98
99 // And STRB_PRE, which is a super-instruction for A8.6.197 & A8.6.198.
100 // As a result, the decoder fails to decode UBFX properly.
101 if (slice(insn, 27, 21) == 0x3f && slice(insn, 6, 4) == 5)
102 return ARM::UBFX;
103
104 // Ditto for STRT, which is a super-instruction for A8.6.210 Encoding A1 & A2.
105 // As a result, the decoder fails to deocode SSAT properly.
106 if (slice(insn, 27, 21) == 0x35 && slice(insn, 5, 4) == 1)
107 return slice(insn, 6, 6) == 0 ? ARM::SSATlsl : ARM::SSATasr;
108
109 // Ditto for RSCrs, which is a super-instruction for A8.6.146 & A8.6.147.
110 // As a result, the decoder fails to decode STRHT/LDRHT/LDRSHT/LDRSBT.
111 if (slice(insn, 27, 24) == 0) {
112 switch (slice(insn, 21, 20)) {
113 case 2:
114 switch (slice(insn, 7, 4)) {
115 case 11:
116 return ARM::STRHT;
117 default:
118 break; // fallthrough
119 }
120 break;
121 case 3:
122 switch (slice(insn, 7, 4)) {
123 case 11:
124 return ARM::LDRHT;
125 case 13:
126 return ARM::LDRSBT;
127 case 15:
128 return ARM::LDRSHT;
129 default:
130 break; // fallthrough
131 }
132 break;
133 default:
134 break; // fallthrough
135 }
136 }
137
138 // Ditto for SBCrs, which is a super-instruction for A8.6.152 & A8.6.153.
139 // As a result, the decoder fails to decode STRH_Post/LDRD_POST/STRD_POST
140 // properly.
141 if (slice(insn, 27, 25) == 0 && slice(insn, 20, 20) == 0) {
142 unsigned PW = slice(insn, 24, 24) << 1 | slice(insn, 21, 21);
143 switch (slice(insn, 7, 4)) {
144 case 11:
145 switch (PW) {
146 case 2: // Offset
147 return ARM::STRH;
148 case 3: // Pre-indexed
149 return ARM::STRH_PRE;
150 case 0: // Post-indexed
151 return ARM::STRH_POST;
152 default:
153 break; // fallthrough
154 }
155 break;
156 case 13:
157 switch (PW) {
158 case 2: // Offset
159 return ARM::LDRD;
160 case 3: // Pre-indexed
161 return ARM::LDRD_PRE;
162 case 0: // Post-indexed
163 return ARM::LDRD_POST;
164 default:
165 break; // fallthrough
166 }
167 break;
168 case 15:
169 switch (PW) {
170 case 2: // Offset
171 return ARM::STRD;
172 case 3: // Pre-indexed
173 return ARM::STRD_PRE;
174 case 0: // Post-indexed
175 return ARM::STRD_POST;
176 default:
177 break; // fallthrough
178 }
179 break;
180 default:
181 break; // fallthrough
182 }
183 }
184
185 // Ditto for SBCSSrs, which is a super-instruction for A8.6.152 & A8.6.153.
186 // As a result, the decoder fails to decode LDRH_POST/LDRSB_POST/LDRSH_POST
187 // properly.
188 if (slice(insn, 27, 25) == 0 && slice(insn, 20, 20) == 1) {
189 unsigned PW = slice(insn, 24, 24) << 1 | slice(insn, 21, 21);
190 switch (slice(insn, 7, 4)) {
191 case 11:
192 switch (PW) {
193 case 2: // Offset
194 return ARM::LDRH;
195 case 3: // Pre-indexed
196 return ARM::LDRH_PRE;
197 case 0: // Post-indexed
198 return ARM::LDRH_POST;
199 default:
200 break; // fallthrough
201 }
202 break;
203 case 13:
204 switch (PW) {
205 case 2: // Offset
206 return ARM::LDRSB;
207 case 3: // Pre-indexed
208 return ARM::LDRSB_PRE;
209 case 0: // Post-indexed
210 return ARM::LDRSB_POST;
211 default:
212 break; // fallthrough
213 }
214 break;
215 case 15:
216 switch (PW) {
217 case 2: // Offset
218 return ARM::LDRSH;
219 case 3: // Pre-indexed
220 return ARM::LDRSH_PRE;
221 case 0: // Post-indexed
222 return ARM::LDRSH_POST;
223 default:
224 break; // fallthrough
225 }
226 break;
227 default:
228 break; // fallthrough
229 }
230 }
231
232 AutoGenedDecoder:
233 // Calling the auto-generated decoder function.
234 return decodeInstruction(insn);
235 }
236
237 // Helper function for special case handling of LDR (literal) and friends.
238 // See, for example, A6.3.7 Load word: Table A6-18 Load word.
239 // See A8.6.57 T3, T4 & A8.6.60 T2 and friends for why we morphed the opcode
240 // before passing it on.
241 static unsigned T2Morph2LoadLiteral(unsigned Opcode) {
242 switch (Opcode) {
243 default:
244 return Opcode; // Return unmorphed opcode.
245
246 case ARM::t2LDRDi8:
247 return ARM::t2LDRDpci;
248
249 case ARM::t2LDR_POST: case ARM::t2LDR_PRE:
250 case ARM::t2LDRi12: case ARM::t2LDRi8:
251 case ARM::t2LDRs:
252 return ARM::t2LDRpci;
253
254 case ARM::t2LDRB_POST: case ARM::t2LDRB_PRE:
255 case ARM::t2LDRBi12: case ARM::t2LDRBi8:
256 case ARM::t2LDRBs:
257 return ARM::t2LDRBpci;
258
259 case ARM::t2LDRH_POST: case ARM::t2LDRH_PRE:
260 case ARM::t2LDRHi12: case ARM::t2LDRHi8:
261 case ARM::t2LDRHs:
262 return ARM::t2LDRHpci;
263
264 case ARM::t2LDRSB_POST: case ARM::t2LDRSB_PRE:
265 case ARM::t2LDRSBi12: case ARM::t2LDRSBi8:
266 case ARM::t2LDRSBs:
267 return ARM::t2LDRSBpci;
268
269 case ARM::t2LDRSH_POST: case ARM::t2LDRSH_PRE:
270 case ARM::t2LDRSHi12: case ARM::t2LDRSHi8:
271 case ARM::t2LDRSHs:
272 return ARM::t2LDRSHpci;
273 }
274 }
275
276 /// decodeThumbSideEffect is a decorator function which can potentially twiddle
277 /// the instruction or morph the returned opcode under Thumb2.
278 ///
279 /// First it checks whether the insn is a NEON or VFP instr; if true, bit
280 /// twiddling could be performed on insn to turn it into an ARM NEON/VFP
281 /// equivalent instruction and decodeInstruction is called with the transformed
282 /// insn.
283 ///
284 /// Next, there is special handling for Load byte/halfword/word instruction by
285 /// checking whether Rn=0b1111 and call T2Morph2LoadLiteral() on the decoded
286 /// Thumb2 instruction. See comments below for further details.
287 ///
288 /// Finally, one last check is made to see whether the insn is a NEON/VFP and
289 /// decodeInstruction(insn) is invoked on the original insn.
290 ///
291 /// Otherwise, decodeThumbInstruction is called with the original insn.
292 static unsigned decodeThumbSideEffect(bool IsThumb2, uint32_t &insn) {
293 if (IsThumb2) {
294 uint16_t op1 = slice(insn, 28, 27);
295 uint16_t op2 = slice(insn, 26, 20);
296
297 // A6.3 32-bit Thumb instruction encoding
298 // Table A6-9 32-bit Thumb instruction encoding
299
300 // The coprocessor instructions of interest are transformed to their ARM
301 // equivalents.
302
303 // --------- Transform Begin Marker ---------
304 if ((op1 == 1 || op1 == 3) && slice(op2, 6, 4) == 7) {
305 // A7.4 Advanced SIMD data-processing instructions
306 // U bit of Thumb corresponds to Inst{24} of ARM.
307 uint16_t U = slice(op1, 1, 1);
308
309 // Inst{28-24} of ARM = {1,0,0,1,U};
310 uint16_t bits28_24 = 9 << 1 | U;
311 DEBUG(showBitVector(errs(), insn));
312 setSlice(insn, 28, 24, bits28_24);
313 return decodeInstruction(insn);
314 }
315
316 if (op1 == 3 && slice(op2, 6, 4) == 1 && slice(op2, 0, 0) == 0) {
317 // A7.7 Advanced SIMD element or structure load/store instructions
318 // Inst{27-24} of Thumb = 0b1001
319 // Inst{27-24} of ARM = 0b0100
320 DEBUG(showBitVector(errs(), insn));
321 setSlice(insn, 27, 24, 4);
322 return decodeInstruction(insn);
323 }
324 // --------- Transform End Marker ---------
325
326 // See, for example, A6.3.7 Load word: Table A6-18 Load word.
327 // See A8.6.57 T3, T4 & A8.6.60 T2 and friends for why we morphed the opcode
328 // before passing it on to our delegate.
329 if (op1 == 3 && slice(op2, 6, 5) == 0 && slice(op2, 0, 0) == 1
330 && slice(insn, 19, 16) == 15)
331 return T2Morph2LoadLiteral(decodeThumbInstruction(insn));
332
333 // One last check for NEON/VFP instructions.
334 if ((op1 == 1 || op1 == 3) && slice(op2, 6, 6) == 1)
335 return decodeInstruction(insn);
336
337 // Fall through.
338 }
339
340 return decodeThumbInstruction(insn);
341 }
342
343 static inline bool Thumb2PreloadOpcodeNoPCI(unsigned Opcode) {
344 switch (Opcode) {
345 default:
346 return false;
347 case ARM::t2PLDi12: case ARM::t2PLDi8:
348 case ARM::t2PLDr: case ARM::t2PLDs:
349 case ARM::t2PLDWi12: case ARM::t2PLDWi8:
350 case ARM::t2PLDWr: case ARM::t2PLDWs:
351 case ARM::t2PLIi12: case ARM::t2PLIi8:
352 case ARM::t2PLIr: case ARM::t2PLIs:
353 return true;
354 }
355 }
356
357 static inline unsigned T2Morph2Preload2PCI(unsigned Opcode) {
358 switch (Opcode) {
359 default:
360 return 0;
361 case ARM::t2PLDi12: case ARM::t2PLDi8:
362 case ARM::t2PLDr: case ARM::t2PLDs:
363 return ARM::t2PLDpci;
364 case ARM::t2PLDWi12: case ARM::t2PLDWi8:
365 case ARM::t2PLDWr: case ARM::t2PLDWs:
366 return ARM::t2PLDWpci;
367 case ARM::t2PLIi12: case ARM::t2PLIi8:
368 case ARM::t2PLIr: case ARM::t2PLIs:
369 return ARM::t2PLIpci;
370 }
371 }
372
373 //
374 // Public interface for the disassembler
375 //
376
377 bool ARMDisassembler::getInstruction(MCInst &MI,
378 uint64_t &Size,
379 const MemoryObject &Region,
380 uint64_t Address,
381 raw_ostream &os) const {
382 // The machine instruction.
383 uint32_t insn;
384
385 // We want to read exactly 4 bytes of data.
386 if (Region.readBytes(Address, 4, (uint8_t*)&insn, NULL) == -1)
387 return false;
388
389 unsigned Opcode = decodeARMInstruction(insn);
390 ARMFormat Format = ARMFormats[Opcode];
391 NSFormat NSF = NSFormats[Opcode];
392 Size = 4;
393
394 DEBUG({
395 errs() << "Opcode=" << Opcode << " Name=" << ARMUtils::OpcodeName(Opcode)
396 << " Format=" << stringForARMFormat(Format) << " NSFormat="
397 << stringForNSFormat(NSF) << '\n';
398 showBitVector(errs(), insn);
399 });
400
401 AbstractARMMCBuilder *Builder =
402 ARMMCBuilderFactory::CreateMCBuilder(Opcode, Format, NSF);
403
404 if (!Builder)
405 return false;
406
407 if (!Builder->Build(MI, insn))
408 return false;
409
410 delete Builder;
411
412 return true;
413 }
414
415 bool ThumbDisassembler::getInstruction(MCInst &MI,
416 uint64_t &Size,
417 const MemoryObject &Region,
418 uint64_t Address,
419 raw_ostream &os) const {
420 // The machine instruction.
421 uint32_t insn = 0;
422 uint32_t insn1 = 0;
423
424 // A6.1 Thumb instruction set encoding
425 //
426 // If bits [15:11] of the halfword being decoded take any of the following
427 // values, the halfword is the first halfword of a 32-bit instruction:
428 // o 0b11101
429 // o 0b11110
430 // o 0b11111.
431 //
432 // Otherwise, the halfword is a 16-bit instruction.
433
434 // Read 2 bytes of data first.
435 if (Region.readBytes(Address, 2, (uint8_t*)&insn, NULL) == -1)
436 return false;
437
438 unsigned bits15_11 = slice(insn, 15, 11);
439 bool IsThumb2 = false;
440
441 // 32-bit instructions if the bits [15:11] of the halfword matches
442 // { 0b11101 /* 0x1D */, 0b11110 /* 0x1E */, ob11111 /* 0x1F */ }.
443 if (bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F) {
444 IsThumb2 = true;
445 if (Region.readBytes(Address + 2, 2, (uint8_t*)&insn1, NULL) == -1)
446 return false;
447 insn = (insn << 16 | insn1);
448 }
449
450 // The insn could potentially be bit-twiddled in order to be decoded as an ARM
451 // NEON/VFP opcode. In such case, the modified insn is later disassembled as
452 // an ARM NEON/VFP instruction.
453 //
454 // This is a short term solution for lack of encoding bits specified for the
455 // Thumb2 NEON/VFP instructions. The long term solution could be adding some
456 // infrastructure to have each instruction support more than one encodings.
457 // Which encoding is used would be based on which subtarget the compiler/
458 // disassembler is working with at the time. This would allow the sharing of
459 // the NEON patterns between ARM and Thumb2, as well as potential greater
460 // sharing between the regular ARM instructions and the 32-bit wide Thumb2
461 // instructions as well.
462 unsigned Opcode = decodeThumbSideEffect(IsThumb2, insn);
463
464 // A8.6.117/119/120/121.
465 // PLD/PLDW/PLI instructions with Rn==15 is transformed to the pci variant.
466 if (Thumb2PreloadOpcodeNoPCI(Opcode) && slice(insn, 19, 16) == 15)
467 Opcode = T2Morph2Preload2PCI(Opcode);
468
469 ARMFormat Format = ARMFormats[Opcode];
470 NSFormat NSF = NSFormats[Opcode];
471 Size = IsThumb2 ? 4 : 2;
472
473 DEBUG({
474 errs() << "Opcode=" << Opcode << " Name=" << ARMUtils::OpcodeName(Opcode)
475 << " Format=" << stringForARMFormat(Format) << " NSFormat="
476 << stringForNSFormat(NSF) << '\n';
477 showBitVector(errs(), insn);
478 });
479
480 AbstractARMMCBuilder *Builder =
481 ARMMCBuilderFactory::CreateMCBuilder(Opcode, Format, NSF);
482
483 if (!Builder)
484 return false;
485
486 if (!Builder->Build(MI, insn))
487 return false;
488
489 delete Builder;
490
491 return true;
492 }
493
494 } // namespace ARM Disassembler
495
496 static const MCDisassembler *createARMDisassembler(const Target &T) {
497 return new ARMDisassembler::ARMDisassembler;
498 }
499
500 static const MCDisassembler *createThumbDisassembler(const Target &T) {
501 return new ARMDisassembler::ThumbDisassembler;
502 }
503
504 extern "C" void LLVMInitializeARMDisassembler() {
505 // Register the disassembler.
506 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
507 createARMDisassembler);
508 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
509 createThumbDisassembler);
510 }
511
512 } // namespace llvm
0 //===- X86Disassembler.h - Disassembler for x86 and x86_64 ------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10
11 #ifndef ARMDISASSEMBLER_H
12 #define ARMDISASSEMBLER_H
13
14 #include "llvm/MC/MCDisassembler.h"
15
16 namespace llvm {
17
18 class MCInst;
19 class MemoryObject;
20 class raw_ostream;
21
22 namespace ARMDisassembler {
23
24 /// ARMDisassembler - ARM disassembler for all ARM platforms.
25 class ARMDisassembler : public MCDisassembler {
26 public:
27 /// Constructor - Initializes the disassembler.
28 ///
29 ARMDisassembler() :
30 MCDisassembler() {
31 }
32
33 ~ARMDisassembler() {
34 }
35
36 /// getInstruction - See MCDisassembler.
37 bool getInstruction(MCInst &instr,
38 uint64_t &size,
39 const MemoryObject ®ion,
40 uint64_t address,
41 raw_ostream &vStream) const;
42 private:
43 };
44
45 /// ThumbDisassembler - Thumb disassembler for all ARM platforms.
46 class ThumbDisassembler : public MCDisassembler {
47 public:
48 /// Constructor - Initializes the disassembler.
49 ///
50 ThumbDisassembler() :
51 MCDisassembler() {
52 }
53
54 ~ThumbDisassembler() {
55 }
56
57 /// getInstruction - See MCDisassembler.
58 bool getInstruction(MCInst &instr,
59 uint64_t &size,
60 const MemoryObject ®ion,
61 uint64_t address,
62 raw_ostream &vStream) const;
63 private:
64 };
65
66 } // namespace ARMDisassembler
67
68 } // namespace llvm
69
70 #endif
0 //===- ARMDisassemblerCore.cpp - ARM disassembler helpers ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the ARM Disassembler.
10 // It contains code to represent the core concepts of Builder, Builder Factory,
11 // as well as the Algorithm to solve the problem of disassembling an ARM instr.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "ARMAddressingModes.h"
16 #include "ARMDisassemblerCore.h"
17 #include
18
19 /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
20 /// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s
21 /// describing the operand info for each ARMInsts[i].
22 ///
23 /// Together with an instruction's encoding format, we can take advantage of the
24 /// NumOperands and the OpInfo fields of the target instruction description in
25 /// the quest to build out the MCOperand list for an MCInst.
26 ///
27 /// The general guideline is that with a known format, the number of dst and src
28 /// operands are well-known. The dst is built first, followed by the src
29 /// operand(s). The operands not yet used at this point are for the Implicit
30 /// Uses and Defs by this instr. For the Uses part, the pred:$p operand is
31 /// defined with two components:
32 ///
33 /// def pred { // Operand PredicateOperand
34 /// ValueType Type = OtherVT;
35 /// string PrintMethod = "printPredicateOperand";
36 /// string AsmOperandLowerMethod = ?;
37 /// dag MIOperandInfo = (ops i32imm, CCR);
38 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
39 /// dag DefaultOps = (ops (i32 14), (i32 zero_reg));
40 /// }
41 ///
42 /// which is manifested by the TargetOperandInfo[] of:
43 ///
44 /// { 0, 0|(1<
45 /// { ARM::CCRRegClassID, 0|(1<
46 ///
47 /// So the first predicate MCOperand corresponds to the immediate part of the
48 /// ARM condition field (Inst{31-28}), and the second predicate MCOperand
49 /// corresponds to a register kind of ARM::CPSR.
50 ///
51 /// For the Defs part, in the simple case of only cc_out:$s, we have:
52 ///
53 /// def cc_out { // Operand OptionalDefOperand
54 /// ValueType Type = OtherVT;
55 /// string PrintMethod = "printSBitModifierOperand";
56 /// string AsmOperandLowerMethod = ?;
57 /// dag MIOperandInfo = (ops CCR);
58 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
59 /// dag DefaultOps = (ops (i32 zero_reg));
60 /// }
61 ///
62 /// which is manifested by the one TargetOperandInfo of:
63 ///
64 /// { ARM::CCRRegClassID, 0|(1<
65 ///
66 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
67 #include "ARMGenInstrInfo.inc"
68
69 using namespace llvm;
70
71 const char *ARMUtils::OpcodeName(unsigned Opcode) {
72 return ARMInsts[Opcode].Name;
73 }
74
75 // There is a more efficient way than the following. It is fragile, though.
76 // See the code snippet after this function.
77 static unsigned getRegisterEnum(unsigned RegClassID, unsigned RawRegister,
78 bool DRegPair = false) {
79
80 if (DRegPair && RegClassID == ARM::QPRRegClassID) {
81 // LLVM expects { Dd, Dd+1 } to form a super register; this is not specified
82 // in the ARM Architecture Manual as far as I understand it (A8.6.307).
83 // Therefore, we morph the RegClassID to be the sub register class and don't
84 // subsequently transform the RawRegister encoding when calculating RegNum.
85 //
86 // See also ARMinstPrinter::printOperand() wrt "dregpair" modifier part
87 // where this workaround is meant for.
88 RegClassID = ARM::DPRRegClassID;
89 }
90
91 // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
92 unsigned RegNum =
93 RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;
94
95 switch (RegNum) {
96 default:
97 break;
98 case 0:
99 switch (RegClassID) {
100 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R0;
101 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
102 case ARM::DPR_VFP2RegClassID:
103 return ARM::D0;
104 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
105 case ARM::QPR_VFP2RegClassID:
106 return ARM::Q0;
107 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S0;
108 }
109 break;
110 case 1:
111 switch (RegClassID) {
112 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R1;
113 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
114 case ARM::DPR_VFP2RegClassID:
115 return ARM::D1;
116 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
117 case ARM::QPR_VFP2RegClassID:
118 return ARM::Q1;
119 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S1;
120 }
121 break;
122 case 2:
123 switch (RegClassID) {
124 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R2;
125 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
126 case ARM::DPR_VFP2RegClassID:
127 return ARM::D2;
128 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
129 case ARM::QPR_VFP2RegClassID:
130 return ARM::Q2;
131 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S2;
132 }
133 break;
134 case 3:
135 switch (RegClassID) {
136 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R3;
137 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
138 case ARM::DPR_VFP2RegClassID:
139 return ARM::D3;
140 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
141 case ARM::QPR_VFP2RegClassID:
142 return ARM::Q3;
143 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S3;
144 }
145 break;
146 case 4:
147 switch (RegClassID) {
148 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R4;
149 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
150 case ARM::DPR_VFP2RegClassID:
151 return ARM::D4;
152 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q4;
153 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S4;
154 }
155 break;
156 case 5:
157 switch (RegClassID) {
158 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R5;
159 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
160 case ARM::DPR_VFP2RegClassID:
161 return ARM::D5;
162 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q5;
163 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S5;
164 }
165 break;
166 case 6:
167 switch (RegClassID) {
168 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R6;
169 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
170 case ARM::DPR_VFP2RegClassID:
171 return ARM::D6;
172 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q6;
173 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S6;
174 }
175 break;
176 case 7:
177 switch (RegClassID) {
178 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R7;
179 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
180 case ARM::DPR_VFP2RegClassID:
181 return ARM::D7;
182 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q7;
183 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S7;
184 }
185 break;
186 case 8:
187 switch (RegClassID) {
188 case ARM::GPRRegClassID: return ARM::R8;
189 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D8;
190 case ARM::QPRRegClassID: return ARM::Q8;
191 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S8;
192 }
193 break;
194 case 9:
195 switch (RegClassID) {
196 case ARM::GPRRegClassID: return ARM::R9;
197 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D9;
198 case ARM::QPRRegClassID: return ARM::Q9;
199 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S9;
200 }
201 break;
202 case 10:
203 switch (RegClassID) {
204 case ARM::GPRRegClassID: return ARM::R10;
205 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D10;
206 case ARM::QPRRegClassID: return ARM::Q10;
207 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S10;
208 }
209 break;
210 case 11:
211 switch (RegClassID) {
212 case ARM::GPRRegClassID: return ARM::R11;
213 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D11;
214 case ARM::QPRRegClassID: return ARM::Q11;
215 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S11;
216 }
217 break;
218 case 12:
219 switch (RegClassID) {
220 case ARM::GPRRegClassID: return ARM::R12;
221 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D12;
222 case ARM::QPRRegClassID: return ARM::Q12;
223 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S12;
224 }
225 break;
226 case 13:
227 switch (RegClassID) {
228 case ARM::GPRRegClassID: return ARM::SP;
229 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D13;
230 case ARM::QPRRegClassID: return ARM::Q13;
231 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S13;
232 }
233 break;
234 case 14:
235 switch (RegClassID) {
236 case ARM::GPRRegClassID: return ARM::LR;
237 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D14;
238 case ARM::QPRRegClassID: return ARM::Q14;
239 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S14;
240 }
241 break;
242 case 15:
243 switch (RegClassID) {
244 case ARM::GPRRegClassID: return ARM::PC;
245 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D15;
246 case ARM::QPRRegClassID: return ARM::Q15;
247 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S15;
248 }
249 break;
250 case 16:
251 switch (RegClassID) {
252 case ARM::DPRRegClassID: return ARM::D16;
253 case ARM::SPRRegClassID: return ARM::S16;
254 }
255 break;
256 case 17:
257 switch (RegClassID) {
258 case ARM::DPRRegClassID: return ARM::D17;
259 case ARM::SPRRegClassID: return ARM::S17;
260 }
261 break;
262 case 18:
263 switch (RegClassID) {
264 case ARM::DPRRegClassID: return ARM::D18;
265 case ARM::SPRRegClassID: return ARM::S18;
266 }
267 break;
268 case 19:
269 switch (RegClassID) {
270 case ARM::DPRRegClassID: return ARM::D19;
271 case ARM::SPRRegClassID: return ARM::S19;
272 }
273 break;
274 case 20:
275 switch (RegClassID) {
276 case ARM::DPRRegClassID: return ARM::D20;
277 case ARM::SPRRegClassID: return ARM::S20;
278 }
279 break;
280 case 21:
281 switch (RegClassID) {
282 case ARM::DPRRegClassID: return ARM::D21;
283 case ARM::SPRRegClassID: return ARM::S21;
284 }
285 break;
286 case 22:
287 switch (RegClassID) {
288 case ARM::DPRRegClassID: return ARM::D22;
289 case ARM::SPRRegClassID: return ARM::S22;
290 }
291 break;
292 case 23:
293 switch (RegClassID) {
294 case ARM::DPRRegClassID: return ARM::D23;
295 case ARM::SPRRegClassID: return ARM::S23;
296 }
297 break;
298 case 24:
299 switch (RegClassID) {
300 case ARM::DPRRegClassID: return ARM::D24;
301 case ARM::SPRRegClassID: return ARM::S24;
302 }
303 break;
304 case 25:
305 switch (RegClassID) {
306 case ARM::DPRRegClassID: return ARM::D25;
307 case ARM::SPRRegClassID: return ARM::S25;
308 }
309 break;
310 case 26:
311 switch (RegClassID) {
312 case ARM::DPRRegClassID: return ARM::D26;
313 case ARM::SPRRegClassID: return ARM::S26;
314 }
315 break;
316 case 27:
317 switch (RegClassID) {
318 case ARM::DPRRegClassID: return ARM::D27;
319 case ARM::SPRRegClassID: return ARM::S27;
320 }
321 break;
322 case 28:
323 switch (RegClassID) {
324 case ARM::DPRRegClassID: return ARM::D28;
325 case ARM::SPRRegClassID: return ARM::S28;
326 }
327 break;
328 case 29:
329 switch (RegClassID) {
330 case ARM::DPRRegClassID: return ARM::D29;
331 case ARM::SPRRegClassID: return ARM::S29;
332 }
333 break;
334 case 30:
335 switch (RegClassID) {
336 case ARM::DPRRegClassID: return ARM::D30;
337 case ARM::SPRRegClassID: return ARM::S30;
338 }
339 break;
340 case 31:
341 switch (RegClassID) {
342 case ARM::DPRRegClassID: return ARM::D31;
343 case ARM::SPRRegClassID: return ARM::S31;
344 }
345 break;
346 }
347 llvm_unreachable("Invalid (RegClassID, RawRegister) combination");
348 }
349
350 // This is efficient but fragile.
351 /*
352 // See ARMGenRegisterInfo.h.inc for more info.
353 static const TargetRegisterClass* const ARMRegisterClasses[] = {
354 NULL,
355 &ARM::CCRRegClass, // CCRRegClassID = 1,
356 &ARM::DPRRegClass, // DPRRegClassID = 2,
357 &ARM::DPR_8RegClass, // DPR_8RegClassID = 3,
358 &ARM::DPR_VFP2RegClass, // DPR_VFP2RegClassID = 4,
359 &ARM::GPRRegClass, // GPRRegClassID = 5,
360 &ARM::QPRRegClass, // QPRRegClassID = 6,
361 &ARM::QPR_8RegClass, // QPR_8RegClassID = 7,
362 &ARM::QPR_VFP2RegClass, // QPR_VFP2RegClassID = 8,
363 &ARM::SPRRegClass, // SPRRegClassID = 9,
364 &ARM::SPR_8RegClass, // SPR_8RegClassID = 10,
365 &ARM::SPR_INVALIDRegClass, // SPR_INVALIDRegClassID = 11,
366 &ARM::tGPRRegClass, // tGPRRegClassID = 12
367 };
368
369 // Return the register enum given register class id and raw register value.
370 static unsigned getRegisterEnum(unsigned RegClassID, unsigned RawRegister) {
371 assert(RegClassID < array_lengthof(ARMRegisterClasses) &&
372 "Register Class ID out of range");
373 return ARMRegisterClasses[RegClassID]->getRegister(RawRegister);
374 }
375 */
376
377 /// DisassembleFP - DisassembleFP points to a function that disassembles an insn
378 /// and builds the MCOperand list upon disassembly. It returns false on failure
379 /// or true on success. The number of operands added is updated upon success.
380 typedef bool (*DisassembleFP)(MCInst &MI, unsigned Opcode, uint32_t insn,
381 unsigned short NumOps, unsigned &NumOpsAdded);
382
383 ///////////////////////////////
384 // //
385 // Utility Functions //
386 // //
387 ///////////////////////////////
388
389 // Extract/Decode Rd: Inst{15-12}.
390 static inline unsigned decodeRd(uint32_t insn) {
391 return (insn >> ARMII::RegRdShift) & ARMII::GPRRegMask;
392 }
393
394 // Extract/Decode Rn: Inst{19-16}.
395 static inline unsigned decodeRn(uint32_t insn) {
396 return (insn >> ARMII::RegRnShift) & ARMII::GPRRegMask;
397 }
398
399 // Extract/Decode Rm: Inst{3-0}.
400 static inline unsigned decodeRm(uint32_t insn) {
401 return (insn & ARMII::GPRRegMask);
402 }
403
404 // Extract/Decode Rs: Inst{11-8}.
405 static inline unsigned decodeRs(uint32_t insn) {
406 return (insn >> ARMII::RegRsShift) & ARMII::GPRRegMask;
407 }
408
409 static inline unsigned getCondField(uint32_t insn) {
410 return (insn >> ARMII::CondShift);
411 }
412
413 static inline unsigned getIBit(uint32_t insn) {
414 return (insn >> ARMII::I_BitShift) & 1;
415 }
416
417 static inline unsigned getAM3IBit(uint32_t insn) {
418 return (insn >> ARMII::AM3_I_BitShift) & 1;
419 }
420
421 static inline unsigned getPBit(uint32_t insn) {
422 return (insn >> ARMII::P_BitShift) & 1;
423 }
424
425 static inline unsigned getUBit(uint32_t insn) {
426 return (insn >> ARMII::U_BitShift) & 1;
427 }
428
429 static inline unsigned getPUBits(uint32_t insn) {
430 return (insn >> ARMII::U_BitShift) & 3;
431 }
432
433 static inline unsigned getSBit(uint32_t insn) {
434 return (insn >> ARMII::S_BitShift) & 1;
435 }
436
437 static inline unsigned getWBit(uint32_t insn) {
438 return (insn >> ARMII::W_BitShift) & 1;
439 }
440
441 static inline unsigned getDBit(uint32_t insn) {
442 return (insn >> ARMII::D_BitShift) & 1;
443 }
444
445 static inline unsigned getNBit(uint32_t insn) {
446 return (insn >> ARMII::N_BitShift) & 1;
447 }
448
449 static inline unsigned getMBit(uint32_t insn) {
450 return (insn >> ARMII::M_BitShift) & 1;
451 }
452
453 namespace {
454 // Sign extend 5 bit number x to r.
455 // Usage: int r = signextend(x);
456 template inline T signextend(const T x) {
457 struct {T x:B;} s;
458 return s.x = x;
459 }
460 }
461
462 // See A8.4 Shifts applied to a register.
463 // A8.4.2 Register controlled shifts.
464 //
465 // getShiftOpcForBits - getShiftOpcForBits translates from the ARM encoding bits
466 // into llvm enums for shift opcode.
467 //
468 // A8-12: DecodeRegShift()
469 static inline ARM_AM::ShiftOpc getShiftOpcForBits(unsigned bits) {
470 switch (bits) {
471 default: assert(0 && "No such value");
472 case 0: return ARM_AM::lsl;
473 case 1: return ARM_AM::lsr;
474 case 2: return ARM_AM::asr;
475 case 3: return ARM_AM::ror;
476 }
477 }
478
479 // See A8.4 Shifts applied to a register.
480 // A8.4.1 Constant shifts.
481 //
482 // getImmShiftSE - getImmShiftSE translates from the raw ShiftOpc and raw Imm5
483 // encodings into the intended ShiftOpc and shift amount.
484 //
485 // A8-11: DecodeImmShift()
486 static inline void getImmShiftSE(ARM_AM::ShiftOpc &ShOp, unsigned &ShImm) {
487 // If type == 0b11 and imm5 == 0, we have an rrx, instead.
488 if (ShOp == ARM_AM::ror && ShImm == 0)
489 ShOp = ARM_AM::rrx;
490 // If (lsr or asr) and imm5 == 0, shift amount is 32.
491 if ((ShOp == ARM_AM::lsr || ShOp == ARM_AM::asr) && ShImm == 0)
492 ShImm = 32;
493 }
494
495 // getAMSubModeForBits - getAMSubModeForBits translates from the ARM encoding
496 // bits Inst{24-23} (P(24) and U(23)) into llvm enums for AMSubMode.
497 static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
498 switch (bits) {
499 default: assert(0 && "No such value");
500 case 1: return ARM_AM::ia; // P=0 U=1
501 case 3: return ARM_AM::ib; // P=1 U=1
502 case 0: return ARM_AM::da; // P=0 U=0
503 case 2: return ARM_AM::db; // P=1 U=0
504 }
505 }
506
507 ////////////////////////////////////////////
508 // //
509 // Disassemble function definitions //
510 // //
511 ////////////////////////////////////////////
512
513 /// There is a separate Disassemble*Frm function entry for disassembly of an ARM
514 /// instr into a list of MCOperands in the appropriate order, with possible dst,
515 /// followed by possible src(s).
516 ///
517 /// The processing of the predicate, and the 'S' modifier bit, if MI modifies
518 /// the CPSR, is factored into ARMBasicMCBuilder's class method named
519 /// TryPredicateAndSBitModifier.
520
521 static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
522 unsigned short NumOps, unsigned &NumOpsAdded) {
523
524 if (Opcode == ARM::Int_MemBarrierV7 || Opcode == ARM::Int_SyncBarrierV7)
525 return true;
526
527 assert(0 && "Unexpected pseudo instruction!");
528 return false;
529 }
530
531 // Multiply Instructions.
532 // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS:
533 // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
534 //
535 // MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT:
536 // Rd{19-16} Rn{3-0} Rm{11-8}
537 //
538 // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT:
539 // RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8}
540 //
541 // The mapping of the multiply registers to the "regular" ARM registers, where
542 // there are convenience decoder functions, is:
543 //
544 // Inst{15-12} => Rd
545 // Inst{19-16} => Rn
546 // Inst{3-0} => Rm
547 // Inst{11-8} => Rs
548 static bool DisassembleMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
549 unsigned short NumOps, unsigned &NumOpsAdded) {
550
551 const TargetInstrDesc &TID = ARMInsts[Opcode];
552 unsigned short NumDefs = TID.getNumDefs();
553 const TargetOperandInfo *OpInfo = TID.OpInfo;
554 unsigned &OpIdx = NumOpsAdded;
555
556 OpIdx = 0;
557
558 assert(NumDefs > 0 && "NumDefs should be greater than 0 for MulFrm");
559 assert(NumOps >= 3
560 && OpInfo[0].RegClass == ARM::GPRRegClassID
561 && OpInfo[1].RegClass == ARM::GPRRegClassID
562 && OpInfo[2].RegClass == ARM::GPRRegClassID);
563
564 // Instructions with two destination registers have RdLo{15-12} first.
565 if (NumDefs == 2) {
566 assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID);
567 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
568 decodeRd(insn))));
569 ++OpIdx;
570 }
571
572 // The destination register: RdHi{19-16} or Rd{19-16}.
573 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
574 decodeRn(insn))));
575
576 // The two src regsiters: Rn{3-0}, then Rm{11-8}.
577 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
578 decodeRm(insn))));
579 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
580 decodeRs(insn))));
581 OpIdx += 3;
582
583 // Many multiply instructions (e.g., MLA) have three src registers.
584 // The third register operand is Ra{15-12}.
585 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
586 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
587 decodeRd(insn))));
588 ++OpIdx;
589 }
590
591 return true;
592 }
593
594 // Helper routines for disassembly of coprocessor instructions.
595
596 static bool LdStCopOpcode(unsigned Opcode) {
597 if ((Opcode >= ARM::LDC2L_OFFSET && Opcode <= ARM::LDC_PRE) ||
598 (Opcode >= ARM::STC2L_OFFSET && Opcode <= ARM::STC_PRE))
599 return true;
600 return false;
601 }
602 static bool CoprocessorOpcode(unsigned Opcode) {
603 if (LdStCopOpcode(Opcode))
604 return true;
605
606 switch (Opcode) {
607 default:
608 return false;
609 case ARM::CDP: case ARM::CDP2:
610 case ARM::MCR: case ARM::MCR2: case ARM::MRC: case ARM::MRC2:
611 case ARM::MCRR: case ARM::MCRR2: case ARM::MRRC: case ARM::MRRC2:
612 return true;
613 }
614 }
615 static inline unsigned GetCoprocessor(uint32_t insn) {
616 return slice(insn, 11, 8);
617 }
618 static inline unsigned GetCopOpc1(uint32_t insn, bool CDP) {
619 return CDP ? slice(insn, 23, 20) : slice(insn, 23, 21);
620 }
621 static inline unsigned GetCopOpc2(uint32_t insn) {
622 return slice(insn, 7, 5);
623 }
624 static inline unsigned GetCopOpc(uint32_t insn) {
625 return slice(insn, 7, 4);
626 }
627 // Most of the operands are in immediate forms, except Rd and Rn, which are ARM
628 // core registers.
629 //
630 // CDP, CDP2: cop opc1 CRd CRn CRm opc2
631 //
632 // MCR, MCR2, MRC, MRC2: cop opc1 Rd CRn CRm opc2
633 //
634 // MCRR, MCRR2, MRRC, MRRc2: cop opc Rd Rn CRm
635 //
636 // LDC_OFFSET, LDC_PRE, LDC_POST: cop CRd Rn R0 [+/-]imm8:00
637 // and friends
638 // STC_OFFSET, STC_PRE, STC_POST: cop CRd Rn R0 [+/-]imm8:00
639 // and friends
640 // <-- addrmode2 -->
641 //
642 // LDC_OPTION: cop CRd Rn imm8
643 // and friends
644 // STC_OPTION: cop CRd Rn imm8
645 // and friends
646 //
647 static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
648 unsigned short NumOps, unsigned &NumOpsAdded) {
649
650 assert(NumOps >= 5);
651
652 unsigned &OpIdx = NumOpsAdded;
653 bool OneCopOpc = (Opcode == ARM::MCRR || Opcode == ARM::MCRR2 ||
654 Opcode == ARM::MRRC || Opcode == ARM::MRRC2);
655 // CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
656 bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
657 bool LdStCop = LdStCopOpcode(Opcode);
658
659 OpIdx = 0;
660
661 MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
662
663 if (LdStCop) {
664 // Unindex if P:W = 0b00 --> _OPTION variant
665 unsigned PW = getPBit(insn) << 1 | getWBit(insn);
666
667 MI.addOperand(MCOperand::CreateImm(decodeRd(insn)));
668
669 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
670 decodeRn(insn))));
671
672 if (PW) {
673 MI.addOperand(MCOperand::CreateReg(0));
674 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
675 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
676 ARM_AM::no_shift);
677 MI.addOperand(MCOperand::CreateImm(Offset));
678 OpIdx = 5;
679 } else {
680 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
681 OpIdx = 4;
682 }
683 } else {
684 MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
685 : GetCopOpc1(insn, NoGPR)));
686
687 MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
688 : MCOperand::CreateReg(
689 getRegisterEnum(ARM::GPRRegClassID,
690 decodeRd(insn))));
691
692 MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
693 getRegisterEnum(ARM::GPRRegClassID,
694 decodeRn(insn)))
695 : MCOperand::CreateImm(decodeRn(insn)));
696
697 MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
698
699 OpIdx = 5;
700
701 if (!OneCopOpc) {
702 MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));
703 ++OpIdx;
704 }
705 }
706
707 return true;
708 }
709
710 // Branch Instructions.
711 // BLr9: SignExtend(Imm24:'00', 32)
712 // Bcc, BLr9_pred: SignExtend(Imm24:'00', 32) Pred0 Pred1
713 // SMC: ZeroExtend(imm4, 32)
714 // SVC: ZeroExtend(Imm24, 32)
715 //
716 // Various coprocessor instructions are assigned BrFrm arbitrarily.
717 // Delegates to DisassembleCoprocessor() helper function.
718 //
719 // MRS/MRSsys: Rd
720 // MSR/MSRsys: Rm mask=Inst{19-16}
721 // BXJ: Rm
722 // MSRi/MSRsysi: so_imm
723 // SRSW/SRS: addrmode4:$addr mode_imm
724 // RFEW/RFE: addrmode4:$addr Rn
725 static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
726 unsigned short NumOps, unsigned &NumOpsAdded) {
727
728 if (CoprocessorOpcode(Opcode))
729 return DisassembleCoprocessor(MI, Opcode, insn, NumOps, NumOpsAdded);
730
731 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
732
733 // MRS and MRSsys take one GPR reg Rd.
734 if (Opcode == ARM::MRS || Opcode == ARM::MRSsys) {
735 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID);
736 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
737 decodeRd(insn))));
738 NumOpsAdded = 1;
739 return true;
740 }
741 // BXJ takes one GPR reg Rm.
742 if (Opcode == ARM::BXJ) {
743 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID);
744 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
745 decodeRm(insn))));
746 NumOpsAdded = 1;
747 return true;
748 }
749 // MSR and MSRsys take one GPR reg Rm, followed by the mask.
750 if (Opcode == ARM::MSR || Opcode == ARM::MSRsys) {
751 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID);
752 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
753 decodeRm(insn))));
754 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
755 NumOpsAdded = 2;
756 return true;
757 }
758 // MSRi and MSRsysi take one so_imm operand, followed by the mask.
759 if (Opcode == ARM::MSRi || Opcode == ARM::MSRsysi) {
760 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
761 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
762 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
763 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
764 unsigned Imm = insn & 0xFF;
765 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
766 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
767 NumOpsAdded = 2;
768 return true;
769 }
770 // SRSW and SRS requires addrmode4:$addr for ${addr:submode}, followed by the
771 // mode immediate (Inst{4-0}).
772 if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
773 Opcode == ARM::RFEW || Opcode == ARM::RFE) {
774 // ARMInstPrinter::printAddrMode4Operand() prints special mode string
775 // if the base register is SP; so don't set ARM::SP.
776 MI.addOperand(MCOperand::CreateReg(0));
777 bool WB = (Opcode == ARM::SRSW);
778 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
779 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode, WB)));
780
781 if (Opcode == ARM::SRSW || Opcode == ARM::SRS)
782 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
783 else
784 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
785 decodeRn(insn))));
786 NumOpsAdded = 3;
787 return true;
788 }
789
790 assert(Opcode == ARM::Bcc || Opcode == ARM::BLr9 || Opcode == ARM::BLr9_pred
791 || Opcode == ARM::SMC || Opcode == ARM::SVC);
792
793 assert(NumOps >= 1 && OpInfo[0].RegClass == 0);
794
795 int Imm32 = 0;
796 if (Opcode == ARM::SMC) {
797 // ZeroExtend(imm4, 32) where imm24 = Inst{3-0}.
798 Imm32 = slice(insn, 3, 0);
799 } else if (Opcode == ARM::SVC) {
800 // ZeroExtend(imm24, 32) where imm24 = Inst{23-0}.
801 Imm32 = slice(insn, 23, 0);
802 } else {
803 // SignExtend(imm24:'00', 32) where imm24 = Inst{23-0}.
804 unsigned Imm26 = slice(insn, 23, 0) << 2;
805 Imm32 = signextend(Imm26);
806
807 // When executing an ARM instruction, PC reads as the address of the current
808 // instruction plus 8. The assembler subtracts 8 from the difference
809 // between the branch instruction and the target address, disassembler has
810 // to add 8 to compensate.
811 Imm32 += 8;
812 }
813
814 MI.addOperand(MCOperand::CreateImm(Imm32));
815 NumOpsAdded = 1;
816
817 return true;
818 }
819
820 // Misc. Branch Instructions.
821 // BR_JTadd, BR_JTr, BR_JTm
822 // BLXr9, BXr9
823 // BRIND, BX_RET
824 static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
825 unsigned short NumOps, unsigned &NumOpsAdded) {
826
827 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
828 unsigned &OpIdx = NumOpsAdded;
829
830 OpIdx = 0;
831
832 // BX_RET has only two predicate operands, do an early return.
833 if (Opcode == ARM::BX_RET)
834 return true;
835
836 // BLXr9 and BRIND take one GPR reg.
837 if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) {
838 assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID);
839 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
840 decodeRm(insn))));
841 OpIdx = 1;
842 return true;
843 }
844
845 // BR_JTadd is an ADD with Rd = PC, (Rn, Rm) as the target and index regs.
846 if (Opcode == ARM::BR_JTadd) {
847 // InOperandList with GPR:$target and GPR:$idx regs.
848
849 assert(NumOps == 4);
850 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
851 decodeRn(insn))));
852 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
853 decodeRm(insn))));
854
855 // Fill in the two remaining imm operands to signify build completion.
856 MI.addOperand(MCOperand::CreateImm(0));
857 MI.addOperand(MCOperand::CreateImm(0));
858
859 OpIdx = 4;
860 return true;
861 }
862
863 // BR_JTr is a MOV with Rd = PC, and Rm as the source register.
864 if (Opcode == ARM::BR_JTr) {
865 // InOperandList with GPR::$target reg.
866
867 assert(NumOps == 3);
868 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
869 decodeRm(insn))));
870
871 // Fill in the two remaining imm operands to signify build completion.
872 MI.addOperand(MCOperand::CreateImm(0));
873 MI.addOperand(MCOperand::CreateImm(0));
874
875 OpIdx = 3;
876 return true;
877 }
878
879 // BR_JTm is an LDR with Rt = PC.
880 if (Opcode == ARM::BR_JTm) {
881 // This is the reg/reg form, with base reg followed by +/- reg shop imm.
882 // See also ARMAddressingModes.h (Addressing Mode #2).
883
884 assert(NumOps == 5 && getIBit(insn) == 1);
885 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
886 decodeRn(insn))));
887
888 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
889
890 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
891 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
892 decodeRm(insn))));
893 // Inst{6-5} encodes the shift opcode.
894 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
895 // Inst{11-7} encodes the imm5 shift amount.
896 unsigned ShImm = slice(insn, 11, 7);
897
898 // A8.4.1. Possible rrx or shift amount of 32...
899 getImmShiftSE(ShOp, ShImm);
900 MI.addOperand(MCOperand::CreateImm(
901 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
902
903 // Fill in the two remaining imm operands to signify build completion.
904 MI.addOperand(MCOperand::CreateImm(0));
905 MI.addOperand(MCOperand::CreateImm(0));
906
907 OpIdx = 5;
908 return true;
909 }
910
911 assert(0 && "Unexpected BrMiscFrm Opcode");
912 return false;
913 }
914
915 static inline uint32_t getBFCInvMask(uint32_t insn) {
916 uint32_t lsb = slice(insn, 11, 7);
917 uint32_t msb = slice(insn, 20, 16);
918 uint32_t Val = 0;
919 assert(lsb <= msb && "Encoding error: lsb > msb");
920 for (uint32_t i = lsb; i <= msb; ++i)
921 Val |= (1 << i);
922 return ~Val;
923 }
924
925 static inline bool SaturateOpcode(unsigned Opcode) {
926 switch (Opcode) {
927 case ARM::SSATlsl: case ARM::SSATasr: case ARM::SSAT16:
928 case ARM::USATlsl: case ARM::USATasr: case ARM::USAT16:
929 return true;
930 default:
931 return false;
932 }
933 }
934
935 static inline unsigned decodeSaturatePos(unsigned Opcode, uint32_t insn) {
936 switch (Opcode) {
937 case ARM::SSATlsl:
938 case ARM::SSATasr:
939 return slice(insn, 20, 16) + 1;
940 case ARM::SSAT16:
941 return slice(insn, 19, 16) + 1;
942 case ARM::USATlsl:
943 case ARM::USATasr:
944 return slice(insn, 20, 16);
945 case ARM::USAT16:
946 return slice(insn, 19, 16);
947 default:
948 llvm_unreachable("Invalid opcode passed in");
949 return 0;
950 }
951 }
952
953 // A major complication is the fact that some of the saturating add/subtract
954 // operations have Rd Rm Rn, instead of the "normal" Rd Rn Rm.
955 // They are QADD, QDADD, QDSUB, and QSUB.
956 static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
957 unsigned short NumOps, unsigned &NumOpsAdded) {
958
959 const TargetInstrDesc &TID = ARMInsts[Opcode];
960 unsigned short NumDefs = TID.getNumDefs();
961 bool isUnary = isUnaryDP(TID.TSFlags);
962 const TargetOperandInfo *OpInfo = TID.OpInfo;
963 unsigned &OpIdx = NumOpsAdded;
964
965 OpIdx = 0;
966
967 // Disassemble register def if there is one.
968 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
969 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
970 decodeRd(insn))));
971 ++OpIdx;
972 }
973
974 // Now disassemble the src operands.
975 if (OpIdx >= NumOps)
976 return false;
977
978 // SSAT/SSAT16/USAT/USAT16 has imm operand after Rd.
979 if (SaturateOpcode(Opcode)) {
980 MI.addOperand(MCOperand::CreateImm(decodeSaturatePos(Opcode, insn)));
981
982 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
983 decodeRm(insn))));
984
985 if (Opcode == ARM::SSAT16 || Opcode == ARM::USAT16) {
986 OpIdx += 2;
987 return true;
988 }
989
990 // For SSAT operand reg (Rm) has been disassembled above.
991 // Now disassemble the shift amount.
992
993 // Inst{11-7} encodes the imm5 shift amount.
994 unsigned ShAmt = slice(insn, 11, 7);
995
996 // A8.6.183. Possible ASR shift amount of 32...
997 if (Opcode == ARM::SSATasr && ShAmt == 0)
998 ShAmt = 32;
999
1000 MI.addOperand(MCOperand::CreateImm(ShAmt));
1001
1002 OpIdx += 3;
1003 return true;
1004 }
1005
1006 // Special-case handling of BFC/BFI/SBFX/UBFX.
1007 if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
1008 // TIED_TO operand skipped for BFC and Inst{3-0} (Reg) for BFI.
1009 MI.addOperand(MCOperand::CreateReg(Opcode == ARM::BFC ? 0
1010 : getRegisterEnum(ARM::GPRRegClassID,
1011 decodeRm(insn))));
1012 MI.addOperand(MCOperand::CreateImm(getBFCInvMask(insn)));
1013 OpIdx += 2;
1014 return true;
1015 }
1016 if (Opcode == ARM::SBFX || Opcode == ARM::UBFX) {
1017 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
1018 decodeRm(insn))));
1019 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 7)));
1020 MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16) + 1));
1021 OpIdx += 3;
1022 return true;
1023 }
1024
1025 bool RmRn = (Opcode == ARM::QADD || Opcode == ARM::QDADD ||
1026 Opcode == ARM::QDSUB || Opcode == ARM::QSUB);
1027
1028 // BinaryDP has an Rn operand.
1029 if (!isUnary) {
1030 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID);
1031 MI.addOperand(MCOperand::CreateReg(
1032 getRegisterEnum(ARM::GPRRegClassID,
1033 RmRn ? decodeRm(insn) : decodeRn(insn))));
1034 ++OpIdx;
1035 }
1036
1037 // If this is a two-address operand, skip it, e.g., MOVCCr operand 1.
1038 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
1039 MI.addOperand(MCOperand::CreateReg(0));
1040 ++OpIdx;
1041 }
1042
1043 // Now disassemble operand 2.
1044 if (OpIdx >= NumOps)
1045 return false;
1046
1047 if (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
1048 // We have a reg/reg form.
1049 // Assert disabled because saturating operations, e.g., A8.6.127 QASX, are
1050 // routed here as well.
1051 // assert(getIBit(insn) == 0 && "I_Bit != '0' reg/reg form");
1052 MI.addOperand(MCOperand::CreateReg(
1053 getRegisterEnum(ARM::GPRRegClassID,
1054 RmRn? decodeRn(insn) : decodeRm(insn))));
1055 ++OpIdx;
1056 } else if (Opcode == ARM::MOVi16 || Opcode == ARM::MOVTi16) {
1057 // We have an imm16 = imm4:imm12 (imm4=Inst{19:16}, imm12 = Inst{11:0}).
1058 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
1059 unsigned Imm16 = slice(insn, 19, 16) << 12 | slice(insn, 11, 0);
1060 MI.addOperand(MCOperand::CreateImm(Imm16));
1061 ++OpIdx;
1062 } else {
1063 // We have a reg/imm form.
1064 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
1065 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
1066 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
1067 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
1068 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
1069 unsigned Imm = insn & 0xFF;
1070 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
1071 ++OpIdx;
1072 }
1073
1074 return true;
1075 }
1076
1077 static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1078 unsigned short NumOps, unsigned &NumOpsAdded) {
1079
1080 const TargetInstrDesc &TID = ARMInsts[Opcode];
1081 unsigned short NumDefs = TID.getNumDefs();
1082 bool isUnary = isUnaryDP(TID.TSFlags);
1083 const TargetOperandInfo *OpInfo = TID.OpInfo;
1084 unsigned &OpIdx = NumOpsAdded;
1085
1086 OpIdx = 0;
1087
1088 // Disassemble register def if there is one.
1089 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
1090 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
1091 decodeRd(insn))));
1092 ++OpIdx;
1093 }
1094
1095 // Disassemble the src operands.
1096 if (OpIdx >= NumOps)
1097 return false;
1098
1099 // BinaryDP has an Rn operand.
1100 if (!isUnary) {
1101 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID);
1102 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(ARM::GPRRegClassID,
1103 decodeRn(insn))));
1104 ++OpIdx;
1105 }
1106
1107 // If this is a two-address operand, skip it, e.g., MOVCCs operand 1.
1108 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
1109 MI.addOperand(MCOperand::CreateReg(0));
1110 ++OpIdx;