llvm.org GIT mirror llvm / d302773
fix visitShift to properly zero extend the shift amount if the provided operand is narrower than the shift register. Doing an anyext provides undefined bits in the top part of the register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125457 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 9 years ago
3 changed file(s) with 20 addition(s) and 23 deletion(s). Raw diff Collapse all Expand all
24232423 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
24242424 SDValue Op1 = getValue(I.getOperand(0));
24252425 SDValue Op2 = getValue(I.getOperand(1));
2426 if (!I.getType()->isVectorTy() &&
2427 Op2.getValueType() != TLI.getShiftAmountTy()) {
2426
2427 MVT ShiftTy = TLI.getShiftAmountTy();
2428 unsigned ShiftSize = ShiftTy.getSizeInBits();
2429 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2430
2431 // Coerce the shift amount to the right type if we can.
2432 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2433 DebugLoc DL = getCurDebugLoc();
2434
24282435 // If the operand is smaller than the shift count type, promote it.
2429 EVT PTy = TLI.getPointerTy();
2430 EVT STy = TLI.getShiftAmountTy();
2431 if (STy.bitsGT(Op2.getValueType()))
2432 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2433 TLI.getShiftAmountTy(), Op2);
2436 MVT PtrTy = TLI.getPointerTy();
2437 if (ShiftSize > Op2Size)
2438 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2439
24342440 // If the operand is larger than the shift count type but the shift
24352441 // count type has enough bits to represent any shift value, truncate
24362442 // it now. This is a common case and it exposes the truncate to
24372443 // optimization early.
2438 else if (STy.getSizeInBits() >=
2439 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2440 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2441 TLI.getShiftAmountTy(), Op2);
2442 // Otherwise we'll need to temporarily settle for some other
2443 // convenient type; type legalization will make adjustments as
2444 // needed.
2445 else if (PTy.bitsLT(Op2.getValueType()))
2446 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2447 TLI.getPointerTy(), Op2);
2448 else if (PTy.bitsGT(Op2.getValueType()))
2449 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2450 TLI.getPointerTy(), Op2);
2444 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2445 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2446 // Otherwise we'll need to temporarily settle for some other convenient
2447 // type. Type legalization will make adjustments as needed.
2448 else
2449 Op2 = DAG.getZExtOrTrunc(Op2, DL, PtrTy);
24512450 }
24522451
24532452 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
33 ; RUN: grep {shl } %t1.s | count 9
44 ; RUN: grep {shli } %t1.s | count 3
55 ; RUN: grep {xshw } %t1.s | count 5
6 ; RUN: grep {and } %t1.s | count 5
6 ; RUN: grep {and } %t1.s | count 14
77 ; RUN: grep {andi } %t1.s | count 2
88 ; RUN: grep {rotmi } %t1.s | count 2
99 ; RUN: grep {rotqmbyi } %t1.s | count 1
1212 ; FUN: andi
1313 ; FUN: add
1414 ; FUN: bnei
15 ; SHT-NOT: andi
1615 ; SHT-NOT: bnei
1716
1817 ret i8 %tmp.1
4948 ; FUN: andi
5049 ; FUN: add
5150 ; FUN: bnei
52 ; SHT-NOT: andi
5351 ; SHT-NOT: bnei
5452
5553 ret i16 %tmp.1