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Merging r317204 and r318172: ------------------------------------------------------------------------ r317204 | sdardis | 2017-11-02 05:47:22 -0700 (Thu, 02 Nov 2017) | 15 lines [mips] Use register scavenging with MSA. MSA stores and loads to the stack are more likely to require an emergency GPR spill slot due to the smaller offsets available with those instructions. Handle this by overestimating the size of the stack by determining the largest offset presuming that all callee save registers are spilled and accounting of incoming arguments when determining whether an emergency spill slot is required. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39056 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r318172 | sdardis | 2017-11-14 11:11:45 -0800 (Tue, 14 Nov 2017) | 5 lines [mips] Simplify test for 5.0.1 (NFC) Simplify testing that an emergency spill slot is used when MSA is used so that it can be included in the 5.0.1 release. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318191 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 9 months ago
4 changed file(s) with 264 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
106106 return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);
107107 }
108108
109 // Estimate the size of the stack, including the incoming arguments. We need to
110 // account for register spills, local objects, reserved call frame and incoming
111 // arguments. This is required to determine the largest possible positive offset
112 // from $sp so that it can be determined if an emergency spill slot for stack
113 // addresses is required.
109114 uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const {
110115 const MachineFrameInfo &MFI = MF.getFrameInfo();
111116 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
112117
113 int64_t Offset = 0;
118 int64_t Size = 0;
114119
115 // Iterate over fixed sized objects.
120 // Iterate over fixed sized objects which are incoming arguments.
116121 for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
117 Offset = std::max(Offset, -MFI.getObjectOffset(I));
122 if (MFI.getObjectOffset(I) > 0)
123 Size += MFI.getObjectSize(I);
118124
119125 // Conservatively assume all callee-saved registers will be saved.
120126 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
121 unsigned Size = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
122 Offset = alignTo(Offset + Size, Size);
127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
128 Size = alignTo(Size + RegSize, RegSize);
123129 }
124130
125 unsigned MaxAlign = MFI.getMaxAlignment();
126
127 // Check that MaxAlign is not zero if there is a stack object that is not a
128 // callee-saved spill.
129 assert(!MFI.getObjectIndexEnd() || MaxAlign);
130
131 // Iterate over other objects.
132 for (unsigned I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I)
133 Offset = alignTo(Offset + MFI.getObjectSize(I), MaxAlign);
134
135 // Call frame.
136 if (MFI.adjustsStack() && hasReservedCallFrame(MF))
137 Offset = alignTo(Offset + MFI.getMaxCallFrameSize(),
138 std::max(MaxAlign, getStackAlignment()));
139
140 return alignTo(Offset, getStackAlignment());
131 // Get the size of the rest of the frame objects and any possible reserved
132 // call frame, accounting for alignment.
133 return Size + MFI.estimateStackSize(MF);
141134 }
142135
143136 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
893893 }
894894
895895 // Set scavenging frame index if necessary.
896 uint64_t MaxSPOffset = MF.getInfo()->getIncomingArgSize() +
897 estimateStackSize(MF);
898
899 if (isInt<16>(MaxSPOffset))
896 uint64_t MaxSPOffset = estimateStackSize(MF);
897
898 // MSA has a minimum offset of 10 bits signed. If there is a variable
899 // sized object on the stack, the estimation cannot account for it.
900 if (isIntN(STI.hasMSA() ? 10 : 16, MaxSPOffset) &&
901 !MF.getFrameInfo().hasVarSizedObjects())
900902 return;
901903
902904 const TargetRegisterClass &RC =
0 # RUN: llc %s -start-after=shrink-wrap -march=mips64 -mcpu=mips64r6 -mattr=+fp64,+msa -o /dev/null
1
2 # Test that estimated size of the stack leads to the creation of an emergency
3 # spill when MSA is in use. Previously, this test case would fail during
4 # register scavenging due to the lack of a spill slot.
5 --- |
6 define inreg { i64, i64 } @test(i64 inreg %a.coerce0, i64 inreg %a.coerce1, i64 inreg %b.coerce0, i64 inreg %b.coerce1, i32 signext %c) #0 {
7 entry:
8 %retval = alloca <16 x i8>, align 16
9 %a = alloca <16 x i8>, align 16
10 %b = alloca <16 x i8>, align 16
11 %a.addr = alloca <16 x i8>, align 16
12 %b.addr = alloca <16 x i8>, align 16
13 %c.addr = alloca i32, align 4
14 %g = alloca <16 x i8>*, align 8
15 %d = alloca i8*, align 8
16 %0 = bitcast <16 x i8>* %a to { i64, i64 }*
17 %1 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %0, i32 0, i32 0
18 store i64 %a.coerce0, i64* %1, align 16
19 %2 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %0, i32 0, i32 1
20 store i64 %a.coerce1, i64* %2, align 8
21 %a1 = load <16 x i8>, <16 x i8>* %a, align 16
22 %3 = bitcast <16 x i8>* %b to { i64, i64 }*
23 %4 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %3, i32 0, i32 0
24 store i64 %b.coerce0, i64* %4, align 16
25 %5 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %3, i32 0, i32 1
26 store i64 %b.coerce1, i64* %5, align 8
27 %b2 = load <16 x i8>, <16 x i8>* %b, align 16
28 store <16 x i8> %a1, <16 x i8>* %a.addr, align 16
29 store <16 x i8> %b2, <16 x i8>* %b.addr, align 16
30 store i32 %c, i32* %c.addr, align 4
31 %6 = alloca i8, i64 6400, align 16
32 %7 = bitcast i8* %6 to <16 x i8>*
33 store <16 x i8>* %7, <16 x i8>** %g, align 8
34 %8 = load <16 x i8>*, <16 x i8>** %g, align 8
35 call void @h(<16 x i8>* %b.addr, <16 x i8>* %8)
36 %9 = load <16 x i8>*, <16 x i8>** %g, align 8
37 %10 = bitcast <16 x i8>* %9 to i8*
38 store i8* %10, i8** %d, align 8
39 %11 = load <16 x i8>, <16 x i8>* %a.addr, align 16
40 %12 = load i8*, i8** %d, align 8
41 %arrayidx = getelementptr inbounds i8, i8* %12, i64 0
42 %13 = load i8, i8* %arrayidx, align 1
43 %conv = sext i8 %13 to i32
44 %14 = call <16 x i8> @llvm.mips.fill.b(i32 %conv)
45 %add = add <16 x i8> %11, %14
46 %15 = load i8*, i8** %d, align 8
47 %arrayidx3 = getelementptr inbounds i8, i8* %15, i64 1
48 %16 = load i8, i8* %arrayidx3, align 1
49 %conv4 = sext i8 %16 to i32
50 %17 = call <16 x i8> @llvm.mips.fill.b(i32 %conv4)
51 %add5 = add <16 x i8> %add, %17
52 %18 = load <16 x i8>, <16 x i8>* %b.addr, align 16
53 %add6 = add <16 x i8> %18, %add5
54 store <16 x i8> %add6, <16 x i8>* %b.addr, align 16
55 %19 = load <16 x i8>, <16 x i8>* %b.addr, align 16
56 store <16 x i8> %19, <16 x i8>* %retval, align 16
57 %20 = bitcast <16 x i8>* %retval to { i64, i64 }*
58 %21 = load { i64, i64 }, { i64, i64 }* %20, align 16
59 ret { i64, i64 } %21
60 }
61
62 declare void @h(<16 x i8>*, <16 x i8>*)
63
64 declare <16 x i8> @llvm.mips.fill.b(i32)
65
66 declare void @llvm.stackprotector(i8*, i8**)
67
68 ...
69 ---
70 name: test
71 alignment: 3
72 exposesReturnsTwice: false
73 legalized: false
74 regBankSelected: false
75 selected: false
76 tracksRegLiveness: true
77 registers:
78 liveins:
79 - { reg: '%a0_64', virtual-reg: '' }
80 - { reg: '%a1_64', virtual-reg: '' }
81 - { reg: '%a2_64', virtual-reg: '' }
82 - { reg: '%a3_64', virtual-reg: '' }
83 - { reg: '%t0_64', virtual-reg: '' }
84 frameInfo:
85 isFrameAddressTaken: false
86 isReturnAddressTaken: false
87 hasStackMap: false
88 hasPatchPoint: false
89 stackSize: 0
90 offsetAdjustment: 0
91 maxAlignment: 16
92 adjustsStack: false
93 hasCalls: true
94 stackProtector: ''
95 maxCallFrameSize: 4294967295
96 hasOpaqueSPAdjustment: false
97 hasVAStart: false
98 hasMustTailInVarArgFunc: false
99 savePoint: ''
100 restorePoint: ''
101 fixedStack:
102 stack:
103 - { id: 0, name: retval, type: default, offset: 0, size: 16, alignment: 16,
104 callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
105 - { id: 1, name: a, type: default, offset: 0, size: 16, alignment: 16,
106 callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
107 - { id: 2, name: b, type: default, offset: 0, size: 16, alignment: 16,
108 callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
109 - { id: 3, name: a.addr, type: default, offset: 0, size: 16, alignment: 16,
110 callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
111 - { id: 4, name: b.addr, type: default, offset: 0, size: 16, alignment: 16,
112 callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
113 - { id: 5, name: c.addr, type: default, offset: 0, size: 4, alignment: 4,
114 callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
115 - { id: 6, name: g, type: default, offset: 0, size: 8, alignment: 8,
116 callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
117 - { id: 7, name: d, type: default, offset: 0, size: 8, alignment: 8,
118 callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
119 - { id: 8, name: '', type: default, offset: 0, size: 6400,
120 alignment: 16, callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
121 constants:
122 body: |
123 bb.0.entry:
124 liveins: %a0_64, %a1_64, %a2_64, %a3_64, %t0_64
125
126 SD killed %a0_64, %stack.1.a, 0 :: (store 8 into %ir.1, align 16)
127 SD killed %a1_64, %stack.1.a, 8 :: (store 8 into %ir.2)
128 %w0 = LD_B %stack.1.a, 0 :: (dereferenceable load 16 from %ir.a)
129 SD killed %a2_64, %stack.2.b, 0 :: (store 8 into %ir.4, align 16)
130 SD killed %a3_64, %stack.2.b, 8 :: (store 8 into %ir.5)
131 %w1 = LD_B %stack.2.b, 0 :: (dereferenceable load 16 from %ir.b)
132 ST_B killed %w0, %stack.3.a.addr, 0 :: (store 16 into %ir.a.addr)
133 ST_B killed %w1, %stack.4.b.addr, 0 :: (store 16 into %ir.b.addr)
134 SW %t0, %stack.5.c.addr, 0, implicit killed %t0_64 :: (store 4 into %ir.c.addr)
135 %at_64 = LEA_ADDiu64 %stack.8, 0
136 SD killed %at_64, %stack.6.g, 0 :: (store 8 into %ir.g)
137 %a1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
138 ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
139 %a0_64 = LEA_ADDiu64 %stack.4.b.addr, 0
140 JAL @h, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %a1_64, implicit-def %sp
141 ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
142 %at_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
143 %v0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
144 %v1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
145 %a0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
146 %a1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
147 %a2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
148 %a3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
149 %t0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
150 %t1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
151 %t2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
152 %t3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
153 %t4_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
154 %t5_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
155 %t6_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
156 %t7_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
157 %s0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
158 %s1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
159 %s2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
160 %s3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
161 %s4_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
162 %s5_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
163 %s6_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
164 %s7_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
165 %t8_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
166 %t9_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
167 %ra_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
168 %w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load 16 from %ir.a.addr)
169 SD %at_64, %stack.7.d, 0 :: (store 8 into %ir.d)
170 SD %v0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
171 SD %v1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
172 SD %a0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
173 SD %a1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
174 SD %a2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
175 SD %a3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
176 SD %t0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
177 SD %t1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
178 SD %t2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
179 SD %t3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
180 SD %t4_64, %stack.7.d, 0 :: (store 8 into %ir.d)
181 SD %t5_64, %stack.7.d, 0 :: (store 8 into %ir.d)
182 SD %t6_64, %stack.7.d, 0 :: (store 8 into %ir.d)
183 SD %t7_64, %stack.7.d, 0 :: (store 8 into %ir.d)
184 SD %s0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
185 SD %s1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
186 SD %s2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
187 SD %s3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
188 SD %s4_64, %stack.7.d, 0 :: (store 8 into %ir.d)
189 SD %s5_64, %stack.7.d, 0 :: (store 8 into %ir.d)
190 SD %s6_64, %stack.7.d, 0 :: (store 8 into %ir.d)
191 SD %s7_64, %stack.7.d, 0 :: (store 8 into %ir.d)
192 SD %t8_64, %stack.7.d, 0 :: (store 8 into %ir.d)
193 SD %t9_64, %stack.7.d, 0 :: (store 8 into %ir.d)
194 SD %ra_64, %stack.7.d, 0 :: (store 8 into %ir.d)
195 %at_64 = LD %stack.7.d, 0 :: (dereferenceable load 8 from %ir.d)
196 %v0 = LB %at_64, 0 :: (load 1 from %ir.arrayidx)
197 %w1 = FILL_B killed %v0
198 %w0 = ADDV_B killed %w0, killed %w1
199 %at = LB killed %at_64, 1 :: (load 1 from %ir.arrayidx3)
200 %w1 = FILL_B killed %at
201 %w0 = ADDV_B killed %w0, killed %w1
202 %w1 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
203 %w0 = ADDV_B killed %w1, killed %w0
204 ST_B killed %w0, %stack.4.b.addr, 0 :: (store 16 into %ir.b.addr)
205 %w0 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
206 ST_B killed %w0, %stack.0.retval, 0 :: (store 16 into %ir.retval)
207 %v0_64 = LD %stack.0.retval, 0 :: (dereferenceable load 8 from %ir.20, align 16)
208 %v1_64 = LD %stack.0.retval, 8 :: (dereferenceable load 8 from %ir.20 + 8, align 16)
209 RetRA implicit %v0_64, implicit %v1_64
210
211 ...
1717 ; MIPS32-AE: loadstore_v16i8_just_under_simm10:
1818
1919 %1 = alloca <16 x i8>
20 %2 = alloca [496 x i8] ; Push the frame right up to 512 bytes
20 %2 = alloca [492 x i8] ; Push the frame--acounting for the emergency spill
21 ; slot--right up to 512 bytes
2122
2223 %3 = load volatile <16 x i8>, <16 x i8>* %1
2324 ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 496($sp)
3233 ; MIPS32-AE: loadstore_v16i8_just_over_simm10:
3334
3435 %1 = alloca <16 x i8>
35 %2 = alloca [497 x i8] ; Push the frame just over 512 bytes
36 %2 = alloca [497 x i8] ; Push the frame--acounting for the emergency spill
37 ; slot--right up to 512 bytes
3638
3739 %3 = load volatile <16 x i8>, <16 x i8>* %1
3840 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
4951 ; MIPS32-AE: loadstore_v16i8_just_under_simm16:
5052
5153 %1 = alloca <16 x i8>
52 %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
54 %2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill
55 ; slot--right up to 32768 bytes
5356
5457 %3 = load volatile <16 x i8>, <16 x i8>* %1
5558 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
6871 ; MIPS32-AE: loadstore_v16i8_just_over_simm16:
6972
7073 %1 = alloca <16 x i8>
71 %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
74 %2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill
75 ; slot--just over 32768 bytes
7276
7377 %3 = load volatile <16 x i8>, <16 x i8>* %1
7478 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
120124 ; MIPS32-AE: loadstore_v8i16_just_under_simm10:
121125
122126 %1 = alloca <8 x i16>
123 %2 = alloca [1008 x i8] ; Push the frame right up to 1024 bytes
127 %2 = alloca [1004 x i8] ; Push the frame--acounting for the emergency spill
128 ; slot--right up to 1024 bytes
124129
125130 %3 = load volatile <8 x i16>, <8 x i16>* %1
126131 ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 1008($sp)
135140 ; MIPS32-AE: loadstore_v8i16_just_over_simm10:
136141
137142 %1 = alloca <8 x i16>
138 %2 = alloca [1009 x i8] ; Push the frame just over 1024 bytes
143 %2 = alloca [1009 x i8] ; Push the frame--acounting for the emergency spill
144 ; slot--just over 1024 bytes
139145
140146 %3 = load volatile <8 x i16>, <8 x i16>* %1
141147 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
152158 ; MIPS32-AE: loadstore_v8i16_just_under_simm16:
153159
154160 %1 = alloca <8 x i16>
155 %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
161 %2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill
162 ; slot--right up to 32768 bytes
156163
157164 %3 = load volatile <8 x i16>, <8 x i16>* %1
158165 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
171178 ; MIPS32-AE: loadstore_v8i16_just_over_simm16:
172179
173180 %1 = alloca <8 x i16>
174 %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
181 %2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill
182 ; slot--just over 32768 bytes
175183
176184 %3 = load volatile <8 x i16>, <8 x i16>* %1
177185 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
223231 ; MIPS32-AE: loadstore_v4i32_just_under_simm10:
224232
225233 %1 = alloca <4 x i32>
226 %2 = alloca [2032 x i8] ; Push the frame right up to 2048 bytes
234 %2 = alloca [2028 x i8] ; Push the frame--acounting for the emergency spill
235 ; slot--right up to 2048 bytes
227236
228237 %3 = load volatile <4 x i32>, <4 x i32>* %1
229238 ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 2032($sp)
238247 ; MIPS32-AE: loadstore_v4i32_just_over_simm10:
239248
240249 %1 = alloca <4 x i32>
241 %2 = alloca [2033 x i8] ; Push the frame just over 2048 bytes
250 %2 = alloca [2033 x i8] ; Push the frame--acounting for the emergency spill
251 ; slot--just over 2048 bytes
242252
243253 %3 = load volatile <4 x i32>, <4 x i32>* %1
244254 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
255265 ; MIPS32-AE: loadstore_v4i32_just_under_simm16:
256266
257267 %1 = alloca <4 x i32>
258 %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
268 %2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill
269 ; slot-- right up to 32768 bytes
259270
260271 %3 = load volatile <4 x i32>, <4 x i32>* %1
261272 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
274285 ; MIPS32-AE: loadstore_v4i32_just_over_simm16:
275286
276287 %1 = alloca <4 x i32>
277 %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
288 %2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill
289 ; slot--just over 32768 bytes
278290
279291 %3 = load volatile <4 x i32>, <4 x i32>* %1
280292 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
326338 ; MIPS32-AE: loadstore_v2i64_just_under_simm10:
327339
328340 %1 = alloca <2 x i64>
329 %2 = alloca [4080 x i8] ; Push the frame right up to 4096 bytes
330
341 %2 = alloca [4076 x i8] ; Push the frame--acounting for the emergency spill
342 ; slot--right up to 4096 bytes
331343 %3 = load volatile <2 x i64>, <2 x i64>* %1
332344 ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 4080($sp)
333345 store volatile <2 x i64> %3, <2 x i64>* %1
341353 ; MIPS32-AE: loadstore_v2i64_just_over_simm10:
342354
343355 %1 = alloca <2 x i64>
344 %2 = alloca [4081 x i8] ; Push the frame just over 4096 bytes
356 %2 = alloca [4081 x i8] ; Push the frame--acounting for the emergency spill
357 ; slot--just over 4096 bytes
345358
346359 %3 = load volatile <2 x i64>, <2 x i64>* %1
347360 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
358371 ; MIPS32-AE: loadstore_v2i64_just_under_simm16:
359372
360373 %1 = alloca <2 x i64>
361 %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
374 %2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill
375 ; slot--right up to 32768 bytes
362376
363377 %3 = load volatile <2 x i64>, <2 x i64>* %1
364378 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
377391 ; MIPS32-AE: loadstore_v2i64_just_over_simm16:
378392
379393 %1 = alloca <2 x i64>
380 %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
394 %2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill
395 ; slot--just over 32768 bytes
381396
382397 %3 = load volatile <2 x i64>, <2 x i64>* %1
383398 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768