llvm.org GIT mirror llvm / d1b456b
[NFC] fix trivial typos in comments and documents "to to" -> "to" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323628 91177308-0d34-0410-b5e6-96231b3b80d8 Hiroshi Inoue 1 year, 6 months ago
23 changed file(s) with 23 addition(s) and 23 deletion(s). Raw diff Collapse all Expand all
323323 extremely old versions of GCC. These steps attempt to help you upgrade you
324324 compiler even on such a system. However, if at all possible, we encourage you
325325 to use a recent version of a distribution with a modern system compiler that
326 meets these requirements. Note that it is tempting to to install a prior
326 meets these requirements. Note that it is tempting to install a prior
327327 version of Clang and libc++ to be the host compiler, however libc++ was not
328328 well tested or set up to build on Linux until relatively recently. As
329329 a consequence, this guide suggests just using libstdc++ and a modern GCC as the
4343
4444 auto TargetTriple = sys::getDefaultTargetTriple();
4545
46 LLVM doesn't require us to to link in all the target
46 LLVM doesn't require us to link in all the target
4747 functionality. For example, if we're just using the JIT, we don't need
4848 the assembly printers. Similarly, if we're only targeting certain
4949 architectures, we can only link in the functionality for those
274274 enqueueUsers(GEPI);
275275 }
276276
277 // No-op intrinsics which we know don't escape the pointer to to logic in
277 // No-op intrinsics which we know don't escape the pointer to logic in
278278 // some other function.
279279 void visitDbgInfoIntrinsic(DbgInfoIntrinsic &I) {}
280280 void visitMemIntrinsic(MemIntrinsic &I) {}
677677 const SCEV *LHS, const SCEV *RHS);
678678
679679 /// Test whether the backedge of the loop is protected by a conditional
680 /// between LHS and RHS. This is used to to eliminate casts.
680 /// between LHS and RHS. This is used to eliminate casts.
681681 bool isLoopBackedgeGuardedByCond(const Loop *L, ICmpInst::Predicate Pred,
682682 const SCEV *LHS, const SCEV *RHS);
683683
2121 /// of an instruction should live. It asks the target which banks may be
2222 /// used for each operand of the instruction and what is the cost. Then,
2323 /// it chooses the solution which minimize the cost of the instruction plus
24 /// the cost of any move that may be needed to to the values into the right
24 /// the cost of any move that may be needed to the values into the right
2525 /// register bank.
2626 /// In other words, the cost for an instruction on a register bank RegBank
2727 /// is: Cost of I on RegBank plus the sum of the cost for bringing the
4242 raw_fd_ostream OS;
4343
4444 public:
45 /// This constructor's arguments are passed to to raw_fd_ostream's
45 /// This constructor's arguments are passed to raw_fd_ostream's
4646 /// constructor.
4747 ToolOutputFile(StringRef Filename, std::error_code &EC,
4848 sys::fs::OpenFlags Flags);
72667266 continue;
72677267
72687268 // If this is a memory input, and if the operand is not indirect, do what we
7269 // need to to provide an address for the memory input.
7269 // need to provide an address for the memory input.
72707270 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
72717271 !OpInfo.isIndirect) {
72727272 assert((OpInfo.isMultipleAlternative ||
19841984 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
19851985 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
19861986
1987 // Extend back to to 64-bits.
1987 // Extend back to 64-bits.
19881988 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
19891989 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
19901990
7878 cl::init(true),
7979 cl::Hidden);
8080
81 // Option to to control global loads scalarization
81 // Option to control global loads scalarization
8282 static cl::opt ScalarizeGlobal(
8383 "amdgpu-scalarize-global-loads",
8484 cl::desc("Enable global load scalarization"),
451451 // TODO: assert Regions are sorted descending by pressure
452452 const auto &ST = MF.getSubtarget();
453453 const auto Occ = Regions.front()->MaxPressure.getOccupancy(ST);
454 DEBUG(dbgs() << "Trying to to improve occupancy, target = " << TargetOcc
454 DEBUG(dbgs() << "Trying to improve occupancy, target = " << TargetOcc
455455 << ", current = " << Occ << '\n');
456456
457457 auto NewOcc = TargetOcc;
18361836
18371837 if (!MFI->isEntryFunction()) {
18381838 // Wait for any outstanding memory operations that the input registers may
1839 // depend on. We can't track them and it's better to to the wait after the
1839 // depend on. We can't track them and it's better to the wait after the
18401840 // costly call sequence.
18411841
18421842 // TODO: Could insert earlier and schedule more liberally with operations
686686
687687 if (!MFI->isEntryFunction()) {
688688 // Wait for any outstanding memory operations that the input registers may
689 // depend on. We can't track them and it's better to to the wait after the
689 // depend on. We can't track them and it's better to the wait after the
690690 // costly call sequence.
691691
692692 // TODO: Could insert earlier and schedule more liberally with operations
218218 // result consists of 4 bits, indicating lt, eq, gt and un (unordered),
219219 // only one of which will be set. The result is generated by fcmpu
220220 // instruction. However, bc instruction only inspects one of the first 3
221 // bits, so when un is set, bc instruction may jump to to an undesired
221 // bits, so when un is set, bc instruction may jump to an undesired
222222 // place.
223223 //
224224 // More specifically, if we expect an unordered comparison and un is set, we
26742674 (FrameReg == X86::EBP && VT == MVT::i32)) &&
26752675 "Invalid Frame Register!");
26762676
2677 // Always make a copy of the frame register to to a vreg first, so that we
2677 // Always make a copy of the frame register to a vreg first, so that we
26782678 // never directly reference the frame register (the TwoAddressInstruction-
26792679 // Pass doesn't like that).
26802680 unsigned SrcReg = createResultReg(RC);
1391613916 return insert128BitVector(V1, Subvec, V2Index * 2, DAG, DL);
1391713917 }
1391813918
13919 // Try to lower to to vshuf64x2/vshuf32x4.
13919 // Try to lower to vshuf64x2/vshuf32x4.
1392013920 SDValue Ops[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT)};
1392113921 unsigned PermMask = 0;
1392213922 // Insure elements came from the same Op.
569569 // The ides is inspired from:
570570 // "Partial Redundancy Elimination in SSA Form"
571571 // ROBERT KENNEDY, SUN CHAN, SHIN-MING LIU, RAYMOND LO, PENG TU and FRED CHOW
572 // They use similar idea in the forward graph to to find fully redundant and
572 // They use similar idea in the forward graph to find fully redundant and
573573 // partially redundant expressions, here it is used in the inverse graph to
574574 // find fully anticipable instructions at merge point (post-dominator in
575575 // the inverse CFG).
16741674 }
16751675
16761676 // Step 3: Note that the population count is exactly the trip count of the
1677 // loop in question, which enable us to to convert the loop from noncountable
1677 // loop in question, which enable us to convert the loop from noncountable
16781678 // loop into a countable one. The benefit is twofold:
16791679 //
16801680 // - If the loop only counts population, the entire loop becomes dead after
2121 ret void
2222 }
2323
24 ; There are two objects, so one requires padding to to be correctly
24 ; There are two objects, so one requires padding to be correctly
2525 ; aligned after the other.
2626
2727 ; (38 -> 48) + 38 = 92
None ; The purpose of this test to to verify that the fltused symbol is emitted when
0 ; The purpose of this test to verify that the fltused symbol is emitted when
11 ; any function is called with floating point arguments on Windows. And that it
22 ; is not emitted otherwise.
33
None ; The purpose of this test to to verify that the fltused symbol is emitted when
0 ; The purpose of this test to verify that the fltused symbol is emitted when
11 ; any function is called with floating point arguments on Windows. And that it
22 ; is not emitted otherwise.
33
77
88
99 // Test that on ELF:
10 // 1. the debug info has a relocation to debug_abbrev and one to to debug_line.
10 // 1. the debug info has a relocation to debug_abbrev and one to debug_line.
1111 // 2. the debug_aranges has relocations to text and debug_line.
1212
1313
5050
5151
5252 ; The 'test2_' prefixed functions test that we can discover the last callsite
53 ; bonus after having inlined the prior call site. For this to to work, we need
53 ; bonus after having inlined the prior call site. For this to work, we need
5454 ; a callsite dependent cost so we have a trivial predicate guarding all the
5555 ; cost, and set that in a particular direction.
5656
495495 FALSE,
496496 thread_id);
497497 GTEST_CHECK_(thread != NULL);
498 // We need to to pass a valid thread ID pointer into CreateThread for it
498 // We need to pass a valid thread ID pointer into CreateThread for it
499499 // to work correctly under Win98.
500500 DWORD watcher_thread_id;
501501 HANDLE watcher_thread = ::CreateThread(