llvm.org GIT mirror llvm / d1311ac
[ARM] Introduce the 'sevl' instruction in ARMv8. This also removes the restriction on the immediate field of the 'hint' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8 Joey Gouly 6 years ago
16 changed file(s) with 59 addition(s) and 57 deletion(s). Raw diff Collapse all Expand all
110110 [IntrNoMem]>;
111111 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
112112 [IntrNoMem]>;
113
114 //===----------------------------------------------------------------------===//
115 // HINT
116 def int_arm_sevl : Intrinsic<[], []>;
113117
114118 //===----------------------------------------------------------------------===//
115119 // Advanced SIMD (NEON)
593593 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
594594 def imm0_3 : Operand { let ParserMatchClass = Imm0_3AsmOperand; }
595595
596 /// imm0_4 predicate - Immediate in the range [0,4].
597 def Imm0_4AsmOperand : ImmAsmOperand
598 {
599 let Name = "Imm0_4";
600 let DiagnosticType = "ImmRange0_4";
601 }
602 def imm0_4 : Operand, ImmLeaf= 0 && Imm < 5; }]> {
603 let ParserMatchClass = Imm0_4AsmOperand;
604 let DecoderMethod = "DecodeImm0_4";
605 }
606
607596 /// imm0_7 predicate - Immediate in the range [0,7].
608597 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
609598 def imm0_7 : Operand, ImmLeaf
16761665 [(ARMcallseq_start timm:$amt)]>;
16771666 }
16781667
1679 def HINT : AI<(outs), (ins imm0_4:$imm), MiscFrm, NoItinerary,
1668 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
16801669 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1681 bits<3> imm;
1682 let Inst{27-3} = 0b0011001000001111000000000;
1683 let Inst{2-0} = imm;
1670 bits<8> imm;
1671 let Inst{27-8} = 0b00110010000011110000;
1672 let Inst{7-0} = imm;
16841673 }
16851674
16861675 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
16881677 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
16891678 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
16901679 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1680 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1681
1682 def : Pat<(int_arm_sevl), (HINT 5)>;
16911683
16921684 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
16931685 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
287287 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
288288 T1SystemEncoding<0x40>, // A8.6.157
289289 Requires<[IsThumb2]>;
290
291 def tSEVL : T1pI<(outs), (ins), NoItinerary, "sevl", "", [(int_arm_sevl)]>,
292 T1SystemEncoding<0x50>,
293 Requires<[IsThumb2, HasV8]>;
294
290295
291296 // The imm operand $val can be used by a debugger to store more information
292297 // about the breakpoint.
36513651
36523652 // A6.3.4 Branches and miscellaneous control
36533653 // Table A6-14 Change Processor State, and hint instructions
3654 def t2HINT : T2I<(outs), (ins imm0_4:$imm), NoItinerary, "hint", "\t$imm",[]> {
3654 def t2HINT : T2I<(outs), (ins imm0_255:$imm), NoItinerary, "hint", "\t$imm",[]> {
36553655 bits<3> imm;
36563656 let Inst{31-3} = 0b11110011101011111000000000000;
36573657 let Inst{2-0} = imm;
36583658 }
36593659
3660 def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_4:$imm, pred:$p)>;
3660 def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_255:$imm, pred:$p)>;
36613661 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
36623662 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
36633663 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
36643664 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
36653665 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
3666 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p)> {
3667 let Predicates = [IsThumb2, HasV8];
3668 }
36663669
36673670 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
36683671 bits<4> opt;
678678 int64_t Value = CE->getValue();
679679 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
680680 }
681 bool isImm0_4() const {
682 if (!isImm()) return false;
683 const MCConstantExpr *CE = dyn_cast(getImm());
684 if (!CE) return false;
685 int64_t Value = CE->getValue();
686 return Value >= 0 && Value < 5;
687 }
688681 bool isImm0_1020s4() const {
689682 if (!isImm()) return false;
690683 const MCConstantExpr *CE = dyn_cast(getImm());
76867679 return Error(IDLoc, "instruction variant requires ARMv6 or later");
76877680 case Match_RequiresThumb2:
76887681 return Error(IDLoc, "instruction variant requires Thumb2");
7689 case Match_ImmRange0_4: {
7690 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7691 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7692 return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7693 }
76947682 case Match_ImmRange0_15: {
76957683 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
76967684 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8383 case 2: O << "\twfe"; break;
8484 case 3: O << "\twfi"; break;
8585 case 4: O << "\tsev"; break;
86 case 5:
87 if ((getAvailableFeatures() & ARM::HasV8Ops)) {
88 O << "\tsevl";
89 break;
90 } // Fallthrough for non-v8
8691 default:
8792 // Anything else should just print normally.
8893 printInstruction(MI, O);
88 call void @llvm.arm.dsb(i32 15)
99 ; CHECK: dsb ishld
1010 call void @llvm.arm.dsb(i32 9)
11 ; CHECK: sevl
12 tail call void @llvm.arm.sevl() nounwind
1113 ret void
1214 }
1315
1416 declare void @llvm.arm.dmb(i32)
1517 declare void @llvm.arm.dsb(i32)
18 declare void @llvm.arm.sevl() nounwind
4949 @ CHECK-V7: error: invalid operand for instruction
5050 @ CHECK-V7: error: invalid operand for instruction
5151 @ CHECK-V7: error: invalid operand for instruction
52
53 @------------------------------------------------------------------------------
54 @ SEVL
55 @------------------------------------------------------------------------------
56 sevl
57
58 @ CHECK: sevl @ encoding: [0x05,0xf0,0x20,0xe3]
29272927 hint #2
29282928 hint #1
29292929 hint #0
2930 hint #255
29302931
29312932 @ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
29322933 @ CHECK: wfehi @ encoding: [0x02,0xf0,0x20,0x83]
29392940 @ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
29402941 @ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3]
29412942 @ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3]
2943 @ CHECK: hint #255 @ encoding: [0xff,0xf0,0x20,0xe3]
6868 @ CHECK-V7: error: invalid operand for instruction
6969 @ CHECK-V7: error: invalid operand for instruction
7070 @ CHECK-V7: error: invalid operand for instruction
71
72 @------------------------------------------------------------------------------
73 @ SEVL
74 @------------------------------------------------------------------------------
75 sevl
76 sevl.w
77 it ge
78 sevlge
79
80 @ CHECK-V8: sevl @ encoding: [0x50,0xbf]
81 @ CHECK-V8: sevl.w @ encoding: [0xaf,0xf3,0x05,0x80]
82 @ CHECK-V8: it ge @ encoding: [0xa8,0xbf]
83 @ CHECK-V8: sevlge @ encoding: [0x50,0xbf]
+0
-7
test/MC/ARM/invalid-hint-arm.s less more
None @ RUN: not llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 < %s 2>&1 | FileCheck %s
1
2 hint #5
3 hint #100
4
5 @ CHECK: error: immediate operand must be in the range [0,4]
6 @ CHECK: error: immediate operand must be in the range [0,4]
+0
-9
test/MC/ARM/invalid-hint-thumb.s less more
None @ RUN: not llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 < %s 2>&1 | FileCheck %s
1
2 hint #5
3 hint.w #5
4 hint #100
5
6 @ CHECK: error: immediate operand must be in the range [0,4]
7 @ CHECK: error: immediate operand must be in the range [0,4]
8 @ CHECK: error: immediate operand must be in the range [0,4]
1717 # CHECK: dmb oshld
1818 # CHECK: dmb nshld
1919 # CHECK: dmb ld
20
21 0x05 0xf0 0x20 0xe3
22 # CHECK: sevl
24192419 # CHECK: wfilt
24202420 # CHECK: yield
24212421 # CHECK: yieldne
2422 # CHECK: hint #5
24222423
24232424 0x02 0xf0 0x20 0xe3
24242425 0x02 0xf0 0x20 0x83
24262427 0x03 0xf0 0x20 0xb3
24272428 0x01 0xf0 0x20 0xe3
24282429 0x01 0xf0 0x20 0x13
2430 0x05 0xf0 0x20 0xe3
6767 #------------------------------------------------------------------------------
6868 # Undefined encoding space for hint instructions
6969 #------------------------------------------------------------------------------
70
71 [0x05 0xf0 0x20 0xe3]
72 # CHECK: invalid instruction encoding
73 # CHECK-NEXT: [0x05 0xf0 0x20 0xe3]
74
75 [0x41 0xf0 0x20 0xe3]
76 # CHECK: invalid instruction encoding
77 # CHECK-NEXT: [0x41 0xf0 0x20 0xe3]
7870
7971 # FIXME: is it "dbg #14" or not????
8072 [0xfe 0xf0 0x20 0xe3]
3636 # Undefined encoding space for hint instructions
3737 #------------------------------------------------------------------------------
3838
39 [0xaf 0xf3 0x05 0x80]
40 # CHECK: invalid instruction encoding
41 # CHECK-NEXT: [0xaf 0xf3 0x05 0x80]
42
39 [0x60 0xbf]
40 # CHECK: invalid instruction encoding
41 # CHECK-NEXT: [0x60 0xbf]
4342
4443 #------------------------------------------------------------------------------
4544 # Undefined encoding for it