llvm.org GIT mirror llvm / d11898d
[C++11] Add 'override' keyword to virtual methods that override their base class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203433 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
31 changed file(s) with 469 addition(s) and 476 deletion(s). Raw diff Collapse all Expand all
4848 static char ID;
4949 A15SDOptimizer() : MachineFunctionPass(ID) {}
5050
51 virtual bool runOnMachineFunction(MachineFunction &Fn);
52
53 virtual const char *getPassName() const {
51 bool runOnMachineFunction(MachineFunction &Fn) override;
52
53 const char *getPassName() const override {
5454 return "ARM A15 S->D optimizer";
5555 }
5656
4141 // if there is not such an opcode.
4242 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
4343
44 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
45 MachineBasicBlock::iterator &MBBI,
46 LiveVariables *LV) const;
44 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
45 MachineBasicBlock::iterator &MBBI,
46 LiveVariables *LV) const override;
4747
4848 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
4949 const ARMSubtarget &getSubtarget() const { return Subtarget; }
5050
5151 ScheduleHazardRecognizer *
5252 CreateTargetHazardRecognizer(const TargetMachine *TM,
53 const ScheduleDAG *DAG) const;
53 const ScheduleDAG *DAG) const override;
5454
5555 ScheduleHazardRecognizer *
5656 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
57 const ScheduleDAG *DAG) const;
57 const ScheduleDAG *DAG) const override;
5858
5959 // Branch analysis.
60 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
61 MachineBasicBlock *&FBB,
62 SmallVectorImpl &Cond,
63 bool AllowModify = false) const;
64 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
65 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
66 MachineBasicBlock *FBB,
67 const SmallVectorImpl &Cond,
68 DebugLoc DL) const;
69
70 virtual
71 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
60 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
61 MachineBasicBlock *&FBB,
62 SmallVectorImpl &Cond,
63 bool AllowModify = false) const override;
64 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
65 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
66 MachineBasicBlock *FBB,
67 const SmallVectorImpl &Cond,
68 DebugLoc DL) const override;
69
70 bool
71 ReverseBranchCondition(SmallVectorImpl &Cond) const override;
7272
7373 // Predication support.
74 bool isPredicated(const MachineInstr *MI) const;
74 bool isPredicated(const MachineInstr *MI) const override;
7575
7676 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
7777 int PIdx = MI->findFirstPredOperandIdx();
7979 : ARMCC::AL;
8080 }
8181
82 virtual
8382 bool PredicateInstruction(MachineInstr *MI,
84 const SmallVectorImpl &Pred) const;
85
86 virtual
83 const SmallVectorImpl &Pred) const override;
84
8785 bool SubsumesPredicate(const SmallVectorImpl &Pred1,
88 const SmallVectorImpl &Pred2) const;
89
90 virtual bool DefinesPredicate(MachineInstr *MI,
91 std::vector &Pred) const;
92
93 virtual bool isPredicable(MachineInstr *MI) const;
86 const SmallVectorImpl &Pred2) const override;
87
88 bool DefinesPredicate(MachineInstr *MI,
89 std::vector &Pred) const override;
90
91 bool isPredicable(MachineInstr *MI) const override;
9492
9593 /// GetInstSize - Returns the size of the specified MachineInstr.
9694 ///
9795 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
9896
99 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
100 int &FrameIndex) const;
101 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
102 int &FrameIndex) const;
103 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
104 int &FrameIndex) const;
105 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
106 int &FrameIndex) const;
107
108 virtual void copyPhysReg(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator I, DebugLoc DL,
110 unsigned DestReg, unsigned SrcReg,
111 bool KillSrc) const;
112
113 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
114 MachineBasicBlock::iterator MBBI,
115 unsigned SrcReg, bool isKill, int FrameIndex,
116 const TargetRegisterClass *RC,
117 const TargetRegisterInfo *TRI) const;
118
119 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
120 MachineBasicBlock::iterator MBBI,
121 unsigned DestReg, int FrameIndex,
122 const TargetRegisterClass *RC,
123 const TargetRegisterInfo *TRI) const;
124
125 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
126
127 virtual void reMaterialize(MachineBasicBlock &MBB,
128 MachineBasicBlock::iterator MI,
129 unsigned DestReg, unsigned SubIdx,
130 const MachineInstr *Orig,
131 const TargetRegisterInfo &TRI) const;
132
133 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
134
135 MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
97 unsigned isLoadFromStackSlot(const MachineInstr *MI,
98 int &FrameIndex) const override;
99 unsigned isStoreToStackSlot(const MachineInstr *MI,
100 int &FrameIndex) const override;
101 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
102 int &FrameIndex) const override;
103 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
104 int &FrameIndex) const override;
105
106 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
107 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
108 bool KillSrc) const override;
109
110 void storeRegToStackSlot(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator MBBI,
112 unsigned SrcReg, bool isKill, int FrameIndex,
113 const TargetRegisterClass *RC,
114 const TargetRegisterInfo *TRI) const override;
115
116 void loadRegFromStackSlot(MachineBasicBlock &MBB,
117 MachineBasicBlock::iterator MBBI,
118 unsigned DestReg, int FrameIndex,
119 const TargetRegisterClass *RC,
120 const TargetRegisterInfo *TRI) const override;
121
122 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
123
124 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
125 unsigned DestReg, unsigned SubIdx,
126 const MachineInstr *Orig,
127 const TargetRegisterInfo &TRI) const override;
128
129 MachineInstr *duplicate(MachineInstr *Orig,
130 MachineFunction &MF) const override;
131
132 MachineInstr *commuteInstruction(MachineInstr*,
133 bool=false) const override;
136134
137135 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
138136 unsigned SubIdx, unsigned State,
139137 const TargetRegisterInfo *TRI) const;
140138
141 virtual bool produceSameValue(const MachineInstr *MI0,
142 const MachineInstr *MI1,
143 const MachineRegisterInfo *MRI) const;
139 bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1,
140 const MachineRegisterInfo *MRI) const override;
144141
145142 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
146143 /// determine if two loads are loading from the same base address. It should
147144 /// only return true if the base pointers are the same and the only
148145 /// differences between the two addresses is the offset. It also returns the
149146 /// offsets by reference.
150 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
151 int64_t &Offset1, int64_t &Offset2)const;
147 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
148 int64_t &Offset2) const override;
152149
153150 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
154151 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
158155 /// from the common base address. It returns true if it decides it's desirable
159156 /// to schedule the two loads together. "NumLoads" is the number of loads that
160157 /// have already been scheduled after Load1.
161 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
162 int64_t Offset1, int64_t Offset2,
163 unsigned NumLoads) const;
164
165 virtual bool isSchedulingBoundary(const MachineInstr *MI,
166 const MachineBasicBlock *MBB,
167 const MachineFunction &MF) const;
168
169 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
170 unsigned NumCycles, unsigned ExtraPredCycles,
171 const BranchProbability &Probability) const;
172
173 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
174 unsigned NumT, unsigned ExtraT,
175 MachineBasicBlock &FMBB,
176 unsigned NumF, unsigned ExtraF,
177 const BranchProbability &Probability) const;
178
179 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
180 unsigned NumCycles,
181 const BranchProbability
182 &Probability) const {
158 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
159 int64_t Offset1, int64_t Offset2,
160 unsigned NumLoads) const override;
161
162 bool isSchedulingBoundary(const MachineInstr *MI,
163 const MachineBasicBlock *MBB,
164 const MachineFunction &MF) const override;
165
166 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
167 unsigned NumCycles, unsigned ExtraPredCycles,
168 const BranchProbability &Probability) const override;
169
170 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
171 unsigned ExtraT, MachineBasicBlock &FMBB,
172 unsigned NumF, unsigned ExtraF,
173 const BranchProbability &Probability) const override;
174
175 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
176 const BranchProbability &Probability) const override {
183177 return NumCycles == 1;
184178 }
185179
186 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
187 MachineBasicBlock &FMBB) const;
180 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
181 MachineBasicBlock &FMBB) const override;
188182
189183 /// analyzeCompare - For a comparison instruction, return the source registers
190184 /// in SrcReg and SrcReg2 if having two register operands, and the value it
191185 /// compares against in CmpValue. Return true if the comparison instruction
192186 /// can be analyzed.
193 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
194 unsigned &SrcReg2, int &CmpMask,
195 int &CmpValue) const;
187 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
188 unsigned &SrcReg2, int &CmpMask,
189 int &CmpValue) const override;
196190
197191 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
198192 /// that we can remove a "comparison with zero"; Remove a redundant CMP
199193 /// instruction if the flags can be updated in the same way by an earlier
200194 /// instruction such as SUB.
201 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
202 unsigned SrcReg2, int CmpMask, int CmpValue,
203 const MachineRegisterInfo *MRI) const;
204
205 virtual bool analyzeSelect(const MachineInstr *MI,
206 SmallVectorImpl &Cond,
207 unsigned &TrueOp, unsigned &FalseOp,
208 bool &Optimizable) const;
209
210 virtual MachineInstr *optimizeSelect(MachineInstr *MI, bool) const;
195 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
196 unsigned SrcReg2, int CmpMask, int CmpValue,
197 const MachineRegisterInfo *MRI) const override;
198
199 bool analyzeSelect(const MachineInstr *MI,
200 SmallVectorImpl &Cond,
201 unsigned &TrueOp, unsigned &FalseOp,
202 bool &Optimizable) const override;
203
204 MachineInstr *optimizeSelect(MachineInstr *MI, bool) const override;
211205
212206 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
213207 /// instruction, try to fold the immediate into the use instruction.
214 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
215 unsigned Reg, MachineRegisterInfo *MRI) const;
216
217 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
218 const MachineInstr *MI) const;
219
220 virtual
208 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
209 unsigned Reg, MachineRegisterInfo *MRI) const override;
210
211 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
212 const MachineInstr *MI) const override;
213
221214 int getOperandLatency(const InstrItineraryData *ItinData,
222215 const MachineInstr *DefMI, unsigned DefIdx,
223 const MachineInstr *UseMI, unsigned UseIdx) const;
224 virtual
216 const MachineInstr *UseMI,
217 unsigned UseIdx) const override;
225218 int getOperandLatency(const InstrItineraryData *ItinData,
226219 SDNode *DefNode, unsigned DefIdx,
227 SDNode *UseNode, unsigned UseIdx) const;
220 SDNode *UseNode, unsigned UseIdx) const override;
228221
229222 /// VFP/NEON execution domains.
230223 std::pair
231 getExecutionDomain(const MachineInstr *MI) const;
232 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
224 getExecutionDomain(const MachineInstr *MI) const override;
225 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
233226
234227 unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
235 const TargetRegisterInfo*) const;
228 const TargetRegisterInfo*) const override;
236229 void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
237 const TargetRegisterInfo *TRI) const;
230 const TargetRegisterInfo *TRI) const override;
238231 /// Get the number of addresses by LDM or VLDM or zero for unknown.
239232 unsigned getNumLDMAddresses(const MachineInstr *MI) const;
240233
263256 const MCInstrDesc &UseMCID,
264257 unsigned UseIdx, unsigned UseAlign) const;
265258
266 unsigned getPredicationCost(const MachineInstr *MI) const;
259 unsigned getPredicationCost(const MachineInstr *MI) const override;
267260
268261 unsigned getInstrLatency(const InstrItineraryData *ItinData,
269262 const MachineInstr *MI,
270 unsigned *PredCost = 0) const;
263 unsigned *PredCost = 0) const override;
271264
272265 int getInstrLatency(const InstrItineraryData *ItinData,
273 SDNode *Node) const;
266 SDNode *Node) const override;
274267
275268 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
276269 const MachineRegisterInfo *MRI,
277270 const MachineInstr *DefMI, unsigned DefIdx,
278 const MachineInstr *UseMI, unsigned UseIdx) const;
271 const MachineInstr *UseMI,
272 unsigned UseIdx) const override;
279273 bool hasLowDefLatency(const InstrItineraryData *ItinData,
280 const MachineInstr *DefMI, unsigned DefIdx) const;
274 const MachineInstr *DefMI,
275 unsigned DefIdx) const override;
281276
282277 /// verifyInstruction - Perform target specific instruction verification.
283 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
278 bool verifyInstruction(const MachineInstr *MI,
279 StringRef &ErrInfo) const override;
284280
285281 private:
286282 /// Modeling special VFP / NEON fp MLA / MLS hazards.
9999
100100 public:
101101 /// Code Generation virtual methods...
102 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
103 const uint32_t *getCallPreservedMask(CallingConv::ID) const;
102 const uint16_t *
103 getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
104 const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
104105 const uint32_t *getNoPreservedMask() const;
105106
106107 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
112113 /// Should return NULL in the case that the calling convention does not have
113114 /// this property
114115 const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
115
116 BitVector getReservedRegs(const MachineFunction &MF) const;
117116
118 const TargetRegisterClass*
119 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
120 const TargetRegisterClass*
121 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
117 BitVector getReservedRegs(const MachineFunction &MF) const override;
122118
123 const TargetRegisterClass*
124 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
119 const TargetRegisterClass *
120 getPointerRegClass(const MachineFunction &MF,
121 unsigned Kind = 0) const override;
122 const TargetRegisterClass *
123 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
124
125 const TargetRegisterClass *
126 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
125127
126128 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
127 MachineFunction &MF) const;
129 MachineFunction &MF) const override;
128130
129131 void getRegAllocationHints(unsigned VirtReg,
130132 ArrayRef Order,
131133 SmallVectorImpl &Hints,
132134 const MachineFunction &MF,
133 const VirtRegMap *VRM) const;
135 const VirtRegMap *VRM) const override;
134136
135137 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
136 MachineFunction &MF) const;
138 MachineFunction &MF) const override;
137139
138 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
140 bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override;
139141
140142 bool hasBasePointer(const MachineFunction &MF) const;
141143
142144 bool canRealignStack(const MachineFunction &MF) const;
143 bool needsStackRealignment(const MachineFunction &MF) const;
144 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
145 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
145 bool needsStackRealignment(const MachineFunction &MF) const override;
146 int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
147 int Idx) const override;
148 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
146149 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
147150 unsigned BaseReg, int FrameIdx,
148 int64_t Offset) const;
151 int64_t Offset) const override;
149152 void resolveFrameIndex(MachineBasicBlock::iterator I,
150 unsigned BaseReg, int64_t Offset) const;
151 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
153 unsigned BaseReg, int64_t Offset) const override;
154 bool isFrameOffsetLegal(const MachineInstr *MI,
155 int64_t Offset) const override;
152156
153157 bool cannotEliminateFrame(const MachineFunction &MF) const;
154158
155159 // Debug information queries.
156 unsigned getFrameRegister(const MachineFunction &MF) const;
160 unsigned getFrameRegister(const MachineFunction &MF) const override;
157161 unsigned getBaseRegister() const { return BasePtr; }
158162
159163 bool isLowRegister(unsigned Reg) const;
163167 /// specified immediate.
164168 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
165169 MachineBasicBlock::iterator &MBBI,
166 DebugLoc dl,
167 unsigned DestReg, unsigned SubIdx,
168 int Val,
169 ARMCC::CondCodes Pred = ARMCC::AL,
170 DebugLoc dl, unsigned DestReg, unsigned SubIdx,
171 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
170172 unsigned PredReg = 0,
171173 unsigned MIFlags = MachineInstr::NoFlags)const;
172174
173175 /// Code Generation virtual methods...
174 virtual bool mayOverrideLocalAssignment() const;
176 bool mayOverrideLocalAssignment() const override;
175177
176 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
178 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
177179
178 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
180 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
179181
180 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
182 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
181183
182 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
184 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
183185
184 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
185 int SPAdj, unsigned FIOperandNum,
186 RegScavenger *RS = NULL) const;
186 void eliminateFrameIndex(MachineBasicBlock::iterator II,
187 int SPAdj, unsigned FIOperandNum,
188 RegScavenger *RS = NULL) const override;
187189 };
188190
189191 } // end namespace llvm
5656 bool IsPIC;
5757 bool IsThumb;
5858
59 void getAnalysisUsage(AnalysisUsage &AU) const {
59 void getAnalysisUsage(AnalysisUsage &AU) const override {
6060 AU.addRequired();
6161 MachineFunctionPass::getAnalysisUsage(AU);
6262 }
7575 /// machine instructions.
7676 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
7777
78 bool runOnMachineFunction(MachineFunction &MF);
79
80 virtual const char *getPassName() const {
78 bool runOnMachineFunction(MachineFunction &MF) override;
79
80 const char *getPassName() const override {
8181 return "ARM Machine Code Emitter";
8282 }
8383
265265 static char ID;
266266 ARMConstantIslands() : MachineFunctionPass(ID) {}
267267
268 virtual bool runOnMachineFunction(MachineFunction &MF);
269
270 virtual const char *getPassName() const {
268 bool runOnMachineFunction(MachineFunction &MF) override;
269
270 const char *getPassName() const override {
271271 return "ARM constant island placement and branch shortening pass";
272272 }
273273
102102 bool isLSDA() const { return Kind == ARMCP::CPLSDA; }
103103 bool isMachineBasicBlock() const{ return Kind == ARMCP::CPMachineBasicBlock; }
104104
105 virtual unsigned getRelocationInfo() const { return 2; }
106
107 virtual int getExistingMachineCPValue(MachineConstantPool *CP,
108 unsigned Alignment);
109
110 virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
105 unsigned getRelocationInfo() const override { return 2; }
106
107 int getExistingMachineCPValue(MachineConstantPool *CP,
108 unsigned Alignment) override;
109
110 void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
111111
112112 /// hasSameValue - Return true if this ARM constpool value can share the same
113113 /// constantpool entry as another ARM constpool value.
119119 this->Modifier == A->Modifier;
120120 }
121121
122 virtual void print(raw_ostream &O) const;
122 void print(raw_ostream &O) const override;
123123 void print(raw_ostream *O) const { if (O) print(*O); }
124124 void dump() const;
125125 };
163163 const GlobalValue *getGV() const;
164164 const BlockAddress *getBlockAddress() const;
165165
166 virtual int getExistingMachineCPValue(MachineConstantPool *CP,
167 unsigned Alignment);
168
169 /// hasSameValue - Return true if this ARM constpool value can share the same
170 /// constantpool entry as another ARM constpool value.
171 virtual bool hasSameValue(ARMConstantPoolValue *ACPV);
172
173 virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
174
175 virtual void print(raw_ostream &O) const;
166 int getExistingMachineCPValue(MachineConstantPool *CP,
167 unsigned Alignment) override;
168
169 /// hasSameValue - Return true if this ARM constpool value can share the same
170 /// constantpool entry as another ARM constpool value.
171 bool hasSameValue(ARMConstantPoolValue *ACPV) override;
172
173 void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
174
175 void print(raw_ostream &O) const override;
176176 static bool classof(const ARMConstantPoolValue *APV) {
177177 return APV->isGlobalValue() || APV->isBlockAddress() || APV->isLSDA();
178178 }
197197
198198 const char *getSymbol() const { return S.c_str(); }
199199
200 virtual int getExistingMachineCPValue(MachineConstantPool *CP,
201 unsigned Alignment);
202
203 virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
204
205 /// hasSameValue - Return true if this ARM constpool value can share the same
206 /// constantpool entry as another ARM constpool value.
207 virtual bool hasSameValue(ARMConstantPoolValue *ACPV);
208
209 virtual void print(raw_ostream &O) const;
200 int getExistingMachineCPValue(MachineConstantPool *CP,
201 unsigned Alignment) override;
202
203 void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
204
205 /// hasSameValue - Return true if this ARM constpool value can share the same
206 /// constantpool entry as another ARM constpool value.
207 bool hasSameValue(ARMConstantPoolValue *ACPV) override;
208
209 void print(raw_ostream &O) const override;
210210
211211 static bool classof(const ARMConstantPoolValue *ACPV) {
212212 return ACPV->isExtSymbol();
233233
234234 const MachineBasicBlock *getMBB() const { return MBB; }
235235
236 virtual int getExistingMachineCPValue(MachineConstantPool *CP,
237 unsigned Alignment);
238
239 virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
240
241 /// hasSameValue - Return true if this ARM constpool value can share the same
242 /// constantpool entry as another ARM constpool value.
243 virtual bool hasSameValue(ARMConstantPoolValue *ACPV);
244
245 virtual void print(raw_ostream &O) const;
236 int getExistingMachineCPValue(MachineConstantPool *CP,
237 unsigned Alignment) override;
238
239 void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
240
241 /// hasSameValue - Return true if this ARM constpool value can share the same
242 /// constantpool entry as another ARM constpool value.
243 bool hasSameValue(ARMConstantPoolValue *ACPV) override;
244
245 void print(raw_ostream &O) const override;
246246
247247 static bool classof(const ARMConstantPoolValue *ACPV) {
248248 return ACPV->isMachineBasicBlock();
4545 const ARMSubtarget *STI;
4646 ARMFunctionInfo *AFI;
4747
48 virtual bool runOnMachineFunction(MachineFunction &Fn);
49
50 virtual const char *getPassName() const {
48 bool runOnMachineFunction(MachineFunction &Fn) override;
49
50 const char *getPassName() const override {
5151 return "ARM pseudo instruction expansion pass";
5252 }
5353
143143
144144 // Backend specific FastISel code.
145145 private:
146 virtual bool TargetSelectInstruction(const Instruction *I);
147 virtual unsigned TargetMaterializeConstant(const Constant *C);
148 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
149 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
150 const LoadInst *LI);
151 virtual bool FastLowerArguments();
146 bool TargetSelectInstruction(const Instruction *I) override;
147 unsigned TargetMaterializeConstant(const Constant *C) override;
148 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
149 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
150 const LoadInst *LI) override;
151 bool FastLowerArguments() override;
152152 private:
153153 #include "ARMGenFastISel.inc"
154154
3232
3333 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
3434 /// the function.
35 void emitPrologue(MachineFunction &MF) const;
36 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
35 void emitPrologue(MachineFunction &MF) const override;
36 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
3737
3838 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
3939 MachineBasicBlock::iterator MI,
4040 const std::vector &CSI,
41 const TargetRegisterInfo *TRI) const;
41 const TargetRegisterInfo *TRI) const override;
4242
4343 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MI,
45 const std::vector &CSI,
46 const TargetRegisterInfo *TRI) const;
44 MachineBasicBlock::iterator MI,
45 const std::vector &CSI,
46 const TargetRegisterInfo *TRI) const override;
4747
48 bool hasFP(const MachineFunction &MF) const;
49 bool hasReservedCallFrame(const MachineFunction &MF) const;
50 bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
48 bool hasFP(const MachineFunction &MF) const override;
49 bool hasReservedCallFrame(const MachineFunction &MF) const override;
50 bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
5151 int getFrameIndexReference(const MachineFunction &MF, int FI,
52 unsigned &FrameReg) const;
53 int ResolveFrameIndexReference(const MachineFunction &MF,
54 int FI,
52 unsigned &FrameReg) const override;
53 int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
5554 unsigned &FrameReg, int SPAdj) const;
56 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
55 int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
5756
5857 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
59 RegScavenger *RS) const;
58 RegScavenger *RS) const override;
6059
6160 private:
6261 void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
7069 bool(*Func)(unsigned, bool),
7170 unsigned NumAlignedDPRCS2Regs) const;
7271
73 virtual void eliminateCallFramePseudoInstr(
74 MachineFunction &MF,
75 MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator MI) const;
72 void
73 eliminateCallFramePseudoInstr(MachineFunction &MF,
74 MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator MI) const override;
7776 };
7877
7978 } // End llvm namespace
3636 : ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"),
3737 LastMI(0) {}
3838
39 virtual HazardType getHazardType(SUnit *SU, int Stalls);
40 virtual void Reset();
41 virtual void EmitInstruction(SUnit *SU);
42 virtual void AdvanceCycle();
43 virtual void RecedeCycle();
39 HazardType getHazardType(SUnit *SU, int Stalls) override;
40 void Reset() override;
41 void EmitInstruction(SUnit *SU) override;
42 void AdvanceCycle() override;
43 void RecedeCycle() override;
4444 };
4545
4646 } // end namespace llvm
7272 Subtarget(&TM.getSubtarget()) {
7373 }
7474
75 virtual const char *getPassName() const {
75 const char *getPassName() const override {
7676 return "ARM Instruction Selection";
7777 }
7878
79 virtual void PreprocessISelDAG();
79 void PreprocessISelDAG() override;
8080
8181 /// getI32Imm - Return a target constant of type i32 with the specified
8282 /// value.
8484 return CurDAG->getTargetConstant(Imm, MVT::i32);
8585 }
8686
87 SDNode *Select(SDNode *N);
87 SDNode *Select(SDNode *N) override;
8888
8989
9090 bool hasNoVMLxHazardUse(SDNode *N) const;
256256
257257 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
258258 /// inline asm expressions.
259 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
260 char ConstraintCode,
261 std::vector &OutOps);
259 bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
260 std::vector &OutOps) override;
262261
263262 // Form pairs of consecutive R, S, D, or Q registers.
264263 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
233233 public:
234234 explicit ARMTargetLowering(TargetMachine &TM);
235235
236 virtual unsigned getJumpTableEncoding() const;
237
238 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
236 unsigned getJumpTableEncoding() const override;
237
238 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
239239
240240 /// ReplaceNodeResults - Replace the results of node with an illegal result
241241 /// type with new values built out of custom code.
242242 ///
243 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results,
244 SelectionDAG &DAG) const;
245
246 virtual const char *getTargetNodeName(unsigned Opcode) const;
247
248 virtual bool isSelectSupported(SelectSupportKind Kind) const {
243 void ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results,
244 SelectionDAG &DAG) const override;
245
246 const char *getTargetNodeName(unsigned Opcode) const override;
247
248 bool isSelectSupported(SelectSupportKind Kind) const override {
249249 // ARM does not support scalar condition selects on vectors.
250250 return (Kind != ScalarCondVectorVal);
251251 }
252252
253253 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
254 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
255
256 virtual MachineBasicBlock *
254 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
255
256 MachineBasicBlock *
257257 EmitInstrWithCustomInserter(MachineInstr *MI,
258 MachineBasicBlock *MBB) const;
259
260 virtual void
261 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
258 MachineBasicBlock *MBB) const override;
259
260 void AdjustInstrPostInstrSelection(MachineInstr *MI,
261 SDNode *Node) const override;
262262
263263 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
264 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
265
266 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
264 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
265
266 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
267267
268268 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
269269 /// unaligned memory accesses of the specified type. Returns whether it
270270 /// is "fast" by reference in the second argument.
271 virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
272 bool *Fast) const;
273
274 virtual EVT getOptimalMemOpType(uint64_t Size,
275 unsigned DstAlign, unsigned SrcAlign,
276 bool IsMemset, bool ZeroMemset,
277 bool MemcpyStrSrc,
278 MachineFunction &MF) const;
271 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
272 bool *Fast) const override;
273
274 EVT getOptimalMemOpType(uint64_t Size,
275 unsigned DstAlign, unsigned SrcAlign,
276 bool IsMemset, bool ZeroMemset,
277 bool MemcpyStrSrc,
278 MachineFunction &MF) const override;
279279
280280 using TargetLowering::isZExtFree;
281 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
282
283 virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
281 bool isZExtFree(SDValue Val, EVT VT2) const override;
282
283 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
284284
285285
286286 /// isLegalAddressingMode - Return true if the addressing mode represented
287287 /// by AM is legal for this target, for a load/store of the specified type.
288 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
288 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
289289 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
290290
291291 /// isLegalICmpImmediate - Return true if the specified immediate is legal
292292 /// icmp immediate, that is the target has icmp instructions which can
293293 /// compare a register against the immediate without having to materialize
294294 /// the immediate into a register.
295 virtual bool isLegalICmpImmediate(int64_t Imm) const;
295 bool isLegalICmpImmediate(int64_t Imm) const override;
296296
297297 /// isLegalAddImmediate - Return true if the specified immediate is legal
298298 /// add immediate, that is the target has add instructions which can
299299 /// add a register and the immediate without having to materialize
300300 /// the immediate into a register.
301 virtual bool isLegalAddImmediate(int64_t Imm) const;
301 bool isLegalAddImmediate(int64_t Imm) const override;
302302
303303 /// getPreIndexedAddressParts - returns true by value, base pointer and
304304 /// offset pointer and addressing mode by reference if the node's address
305305 /// can be legally represented as pre-indexed load / store address.
306 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
307 SDValue &Offset,
308 ISD::MemIndexedMode &AM,
309 SelectionDAG &DAG) const;
306 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
307 ISD::MemIndexedMode &AM,
308 SelectionDAG &DAG) const override;
310309
311310 /// getPostIndexedAddressParts - returns true by value, base pointer and
312311 /// offset pointer and addressing mode by reference if this node can be
313312 /// combined with a load / store to form a post-indexed load / store.
314 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
315 SDValue &Base, SDValue &Offset,
316 ISD::MemIndexedMode &AM,
317 SelectionDAG &DAG) const;
318
319 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
320 APInt &KnownZero,
321 APInt &KnownOne,
322 const SelectionDAG &DAG,
323 unsigned Depth) const;
324
325
326 virtual bool ExpandInlineAsm(CallInst *CI) const;
327
328 ConstraintType getConstraintType(const std::string &Constraint) const;
313 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
314 SDValue &Offset, ISD::MemIndexedMode &AM,
315 SelectionDAG &DAG) const override;
316
317 void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero,
318 APInt &KnownOne,
319 const SelectionDAG &DAG,
320 unsigned Depth) const override;
321
322
323 bool ExpandInlineAsm(CallInst *CI) const override;
324
325 ConstraintType
326 getConstraintType(const std::string &Constraint) const override;
329327
330328 /// Examine constraint string and operand type and determine a weight value.
331329 /// The operand object must already have been set up with the operand type.
332330 ConstraintWeight getSingleConstraintMatchWeight(
333 AsmOperandInfo &info, const char *constraint) const;
331 AsmOperandInfo &info, const char *constraint) const override;
334332
335333 std::pair
336334 getRegForInlineAsmConstraint(const std::string &Constraint,
337 MVT VT) const;
335 MVT VT) const override;
338336
339337 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
340338 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
341339 /// true it means one of the asm constraint of the inline asm instruction
342340 /// being processed is 'm'.
343 virtual void LowerAsmOperandForConstraint(SDValue Op,
344 std::string &Constraint,
345 std::vector &Ops,
346 SelectionDAG &DAG) const;
341 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
342 std::vector &Ops,
343 SelectionDAG &DAG) const override;
347344
348345 const ARMSubtarget* getSubtarget() const {
349346 return Subtarget;
351348
352349 /// getRegClassFor - Return the register class that should be used for the
353350 /// specified value type.
354 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
351 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
355352
356353 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
357354 /// be used for loads / stores from the global.
358 virtual unsigned getMaximalGlobalOffset() const;
355 unsigned getMaximalGlobalOffset() const override;
359356
360357 /// Returns true if a cast between SrcAS and DestAS is a noop.
361 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
358 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
362359 // Addrspacecasts are always noops.
363360 return true;
364361 }
365362
366363 /// createFastISel - This method returns a target specific FastISel object,
367364 /// or null if the target does not support "fast" ISel.
368 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
369 const TargetLibraryInfo *libInfo) const;
370
371 Sched::Preference getSchedulingPreference(SDNode *N) const;
372
373 bool isShuffleMaskLegal(const SmallVectorImpl &M, EVT VT) const;
374 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
365 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
366 const TargetLibraryInfo *libInfo) const override;
367
368 Sched::Preference getSchedulingPreference(SDNode *N) const override;
369
370 bool
371 isShuffleMaskLegal(const SmallVectorImpl &M, EVT VT) const override;
372 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
375373
376374 /// isFPImmLegal - Returns true if the target can instruction select the
377375 /// specified FP immediate natively. If false, the legalizer will
378376 /// materialize the FP immediate as a load from a constant pool.
379 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
380
381 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
382 const CallInst &I,
383 unsigned Intrinsic) const;
377 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
378
379 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
380 const CallInst &I,
381 unsigned Intrinsic) const override;
384382
385383 /// \brief Returns true if it is beneficial to convert a load of a constant
386384 /// to just the constant itself.
387 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
388 Type *Ty) const;
385 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
386 Type *Ty) const override;
389387
390388 protected:
391389 std::pair
392 findRepresentativeClass(MVT VT) const;
390 findRepresentativeClass(MVT VT) const override;
393391
394392 private:
395393 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
466464 /// lower a pair of fmul and fadd to the latter so it's not clear that there
467465 /// would be a gain or that the gain would be worthwhile enough to risk
468466 /// correctness bugs.
469 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const { return false; }
467 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
470468
471469 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
472470
477475 SmallVectorImpl &InVals,
478476 bool isThisReturn, SDValue ThisVal) const;
479477
480 virtual SDValue
478 SDValue
481479 LowerFormalArguments(SDValue Chain,
482480 CallingConv::ID CallConv, bool isVarArg,
483481 const SmallVectorImpl &Ins,
484482 SDLoc dl, SelectionDAG &DAG,
485 SmallVectorImpl &InVals) const;
483 SmallVectorImpl &InVals) const override;
486484
487485 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
488486 SDLoc dl, SDValue &Chain,
493491 unsigned ArgSize,
494492 bool ForceMutable,
495493 unsigned ByValStoreOffset,
496 unsigned TotalArgRegsSaveSize) const;
494 unsigned TotalArgRegsSaveSize) const;
497495
498496 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
499497 SDLoc dl, SDValue &Chain,
500498 unsigned ArgOffset,
501 unsigned TotalArgRegsSaveSize,
499 unsigned TotalArgRegsSaveSize,
502500 bool ForceMutable = false) const;
503501
504502 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
507505 unsigned &ArgRegsSize,
508506 unsigned &ArgRegsSaveSize) const;
509507
510 virtual SDValue
508 SDValue
511509 LowerCall(TargetLowering::CallLoweringInfo &CLI,
512 SmallVectorImpl &InVals) const;
510 SmallVectorImpl &InVals) const override;
513511
514512 /// HandleByVal - Target-specific cleanup for ByVal support.
515 virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
513 void HandleByVal(CCState *, unsigned &, unsigned) const override;
516514
517515 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
518516 /// for tail call optimization. Targets which want to do tail call
527525 const SmallVectorImpl &Ins,
528526 SelectionDAG& DAG) const;
529527
530 virtual bool CanLowerReturn(CallingConv::ID CallConv,
531 MachineFunction &MF, bool isVarArg,
532 const SmallVectorImpl &Outs,
533 LLVMContext &Context) const;
534
535 virtual SDValue
528 bool CanLowerReturn(CallingConv::ID CallConv,
529 MachineFunction &MF, bool isVarArg,
530 const SmallVectorImpl &Outs,
531 LLVMContext &Context) const override;
532
533 SDValue
536534 LowerReturn(SDValue Chain,
537535 CallingConv::ID CallConv, bool isVarArg,
538536 const SmallVectorImpl &Outs,
539537 const SmallVectorImpl &OutVals,
540 SDLoc dl, SelectionDAG &DAG) const;
541
542 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
543
544 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
538 SDLoc dl, SelectionDAG &DAG) const override;
539
540 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
541
542 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
545543
546544 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
547545 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
9696 static char ID;
9797 ARMCGBR() : MachineFunctionPass(ID) {}
9898
99 virtual bool runOnMachineFunction(MachineFunction &MF) {
99 bool runOnMachineFunction(MachineFunction &MF) override {
100100 ARMFunctionInfo *AFI = MF.getInfo();
101101 if (AFI->getGlobalBaseReg() == 0)
102102 return false;
145145 return true;
146146 }
147147
148 virtual const char *getPassName() const {
148 const char *getPassName() const override {
149149 return "ARM PIC Global Base Reg Initialization";
150150 }
151151
152 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
152 void getAnalysisUsage(AnalysisUsage &AU) const override {
153153 AU.setPreservesCFG();
154154 MachineFunctionPass::getAnalysisUsage(AU);
155155 }
2727 explicit ARMInstrInfo(const ARMSubtarget &STI);
2828
2929 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
30 void getNoopForMachoTarget(MCInst &NopInst) const;
30 void getNoopForMachoTarget(MCInst &NopInst) const override;
3131
3232 // Return the non-pre/post incrementing version of 'Opc'. Return 0
3333 // if there is not such an opcode.
34 unsigned getUnindexedOpcode(unsigned Opc) const;
34 unsigned getUnindexedOpcode(unsigned Opc) const override;
3535
3636 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
3737 /// such, whenever a client has an instance of instruction info, it should
3838 /// always be able to get register info as well (through this method).
3939 ///
40 const ARMRegisterInfo &getRegisterInfo() const { return RI; }
40 const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
4141 };
4242
4343 }
5252 /// overwriting OLD with a branch to NEW. This is used for self-modifying
5353 /// code.
5454 ///
55 virtual void replaceMachineCodeForFunction(void *Old, void *New);
55 void replaceMachineCodeForFunction(void *Old, void *New) override;
5656
5757 /// emitGlobalValueIndirectSym - Use the specified JITCodeEmitter object
5858 /// to emit an indirect symbol which contains the address of the specified
5959 /// ptr.
60 virtual void *emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,
61 JITCodeEmitter &JCE);
60 void *emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,
61 JITCodeEmitter &JCE) override;
6262
6363 // getStubLayout - Returns the size and alignment of the largest call stub
6464 // on ARM.
65 virtual StubLayout getStubLayout();
65 StubLayout getStubLayout() override;
6666
6767 /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
6868 /// small native function that simply calls the function at the specified
6969 /// address.
70 virtual void *emitFunctionStub(const Function* F, void *Fn,
71 JITCodeEmitter &JCE);
70 void *emitFunctionStub(const Function* F, void *Fn,
71 JITCodeEmitter &JCE) override;
7272
7373 /// getLazyResolverFunction - Expose the lazy resolver to the JIT.
74 virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
74 LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
7575
7676 /// relocate - Before the JIT can run a block of code that has been emitted,
7777 /// it must rewrite the code to contain the actual addresses of any
7878 /// referenced global symbols.
79 virtual void relocate(void *Function, MachineRelocation *MR,
80 unsigned NumRelocs, unsigned char* GOTBase);
79 void relocate(void *Function, MachineRelocation *MR,
80 unsigned NumRelocs, unsigned char* GOTBase) override;
8181
8282 /// hasCustomConstantPool - Allows a target to specify that constant
8383 /// pool address resolution is handled by the target.
84 virtual bool hasCustomConstantPool() const { return true; }
84 bool hasCustomConstantPool() const override { return true; }
8585
8686 /// hasCustomJumpTables - Allows a target to specify that jumptables
8787 /// are emitted by the target.
88 virtual bool hasCustomJumpTables() const { return true; }
88 bool hasCustomJumpTables() const override { return true; }
8989
9090 /// allocateSeparateGVMemory - If true, globals should be placed in
9191 /// separately allocated heap memory rather than in the same
9292 /// code memory allocated by JITCodeEmitter.
93 virtual bool allocateSeparateGVMemory() const {
93 bool allocateSeparateGVMemory() const override {
9494 #ifdef __APPLE__
9595 return true;
9696 #else
6868 RegScavenger *RS;
6969 bool isThumb2;
7070
71 virtual bool runOnMachineFunction(MachineFunction &Fn);
72
73 virtual const char *getPassName() const {
71 bool runOnMachineFunction(MachineFunction &Fn) override;
72
73 const char *getPassName() const override {
7474 return "ARM load / store optimization pass";
7575 }
7676
15491549 MachineRegisterInfo *MRI;
15501550 MachineFunction *MF;
15511551
1552 virtual bool runOnMachineFunction(MachineFunction &Fn);
1553
1554 virtual const char *getPassName() const {
1552 bool runOnMachineFunction(MachineFunction &Fn) override;
1553
1554 const char *getPassName() const override {
15551555 return "ARM pre- register allocation load / store optimization pass";
15561556 }
15571557
4343 explicit ARMSelectionDAGInfo(const TargetMachine &TM);
4444 ~ARMSelectionDAGInfo();
4545
46 virtual
4746 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
4847 SDValue Chain,
4948 SDValue Dst, SDValue Src,
5049 SDValue Size, unsigned Align,
5150 bool isVolatile, bool AlwaysInline,
5251 MachinePointerInfo DstPtrInfo,
53 MachinePointerInfo SrcPtrInfo) const;
52 MachinePointerInfo SrcPtrInfo) const override;
5453
5554 // Adjust parameters for memset, see RTABI section 4.3.4
56 virtual
5755 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
5856 SDValue Chain,
5957 SDValue Op1, SDValue Op2,
6058 SDValue Op3, unsigned Align,
6159 bool isVolatile,
62 MachinePointerInfo DstPtrInfo) const;
60 MachinePointerInfo DstPtrInfo) const override;
6361 };
6462
6563 }
239239 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
240240
241241 /// \brief Reset the features for the ARM target.
242 virtual void resetSubtargetFeatures(const MachineFunction *MF);
242 void resetSubtargetFeatures(const MachineFunction *MF) override;
243243 private:
244244 void initializeEnvironment();
245245 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
383383 /// enablePostRAScheduler - True at 'More' optimization.
384384 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
385385 TargetSubtargetInfo::AntiDepBreakMode& Mode,
386 RegClassVector& CriticalPathRCs) const;
386 RegClassVector& CriticalPathRCs) const override;
387387
388388 /// getInstrItins - Return the instruction itineraies based on subtarget
389389 /// selection.
165165 return *getARMTargetMachine().getSubtargetImpl();
166166 }
167167
168 virtual bool addPreISel();
169 virtual bool addInstSelector();
170 virtual bool addPreRegAlloc();
171 virtual bool addPreSched2();
172 virtual bool addPreEmitPass();
168 bool addPreISel() override;
169 bool addInstSelector() override;
170 bool addPreRegAlloc() override;
171 bool addPreSched2() override;
172 bool addPreEmitPass() override;
173173 };
174174 } // namespace
175175
4343 Reloc::Model RM, CodeModel::Model CM,
4444 CodeGenOpt::Level OL);
4545
46 virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
47 virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
48 virtual const ARMTargetLowering *getTargetLowering() const {
46 ARMJITInfo *getJITInfo() override { return &JITInfo; }
47 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
48 const ARMTargetLowering *getTargetLowering() const override {
4949 // Implemented by derived classes
5050 llvm_unreachable("getTargetLowering not implemented");
5151 }
52 virtual const InstrItineraryData *getInstrItineraryData() const {
52 const InstrItineraryData *getInstrItineraryData() const override {
5353 return &InstrItins;
5454 }
5555
5656 /// \brief Register ARM analysis passes with a pass manager.
57 virtual void addAnalysisPasses(PassManagerBase &PM);
57 void addAnalysisPasses(PassManagerBase &PM) override;
5858
5959 // Pass Pipeline Configuration
60 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
60 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
6161
62 virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
62 bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
6363 };
6464
6565 /// ARMTargetMachine - ARM target machine.
7878 Reloc::Model RM, CodeModel::Model CM,
7979 CodeGenOpt::Level OL);
8080
81 virtual const ARMRegisterInfo *getRegisterInfo() const {
81 const ARMRegisterInfo *getRegisterInfo() const override {
8282 return &InstrInfo.getRegisterInfo();
8383 }
8484
85 virtual const ARMTargetLowering *getTargetLowering() const {
85 const ARMTargetLowering *getTargetLowering() const override {
8686 return &TLInfo;
8787 }
8888
89 virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
89 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
9090 return &TSInfo;
9191 }
92 virtual const ARMFrameLowering *getFrameLowering() const {
92 const ARMFrameLowering *getFrameLowering() const override {
9393 return &FrameLowering;
9494 }
95 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
96 virtual const DataLayout *getDataLayout() const { return &DL; }
95 const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
96 const DataLayout *getDataLayout() const override { return &DL; }
9797 };
9898
9999 /// ThumbTargetMachine - Thumb target machine.
117117 CodeGenOpt::Level OL);
118118
119119 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
120 virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
120 const ARMBaseRegisterInfo *getRegisterInfo() const override {
121121 return &InstrInfo->getRegisterInfo();
122122 }
123123
124 virtual const ARMTargetLowering *getTargetLowering() const {
124 const ARMTargetLowering *getTargetLowering() const override {
125125 return &TLInfo;
126126 }
127127
128 virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
128 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
129129 return &TSInfo;
130130 }
131131
132132 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
133 virtual const ARMBaseInstrInfo *getInstrInfo() const {
133 const ARMBaseInstrInfo *getInstrInfo() const override {
134134 return InstrInfo.get();
135135 }
136136 /// returns either Thumb1FrameLowering or ARMFrameLowering
137 virtual const ARMFrameLowering *getFrameLowering() const {
137 const ARMFrameLowering *getFrameLowering() const override {
138138 return FrameLowering.get();
139139 }
140 virtual const DataLayout *getDataLayout() const { return &DL; }
140 const DataLayout *getDataLayout() const override { return &DL; }
141141 };
142142
143143 } // end namespace llvm
5151 initializeARMTTIPass(*PassRegistry::getPassRegistry());
5252 }
5353
54 virtual void initializePass() override {
54 void initializePass() override {
5555 pushTTIStack(this);
5656 }
5757
5959 popTTIStack();
6060 }
6161
62 virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
62 void getAnalysisUsage(AnalysisUsage &AU) const override {
6363 TargetTransformInfo::getAnalysisUsage(AU);
6464 }
6565
6767 static char ID;
6868
6969 /// Provide necessary pointer adjustments for the two base classes.
70 virtual void *getAdjustedAnalysisPointer(const void *ID) override {
70 void *getAdjustedAnalysisPointer(const void *ID) override {
7171 if (ID == &TargetTransformInfo::ID)
7272 return (TargetTransformInfo*)this;
7373 return this;
7676 /// \name Scalar TTI Implementations
7777 /// @{
7878 using TargetTransformInfo::getIntImmCost;
79 virtual unsigned
80 getIntImmCost(const APInt &Imm, Type *Ty) const override;
79 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
8180
8281 /// @}
8382
8584 /// \name Vector TTI Implementations
8685 /// @{
8786
88 unsigned getNumberOfRegisters(bool Vector) const {
87 unsigned getNumberOfRegisters(bool Vector) const override {
8988 if (Vector) {
9089 if (ST->hasNEON())
9190 return 16;
9796 return 13;
9897 }
9998
100 unsigned getRegisterBitWidth(bool Vector) const {
99 unsigned getRegisterBitWidth(bool Vector) const override {
101100 if (Vector) {
102101 if (ST->hasNEON())
103102 return 128;
107106 return 32;
108107 }
109108
110 unsigned getMaximumUnrollFactor() const {
109 unsigned getMaximumUnrollFactor() const override {
111110 // These are out of order CPUs:
112111 if (ST->isCortexA15() || ST->isSwift())
113112 return 2;
115114 }
116115
117116 unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
118 int Index, Type *SubTp) const;
117 int Index, Type *SubTp) const override;
119118
120119 unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
121 Type *Src) const;
122
123 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) const;
124
125 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const;
126
127 unsigned getAddressComputationCost(Type *Val, bool IsComplex) const;
128
129 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
130 OperandValueKind Op1Info = OK_AnyValue,
131 OperandValueKind Op2Info = OK_AnyValue) const;
120 Type *Src) const override;
121
122 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
123 Type *CondTy) const override;
124
125 unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
126 unsigned Index) const override;
127
128 unsigned getAddressComputationCost(Type *Val,
129 bool IsComplex) const override;
130
131 unsigned
132 getArithmeticInstrCost(unsigned Opcode, Type *Ty,
133 OperandValueKind Op1Info = OK_AnyValue,
134 OperandValueKind Op2Info = OK_AnyValue) const override;
132135
133136 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
134 unsigned AddressSpace) const;
137 unsigned AddressSpace) const override;
135138 /// @}
136139 };
137140
2525 ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
2626 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
2727
28 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
29 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
28 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
29 void printRegName(raw_ostream &OS, unsigned RegNo) const override;
3030
3131 // Autogenerated by tblgen.
3232 void printInstruction(const MCInst *MI, raw_ostream &O);
5555
5656 /// @}
5757
58 void PrintImpl(raw_ostream &OS) const;
58 void PrintImpl(raw_ostream &OS) const override;
5959 bool EvaluateAsRelocatableImpl(MCValue &Res,
60 const MCAsmLayout *Layout) const;
61 void AddValueSymbols(MCAssembler *) const;
62 const MCSection *FindAssociatedSection() const {
60 const MCAsmLayout *Layout) const override;
61 void AddValueSymbols(MCAssembler *) const override;
62 const MCSection *FindAssociatedSection() const override {
6363 return getSubExpr()->FindAssociatedSection();
6464 }
6565
6666 // There are no TLS ARMMCExprs at the moment.
67 void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {}
67 void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
6868
6969 static bool classof(const MCExpr *E) {
7070 return E->getKind() == MCExpr::Target;
3939 static char ID;
4040 MLxExpansion() : MachineFunctionPass(ID) {}
4141
42 virtual bool runOnMachineFunction(MachineFunction &Fn);
43
44 virtual const char *getPassName() const {
42 bool runOnMachineFunction(MachineFunction &Fn) override;
43
44 const char *getPassName() const override {
4545 return "ARM MLA / MLS expansion pass";
4646 }
4747
3131
3232 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
3333 /// the function.
34 void emitPrologue(MachineFunction &MF) const;
35 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
34 void emitPrologue(MachineFunction &MF) const override;
35 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
3636
3737 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
3838 MachineBasicBlock::iterator MI,
3939 const std::vector &CSI,
40 const TargetRegisterInfo *TRI) const;
40 const TargetRegisterInfo *TRI) const override;
4141 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MI,
43 const std::vector &CSI,
44 const TargetRegisterInfo *TRI) const;
42 MachineBasicBlock::iterator MI,
43 const std::vector &CSI,
44 const TargetRegisterInfo *TRI) const override;
4545
46 bool hasReservedCallFrame(const MachineFunction &MF) const;
46 bool hasReservedCallFrame(const MachineFunction &MF) const override;
4747
48 void eliminateCallFramePseudoInstr(MachineFunction &MF,
49 MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MI) const;
48 void
49 eliminateCallFramePseudoInstr(MachineFunction &MF,
50 MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MI) const override;
5152 };
5253
5354 } // End llvm namespace
2626 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
2727
2828 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
29 void getNoopForMachoTarget(MCInst &NopInst) const;
29 void getNoopForMachoTarget(MCInst &NopInst) const override;
3030
3131 // Return the non-pre/post incrementing version of 'Opc'. Return 0
3232 // if there is not such an opcode.
33 unsigned getUnindexedOpcode(unsigned Opc) const;
33 unsigned getUnindexedOpcode(unsigned Opc) const override;
3434
3535 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
3636 /// such, whenever a client has an instance of instruction info, it should
3737 /// always be able to get register info as well (through this method).
3838 ///
39 const Thumb1RegisterInfo &getRegisterInfo() const { return RI; }
39 const Thumb1RegisterInfo &getRegisterInfo() const override { return RI; }
4040
4141 void copyPhysReg(MachineBasicBlock &MBB,
4242 MachineBasicBlock::iterator I, DebugLoc DL,
4343 unsigned DestReg, unsigned SrcReg,
44 bool KillSrc) const;
44 bool KillSrc) const override;
4545 void storeRegToStackSlot(MachineBasicBlock &MBB,
4646 MachineBasicBlock::iterator MBBI,
4747 unsigned SrcReg, bool isKill, int FrameIndex,
4848 const TargetRegisterClass *RC,
49 const TargetRegisterInfo *TRI) const;
49 const TargetRegisterInfo *TRI) const override;
5050
5151 void loadRegFromStackSlot(MachineBasicBlock &MBB,
5252 MachineBasicBlock::iterator MBBI,
5353 unsigned DestReg, int FrameIndex,
5454 const TargetRegisterClass *RC,
55 const TargetRegisterInfo *TRI) const;
55 const TargetRegisterInfo *TRI) const override;
5656
5757 };
5858 }
2626 public:
2727 Thumb1RegisterInfo(const ARMSubtarget &STI);
2828
29 const TargetRegisterClass*
30 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
29 const TargetRegisterClass *
30 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
3131
32 const TargetRegisterClass*
33 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
32 const TargetRegisterClass *
33 getPointerRegClass(const MachineFunction &MF,
34 unsigned Kind = 0) const override;
3435
3536 /// emitLoadConstPool - Emits a load from constpool to materialize the
3637 /// specified immediate.
37 void emitLoadConstPool(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator &MBBI,
39 DebugLoc dl,
40 unsigned DestReg, unsigned SubIdx, int Val,
41 ARMCC::CondCodes Pred = ARMCC::AL,
42 unsigned PredReg = 0,
43 unsigned MIFlags = MachineInstr::NoFlags) const;
38 void
39 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
40 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
41 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
42 unsigned MIFlags = MachineInstr::NoFlags) const override;
4443
4544 // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be
4645 // however much remains to be handled. Return 'true' if no further
4948 unsigned FrameReg, int &Offset,
5049 const ARMBaseInstrInfo &TII) const;
5150 void resolveFrameIndex(MachineBasicBlock::iterator I,
52 unsigned BaseReg, int64_t Offset) const;
51 unsigned BaseReg, int64_t Offset) const override;
5352 bool saveScavengerRegister(MachineBasicBlock &MBB,
5453 MachineBasicBlock::iterator I,
5554 MachineBasicBlock::iterator &UseMI,
5655 const TargetRegisterClass *RC,
57 unsigned Reg) const;
56 unsigned Reg) const override;
5857 void eliminateFrameIndex(MachineBasicBlock::iterator II,
5958 int SPAdj, unsigned FIOperandNum,
60 RegScavenger *RS = NULL) const;
59 RegScavenger *RS = NULL) const override;
6160 };
6261 }
6362
3232 const TargetRegisterInfo *TRI;
3333 ARMFunctionInfo *AFI;
3434
35 virtual bool runOnMachineFunction(MachineFunction &Fn);
36
37 virtual const char *getPassName() const {
35 bool runOnMachineFunction(MachineFunction &Fn) override;
36
37 const char *getPassName() const override {
3838 return "Thumb IT blocks insertion pass";
3939 }
4040
2727 explicit Thumb2InstrInfo(const ARMSubtarget &STI);
2828
2929 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
30 void getNoopForMachoTarget(MCInst &NopInst) const;
30 void getNoopForMachoTarget(MCInst &NopInst) const override;
3131
3232 // Return the non-pre/post incrementing version of 'Opc'. Return 0
3333 // if there is not such an opcode.
34 unsigned getUnindexedOpcode(unsigned Opc) const;
34 unsigned getUnindexedOpcode(unsigned Opc) const override;
3535
3636 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
37 MachineBasicBlock *NewDest) const;
37 MachineBasicBlock *NewDest) const override;
3838
3939 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MBBI) const;
40 MachineBasicBlock::iterator MBBI) const override;
4141
4242 void copyPhysReg(MachineBasicBlock &MBB,
4343 MachineBasicBlock::iterator I, DebugLoc DL,
4444 unsigned DestReg, unsigned SrcReg,
45 bool KillSrc) const;
45 bool KillSrc) const override;
4646
4747 void storeRegToStackSlot(MachineBasicBlock &MBB,
4848 MachineBasicBlock::iterator MBBI,
4949 unsigned SrcReg, bool isKill, int FrameIndex,
5050 const TargetRegisterClass *RC,
51 const TargetRegisterInfo *TRI) const;
51 const TargetRegisterInfo *TRI) const override;
5252
5353 void loadRegFromStackSlot(MachineBasicBlock &MBB,
5454 MachineBasicBlock::iterator MBBI,
5555 unsigned DestReg, int FrameIndex,
5656 const TargetRegisterClass *RC,
57 const TargetRegisterInfo *TRI) const;
57 const TargetRegisterInfo *TRI) const override;
5858
5959 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
6060 /// such, whenever a client has an instance of instruction info, it should
6161 /// always be able to get register info as well (through this method).
6262 ///
63 const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
63 const Thumb2RegisterInfo &getRegisterInfo() const override { return RI; }
6464 };
6565
6666 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
2828
2929 /// emitLoadConstPool - Emits a load from constpool to materialize the
3030 /// specified immediate.
31 void emitLoadConstPool(MachineBasicBlock &MBB,
32 MachineBasicBlock::iterator &MBBI,
33 DebugLoc dl,
34 unsigned DestReg, unsigned SubIdx, int Val,
35 ARMCC::CondCodes Pred = ARMCC::AL,
36 unsigned PredReg = 0,
37 unsigned MIFlags = MachineInstr::NoFlags) const;
31 void
32 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
33 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
34 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
35 unsigned MIFlags = MachineInstr::NoFlags) const override;
3836 };
3937 }
4038
136136 const Thumb2InstrInfo *TII;
137137 const ARMSubtarget *STI;
138138
139 virtual bool runOnMachineFunction(MachineFunction &MF);
140
141 virtual const char *getPassName() const {
139 bool runOnMachineFunction(MachineFunction &MF) override;
140
141 const char *getPassName() const override {
142142 return "Thumb2 instruction size reduction pass";
143143 }
144144