llvm.org GIT mirror llvm / d0e93f2
TableGen: use correct MIOperand when printing aliases Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208880 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 5 years ago
6 changed file(s) with 56 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
239239 printShiftedRegister(MI, 2, O);
240240 return;
241241 }
242 // SUBS WZR, Wn, #imm ==> CMP Wn, #imm
243 // SUBS XZR, Xn, #imm ==> CMP Xn, #imm
244 if ((Opcode == ARM64::SUBSWri && MI->getOperand(0).getReg() == ARM64::WZR) ||
245 (Opcode == ARM64::SUBSXri && MI->getOperand(0).getReg() == ARM64::XZR)) {
246 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
247 printAddSubImm(MI, 2, O);
248 return;
249 }
250242 // SUBS WZR, Wn, Wm{, lshift #imm} ==> CMP Wn, Wm{, lshift #imm}
251243 // SUBS XZR, Xn, Xm{, lshift #imm} ==> CMP Xn, Xm{, lshift #imm}
252244 if ((Opcode == ARM64::SUBSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
271263 return;
272264 }
273265
274 // ADDS WZR, Wn, #imm ==> CMN Wn, #imm
275 // ADDS XZR, Xn, #imm ==> CMN Xn, #imm
276 if ((Opcode == ARM64::ADDSWri && MI->getOperand(0).getReg() == ARM64::WZR) ||
277 (Opcode == ARM64::ADDSXri && MI->getOperand(0).getReg() == ARM64::XZR)) {
278 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
279 printAddSubImm(MI, 2, O);
280 return;
281 }
282266 // ADDS WZR, Wn, Wm{, lshift #imm} ==> CMN Wn, Wm{, lshift #imm}
283267 // ADDS XZR, Xn, Xm{, lshift #imm} ==> CMN Xn, Xm{, lshift #imm}
284268 if ((Opcode == ARM64::ADDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
26372637
26382638 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
26392639 // this is compatible with what GAS does.
2640 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2641 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2642 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2643 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2644 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2645 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2646 def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2647 def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2648
2649 def : InstAlias<"call *$dst", (CALL64m i16mem:$dst)>, Requires<[In64BitMode]>;
2650 def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst)>, Requires<[In64BitMode]>;
2651 def : InstAlias<"call *$dst", (CALL32m i16mem:$dst)>, Requires<[In32BitMode]>;
2652 def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst)>, Requires<[In32BitMode]>;
2653 def : InstAlias<"call *$dst", (CALL16m i16mem:$dst)>, Requires<[In16BitMode]>;
2654 def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst)>, Requires<[In16BitMode]>;
2640 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2641 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2642 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2643 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2644 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2645 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2646 def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2647 def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2648
2649 def : InstAlias<"call *$dst", (CALL64m i16mem:$dst), 0>, Requires<[In64BitMode]>;
2650 def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst), 0>, Requires<[In64BitMode]>;
2651 def : InstAlias<"call *$dst", (CALL32m i16mem:$dst), 0>, Requires<[In32BitMode]>;
2652 def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst), 0>, Requires<[In32BitMode]>;
2653 def : InstAlias<"call *$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2654 def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
26552655
26562656
26572657 // "imul , B" is an alias for "imul , B, B".
27252725 // 'sldt ' can be encoded with either sldtw or sldtq with the same
27262726 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
27272727 // errors, since its encoding is the most compact.
2728 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2728 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
27292729
27302730 // shld/shrd op,op -> shld op, op, CL
27312731 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
15601560
15611561 let Predicates = [UseAVX] in {
15621562 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1563 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1563 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
15641564 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1565 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1565 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
15661566
15671567 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
15681568 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
16261626 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
16271627
16281628 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1629 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1629 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
16301630 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1631 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1631 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
16321632
16331633 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
16341634 // and/or XMM operand(s).
826826 IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(),
827827 CGA->AsmString);
828828
829 unsigned NumMIOps = 0;
830 for (auto &Operand : CGA->ResultOperands)
831 NumMIOps += Operand.getMINumOperands();
832
829833 std::string Cond;
830 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo);
834 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps);
831835 IAP->addCond(Cond);
832836
833837 bool CantHandle = false;
834838
839 unsigned MIOpNum = 0;
835840 for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
836841 const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
837842
859864 if (Rec->isSubClassOf("RegisterOperand"))
860865 Rec = Rec->getValueAsDef("RegClass");
861866 if (Rec->isSubClassOf("RegisterClass")) {
862 Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()";
867 Cond = std::string("MI->getOperand(") + llvm::utostr(MIOpNum) +
868 ").isReg()";
863869 IAP->addCond(Cond);
864870
865871 if (!IAP->isOpMapped(ROName)) {
866 IAP->addOperand(ROName, i, PrintMethodIdx);
872 IAP->addOperand(ROName, MIOpNum, PrintMethodIdx);
867873 Record *R = CGA->ResultOperands[i].getRecord();
868874 if (R->isSubClassOf("RegisterOperand"))
869875 R = R->getValueAsDef("RegClass");
870876 Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
871 R->getName() + "RegClassID)"
872 ".contains(MI->getOperand(" + llvm::utostr(i) + ").getReg())";
877 R->getName() + "RegClassID)"
878 ".contains(MI->getOperand(" +
879 llvm::utostr(MIOpNum) + ").getReg())";
873880 IAP->addCond(Cond);
874881 } else {
875882 Cond = std::string("MI->getOperand(") +
876 llvm::utostr(i) + ").getReg() == MI->getOperand(" +
883 llvm::utostr(MIOpNum) + ").getReg() == MI->getOperand(" +
877884 llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()";
878885 IAP->addCond(Cond);
879886 }
880887 } else {
881888 // Assume all printable operands are desired for now. This can be
882889 // overridden in the InstAlias instantiation if necessary.
883 IAP->addOperand(ROName, i, PrintMethodIdx);
890 IAP->addOperand(ROName, MIOpNum, PrintMethodIdx);
884891 }
885892
886893 break;
887894 }
888895 case CodeGenInstAlias::ResultOperand::K_Imm: {
889 std::string Op = "MI->getOperand(" + llvm::utostr(i) + ")";
896 std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")";
890897
891898 // Just because the alias has an immediate result, doesn't mean the
892899 // MCInst will. An MCExpr could be present, for example.
906913 }
907914
908915 Cond = std::string("MI->getOperand(") +
909 llvm::utostr(i) + ").getReg() == " + Target.getName() +
916 llvm::utostr(MIOpNum) + ").getReg() == " + Target.getName() +
910917 "::" + CGA->ResultOperands[i].getRegister()->getName();
911918 IAP->addCond(Cond);
912919 break;
913920 }
914921
915922 if (!IAP) break;
923 MIOpNum += RO.getMINumOperands();
916924 }
917925
918926 if (CantHandle) continue;
533533 }
534534
535535 return false;
536 }
537
538 unsigned CodeGenInstAlias::ResultOperand::getMINumOperands() const {
539 if (!isRecord())
540 return 1;
541
542 Record *Rec = getRecord();
543 if (!Rec->isSubClassOf("Operand"))
544 return 1;
545
546 DagInit *MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
547 if (MIOpInfo->getNumArgs() == 0) {
548 // Unspecified, so it defaults to 1
549 return 1;
550 }
551
552 return MIOpInfo->getNumArgs();
536553 }
537554
538555 CodeGenInstAlias::CodeGenInstAlias(Record *R, unsigned Variant,
323323 Record *getRecord() const { assert(isRecord()); return R; }
324324 int64_t getImm() const { assert(isImm()); return Imm; }
325325 Record *getRegister() const { assert(isReg()); return R; }
326
327 unsigned getMINumOperands() const;
326328 };
327329
328330 /// ResultOperands - The decoded operands for the result instruction.