llvm.org GIT mirror llvm / d0c3817
Move hasFP() and few related hooks to TargetFrameInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 8 years ago
68 changed file(s) with 498 addition(s) and 467 deletion(s). Raw diff Collapse all Expand all
104104 virtual void emitPrologue(MachineFunction &MF) const = 0;
105105 virtual void emitEpilogue(MachineFunction &MF,
106106 MachineBasicBlock &MBB) const = 0;
107
108 /// hasFP - Return true if the specified function should have a dedicated
109 /// frame pointer register. For most targets this is true only if the function
110 /// has variable sized allocas or if frame pointer elimination is disabled.
111 virtual bool hasFP(const MachineFunction &MF) const = 0;
112
113 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
114 /// not required, we reserve argument space for call sites in the function
115 /// immediately on entry to the current function. This eliminates the need for
116 /// add/sub sp brackets around call sites. Returns true if the call frame is
117 /// included as part of the stack frame.
118 virtual bool hasReservedCallFrame(const MachineFunction &MF) const {
119 return !hasFP(MF);
120 }
121
122 /// canSimplifyCallFramePseudos - When possible, it's best to simplify the
123 /// call frame pseudo ops before doing frame index elimination. This is
124 /// possible only when frame index references between the pseudos won't
125 /// need adjusting for the call frame adjustments. Normally, that's true
126 /// if the function has a reserved call frame or a frame pointer. Some
127 /// targets (Thumb2, for example) may have more complicated criteria,
128 /// however, and can override this behavior.
129 virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const {
130 return hasReservedCallFrame(MF) || hasFP(MF);
131 }
132
107133 };
108134
109135 } // End llvm namespace
595595 return false;
596596 }
597597
598 /// hasFP - Return true if the specified function should have a dedicated
599 /// frame pointer register. For most targets this is true only if the function
600 /// has variable sized allocas or if frame pointer elimination is disabled.
601 virtual bool hasFP(const MachineFunction &MF) const = 0;
602
603 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
604 /// not required, we reserve argument space for call sites in the function
605 /// immediately on entry to the current function. This eliminates the need for
606 /// add/sub sp brackets around call sites. Returns true if the call frame is
607 /// included as part of the stack frame.
608 virtual bool hasReservedCallFrame(const MachineFunction &MF) const {
609 return !hasFP(MF);
610 }
611
612 /// canSimplifyCallFramePseudos - When possible, it's best to simplify the
613 /// call frame pseudo ops before doing frame index elimination. This is
614 /// possible only when frame index references between the pseudos won't
615 /// need adjusting for the call frame adjustments. Normally, that's true
616 /// if the function has a reserved call frame or a frame pointer. Some
617 /// targets (Thumb2, for example) may have more complicated criteria,
618 /// however, and can override this behavior.
619 virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const {
620 return hasReservedCallFrame(MF) || hasFP(MF);
621 }
622
623598 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
624599 /// the stack frame of the given function for the specified register. e.g. On
625600 /// x86, if the frame register is required, the first fixed stack object is
141141 /// pseudo instructions.
142142 void PEI::calculateCallsInformation(MachineFunction &Fn) {
143143 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
144 const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
144145 MachineFrameInfo *MFI = Fn.getFrameInfo();
145146
146147 unsigned MaxCallFrameSize = 0;
183184 // the target doesn't indicate otherwise, remove the call frame pseudos
184185 // here. The sub/add sp instruction pairs are still inserted, but we don't
185186 // need to track the SP adjustment for frame index elimination.
186 if (RegInfo->canSimplifyCallFramePseudos(Fn))
187 if (TFI->canSimplifyCallFramePseudos(Fn))
187188 RegInfo->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I);
188189 }
189190 }
552553 // Make sure the special register scavenging spill slot is closest to the
553554 // frame pointer if a frame pointer is required.
554555 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
555 if (RS && RegInfo->hasFP(Fn) && !RegInfo->needsStackRealignment(Fn)) {
556 if (RS && TFI.hasFP(Fn) && !RegInfo->needsStackRealignment(Fn)) {
556557 int SFI = RS->getScavengingFrameIndex();
557558 if (SFI >= 0)
558559 AdjustStackOffset(MFI, SFI, StackGrowsDown, Offset, MaxAlign);
634635
635636 // Make sure the special register scavenging spill slot is closest to the
636637 // stack pointer.
637 if (RS && (!RegInfo->hasFP(Fn) || RegInfo->needsStackRealignment(Fn))) {
638 if (RS && (!TFI.hasFP(Fn) || RegInfo->needsStackRealignment(Fn))) {
638639 int SFI = RS->getScavengingFrameIndex();
639640 if (SFI >= 0)
640641 AdjustStackOffset(MFI, SFI, StackGrowsDown, Offset, MaxAlign);
644645 // If we have reserved argument space for call sites in the function
645646 // immediately on entry to the current function, count it as part of the
646647 // overall stack size.
647 if (MFI->adjustsStack() && RegInfo->hasReservedCallFrame(Fn))
648 if (MFI->adjustsStack() && TFI.hasReservedCallFrame(Fn))
648649 Offset += MFI->getMaxCallFrameSize();
649650
650651 // Round up the size to a multiple of the alignment. If the function has
8484
8585 BitVector ARMBaseRegisterInfo::
8686 getReservedRegs(const MachineFunction &MF) const {
87 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
88
8789 // FIXME: avoid re-calculating this everytime.
8890 BitVector Reserved(getNumRegs());
8991 Reserved.set(ARM::SP);
9092 Reserved.set(ARM::PC);
9193 Reserved.set(ARM::FPSCR);
92 if (hasFP(MF))
94 if (TFI->hasFP(MF))
9395 Reserved.set(FramePtr);
9496 if (hasBasePointer(MF))
9597 Reserved.set(BasePtr);
101103
102104 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
103105 unsigned Reg) const {
106 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
107
104108 switch (Reg) {
105109 default: break;
106110 case ARM::SP:
112116 break;
113117 case ARM::R7:
114118 case ARM::R11:
115 if (FramePtr == Reg && hasFP(MF))
119 if (FramePtr == Reg && TFI->hasFP(MF))
116120 return true;
117121 break;
118122 case ARM::R9:
348352 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
349353 unsigned HintType, unsigned HintReg,
350354 const MachineFunction &MF) const {
355 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
351356 // Alternative register allocation orders when favoring even / odd registers
352357 // of register pairs.
353358
429434 return std::make_pair(RC->allocation_order_begin(MF),
430435 RC->allocation_order_end(MF));
431436
432 if (!hasFP(MF)) {
437 if (!TFI->hasFP(MF)) {
433438 if (!STI.isR9Reserved())
434439 return std::make_pair(GPREven1,
435440 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
458463 return std::make_pair(RC->allocation_order_begin(MF),
459464 RC->allocation_order_end(MF));
460465
461 if (!hasFP(MF)) {
466 if (!TFI->hasFP(MF)) {
462467 if (!STI.isR9Reserved())
463468 return std::make_pair(GPROdd1,
464469 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
523528 }
524529 }
525530
526 /// hasFP - Return true if the specified function should have a dedicated frame
527 /// pointer register. This is true if the function has variable sized allocas
528 /// or if frame pointer elimination is disabled.
529 ///
530 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
531 // Mac OS X requires FP not to be clobbered for backtracing purpose.
532 if (STI.isTargetDarwin())
533 return true;
534
535 const MachineFrameInfo *MFI = MF.getFrameInfo();
536 // Always eliminate non-leaf frame pointers.
537 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
538 needsStackRealignment(MF) ||
539 MFI->hasVarSizedObjects() ||
540 MFI->isFrameAddressTaken());
541 }
542
543531 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
544532 const MachineFrameInfo *MFI = MF.getFrameInfo();
545533 const ARMFunctionInfo *AFI = MF.getInfo();
625613 /// instructions will require a scratch register during their expansion later.
626614 unsigned
627615 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
616 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
628617 const ARMFunctionInfo *AFI = MF.getInfo();
629618 unsigned Limit = (1 << 12) - 1;
630619 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
653642 case ARMII::AddrModeT2_i12:
654643 // i12 supports only positive offset so these will be converted to
655644 // i8 opcodes. See llvm::rewriteT2FrameIndex.
656 if (hasFP(MF) && AFI->hasStackFrame())
645 if (TFI->hasFP(MF) && AFI->hasStackFrame())
657646 Limit = std::min(Limit, (1U << 8) - 1);
658647 break;
659648 case ARMII::AddrMode4:
698687 unsigned NumGPRSpills = 0;
699688 SmallVector UnspilledCS1GPRs;
700689 SmallVector UnspilledCS2GPRs;
690 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
701691 ARMFunctionInfo *AFI = MF.getInfo();
702692 MachineFrameInfo *MFI = MF.getFrameInfo();
703693
812802 // worth the effort and added fragility?
813803 bool BigStack =
814804 (RS &&
815 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
805 (estimateStackSize(MF) + ((TFI->hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
816806 estimateRSStackSizeLimit(MF)))
817807 || MFI->hasVarSizedObjects()
818 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
808 || (MFI->adjustsStack() && !TFI->canSimplifyCallFramePseudos(MF));
819809
820810 bool ExtraCSSpill = false;
821811 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
833823 ExtraCSSpill = true;
834824 }
835825
836 if (hasFP(MF)) {
826 if (TFI->hasFP(MF)) {
837827 MF.getRegInfo().setPhysRegUsed(FramePtr);
838828 NumGPRSpills++;
839829 }
926916
927917 unsigned
928918 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
929 if (hasFP(MF))
919 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
920
921 if (TFI->hasFP(MF))
930922 return FramePtr;
931923 return ARM::SP;
932924 }
947939 unsigned &FrameReg,
948940 int SPAdj) const {
949941 const MachineFrameInfo *MFI = MF.getFrameInfo();
942 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
950943 const ARMFunctionInfo *AFI = MF.getInfo();
951944 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
952945 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
964957 // When dynamically realigning the stack, use the frame pointer for
965958 // parameters, and the stack/base pointer for locals.
966959 if (needsStackRealignment(MF)) {
967 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
960 assert (TFI->hasFP(MF) && "dynamic stack realignment without a FP!");
968961 if (isFixed) {
969962 FrameReg = getFrameRegister(MF);
970963 Offset = FPOffset;
977970 }
978971
979972 // If there is a frame pointer, use it when we can.
980 if (hasFP(MF) && AFI->hasStackFrame()) {
973 if (TFI->hasFP(MF) && AFI->hasStackFrame()) {
981974 // Use frame pointer to reference fixed objects. Use it for locals if
982975 // there are VLAs (and thus the SP isn't reliable as a base).
983976 if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
12511244 return EnableLocalStackAlloc;
12521245 }
12531246
1254 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1255 // not required, we reserve argument space for call sites in the function
1256 // immediately on entry to the current function. This eliminates the need for
1257 // add/sub sp brackets around call sites. Returns true if the call frame is
1258 // included as part of the stack frame.
1259 bool ARMBaseRegisterInfo::
1260 hasReservedCallFrame(const MachineFunction &MF) const {
1261 const MachineFrameInfo *FFI = MF.getFrameInfo();
1262 unsigned CFSize = FFI->getMaxCallFrameSize();
1263 // It's not always a good idea to include the call frame as part of the
1264 // stack frame. ARM (especially Thumb) has small immediate offset to
1265 // address the stack frame. So a large call frame can cause poor codegen
1266 // and may even makes it impossible to scavenge a register.
1267 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1268 return false;
1269
1270 return !MF.getFrameInfo()->hasVarSizedObjects();
1271 }
1272
1273 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
1274 // call frame pseudos can be simplified. Unlike most targets, having a FP
1275 // is not sufficient here since we still may reference some objects via SP
1276 // even when FP is available in Thumb2 mode.
1277 bool ARMBaseRegisterInfo::
1278 canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1279 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1280 }
1281
12821247 static void
12831248 emitSPUpdate(bool isARM,
12841249 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
12971262 void ARMBaseRegisterInfo::
12981263 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
12991264 MachineBasicBlock::iterator I) const {
1300 if (!hasReservedCallFrame(MF)) {
1265 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1266 if (!TFI->hasReservedCallFrame(MF)) {
13011267 // If we have alloca, convert as follows:
13021268 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
13031269 // ADJCALLSTACKUP -> add, sp, sp, amount
14281394 // Note that the incoming offset is based on the SP value at function entry,
14291395 // so it'll be negative.
14301396 MachineFunction &MF = *MI->getParent()->getParent();
1397 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
14311398 MachineFrameInfo *MFI = MF.getFrameInfo();
14321399 ARMFunctionInfo *AFI = MF.getInfo();
14331400
14551422 // don't know for sure yet whether we'll need that, so we guess based
14561423 // on whether there are any local variables that would trigger it.
14571424 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1458 if (hasFP(MF) &&
1425 if (TFI->hasFP(MF) &&
14591426 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
14601427 if (isFrameOffsetLegal(MI, FPOffset))
14611428 return false;
138138 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
139139 MachineFunction &MF) const;
140140
141 bool hasFP(const MachineFunction &MF) const;
142141 bool hasBasePointer(const MachineFunction &MF) const;
143142
144143 bool canRealignStack(const MachineFunction &MF) const;
195194
196195 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
197196
198 virtual bool hasReservedCallFrame(const MachineFunction &MF) const;
199 virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
200
201197 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
202198 MachineBasicBlock &MBB,
203199 MachineBasicBlock::iterator I) const;
2323 #include "llvm/CodeGen/MachineFrameInfo.h"
2424 #include "llvm/CodeGen/MachineFunctionPass.h"
2525 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/Target/TargetFrameInfo.h"
2627 #include "llvm/Target/TargetRegisterInfo.h"
2728 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
2829 using namespace llvm;
599600
600601 case ARM::Int_eh_sjlj_dispatchsetup: {
601602 MachineFunction &MF = *MI.getParent()->getParent();
603 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
602604 const ARMBaseInstrInfo *AII =
603605 static_cast(TII);
604606 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
609611 ARMFunctionInfo *AFI = MF.getInfo();
610612 int32_t NumBytes = AFI->getFramePtrSpillOffset();
611613 unsigned FramePtr = RI.getFrameRegister(MF);
612 assert (RI.hasFP(MF) && "base pointer without frame pointer?");
614 assert (TFI->hasFP(MF) && "base pointer without frame pointer?");
613615
614616 if (AFI->isThumb2Function()) {
615617 llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1616 #include "llvm/CodeGen/MachineFrameInfo.h"
1717 #include "llvm/CodeGen/MachineFunction.h"
1818 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetOptions.h"
1920
2021 using namespace llvm;
22
23 /// hasFP - Return true if the specified function should have a dedicated frame
24 /// pointer register. This is true if the function has variable sized allocas
25 /// or if frame pointer elimination is disabled.
26 ///
27 bool ARMFrameInfo::hasFP(const MachineFunction &MF) const {
28 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
29
30 // Mac OS X requires FP not to be clobbered for backtracing purpose.
31 if (STI.isTargetDarwin())
32 return true;
33
34 const MachineFrameInfo *MFI = MF.getFrameInfo();
35 // Always eliminate non-leaf frame pointers.
36 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
37 RegInfo->needsStackRealignment(MF) ||
38 MFI->hasVarSizedObjects() ||
39 MFI->isFrameAddressTaken());
40 }
41
42 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
43 // not required, we reserve argument space for call sites in the function
44 // immediately on entry to the current function. This eliminates the need for
45 // add/sub sp brackets around call sites. Returns true if the call frame is
46 // included as part of the stack frame.
47 bool ARMFrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
48 const MachineFrameInfo *FFI = MF.getFrameInfo();
49 unsigned CFSize = FFI->getMaxCallFrameSize();
50 // It's not always a good idea to include the call frame as part of the
51 // stack frame. ARM (especially Thumb) has small immediate offset to
52 // address the stack frame. So a large call frame can cause poor codegen
53 // and may even makes it impossible to scavenge a register.
54 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
55 return false;
56
57 return !MF.getFrameInfo()->hasVarSizedObjects();
58 }
59
60 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
61 // call frame pseudos can be simplified. Unlike most targets, having a FP
62 // is not sufficient here since we still may reference some objects via SP
63 // even when FP is available in Thumb2 mode.
64 bool ARMFrameInfo::canSimplifyCallFramePseudos(const MachineFunction &MF)const {
65 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
66 }
2167
2268 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
2369 for (unsigned i = 0; CSRegs[i]; ++i)
135181 // Otherwise, if this is not Darwin, all the callee-saved registers go
136182 // into spill area 1, including the FP in R11. In either case, it is
137183 // now safe to emit this assignment.
138 bool HasFP = RegInfo->hasFP(MF);
184 bool HasFP = hasFP(MF);
139185 if (HasFP) {
140186 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
141187 MachineInstrBuilder MIB =
169215 AFI->setShouldRestoreSPFromFP(true);
170216 }
171217
172 if (STI.isTargetELF() && RegInfo->hasFP(MF)) {
218 if (STI.isTargetELF() && hasFP(MF)) {
173219 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
174220 AFI->getFramePtrSpillOffset());
175221 AFI->setShouldRestoreSPFromFP(true);
3333 /// the function.
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36
37 bool hasFP(const MachineFunction &MF) const;
38 bool hasReservedCallFrame(const MachineFunction &MF) const;
39 bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
3640 };
3741
3842 } // End llvm namespace
890890 unsigned
891891 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
892892 MachineFunction &MF) const {
893 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
894
893895 switch (RC->getID()) {
894896 default:
895897 return 0;
896898 case ARM::tGPRRegClassID:
897 return RegInfo->hasFP(MF) ? 4 : 5;
899 return TFI->hasFP(MF) ? 4 : 5;
898900 case ARM::GPRRegClassID: {
899 unsigned FP = RegInfo->hasFP(MF) ? 1 : 0;
901 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
900902 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
901903 }
902904 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
1818 #include "llvm/CodeGen/MachineInstrBuilder.h"
1919
2020 using namespace llvm;
21
22 bool Thumb1FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
23 const MachineFrameInfo *FFI = MF.getFrameInfo();
24 unsigned CFSize = FFI->getMaxCallFrameSize();
25 // It's not always a good idea to include the call frame as part of the
26 // stack frame. ARM (especially Thumb) has small immediate offset to
27 // address the stack frame. So a large call frame can cause poor codegen
28 // and may even makes it impossible to scavenge a register.
29 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
30 return false;
31
32 return !MF.getFrameInfo()->hasVarSizedObjects();
33 }
2134
2235 static void emitSPUpdate(MachineBasicBlock &MBB,
2336 MachineBasicBlock::iterator &MBBI,
104117 }
105118
106119 // Adjust FP so it point to the stack slot that contains the previous FP.
107 if (RegInfo->hasFP(MF)) {
120 if (hasFP(MF)) {
108121 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
109122 .addFrameIndex(FramePtrSpillFI).addImm(0);
110123 AFI->setShouldRestoreSPFromFP(true);
125138 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes);
126139 }
127140
128 if (STI.isTargetELF() && RegInfo->hasFP(MF))
141 if (STI.isTargetELF() && hasFP(MF))
129142 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
130143 AFI->getFramePtrSpillOffset());
131144
3333 /// the function.
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36
37 bool hasReservedCallFrame(const MachineFunction &MF) const;
3638 };
3739
3840 } // End llvm namespace
6767 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
6868 }
6969
70 bool Thumb1RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
71 const MachineFrameInfo *FFI = MF.getFrameInfo();
72 unsigned CFSize = FFI->getMaxCallFrameSize();
73 // It's not always a good idea to include the call frame as part of the
74 // stack frame. ARM (especially Thumb) has small immediate offset to
75 // address the stack frame. So a large call frame can cause poor codegen
76 // and may even makes it impossible to scavenge a register.
77 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
78 return false;
79
80 return !MF.getFrameInfo()->hasVarSizedObjects();
81 }
82
8370
8471 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
8572 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
302289 void Thumb1RegisterInfo::
303290 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
304291 MachineBasicBlock::iterator I) const {
305 if (!hasReservedCallFrame(MF)) {
292 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
293
294 if (!TFI->hasReservedCallFrame(MF)) {
306295 // If we have alloca, convert as follows:
307296 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
308297 // ADJCALLSTACKUP -> add, sp, sp, amount
582571 MachineInstr &MI = *II;
583572 MachineBasicBlock &MBB = *MI.getParent();
584573 MachineFunction &MF = *MBB.getParent();
574 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
585575 ARMFunctionInfo *AFI = MF.getInfo();
586576 DebugLoc dl = MI.getDebugLoc();
587577
600590 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
601591 Offset -= AFI->getGPRCalleeSavedArea2Offset();
602592 else if (MF.getFrameInfo()->hasVarSizedObjects()) {
603 assert(SPAdj == 0 && hasFP(MF) && "Unexpected");
593 assert(SPAdj == 0 && TFI->hasFP(MF) && "Unexpected");
604594 // There are alloca()'s in this function, must reference off the frame
605595 // pointer or base pointer instead.
606596 if (!hasBasePointer(MF)) {
3737 unsigned PredReg = 0) const;
3838
3939 /// Code Generation virtual methods...
40 bool hasReservedCallFrame(const MachineFunction &MF) const;
41
4240 void eliminateCallFramePseudoInstr(MachineFunction &MF,
4341 MachineBasicBlock &MBB,
4442 MachineBasicBlock::iterator I) const;
3333 return l - h * Alpha::IMM_MULT;
3434 }
3535
36 // hasFP - Return true if the specified function should have a dedicated frame
37 // pointer register. This is true if the function has variable sized allocas or
38 // if frame pointer elimination is disabled.
39 //
40 bool AlphaFrameInfo::hasFP(const MachineFunction &MF) const {
41 const MachineFrameInfo *MFI = MF.getFrameInfo();
42 return MFI->hasVarSizedObjects();
43 }
44
3645 void AlphaFrameInfo::emitPrologue(MachineFunction &MF) const {
3746 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
3847 MachineBasicBlock::iterator MBBI = MBB.begin();
3948 MachineFrameInfo *MFI = MF.getFrameInfo();
40 const AlphaRegisterInfo *RegInfo =
41 static_cast(MF.getTarget().getRegisterInfo());
42 const AlphaInstrInfo &TII =
43 *static_cast(MF.getTarget().getInstrInfo());
49 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
4450
4551 DebugLoc dl = (MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc());
46 bool FP = RegInfo->hasFP(MF);
52 bool FP = hasFP(MF);
4753
4854 // Handle GOP offset
4955 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29)
98104 MachineBasicBlock &MBB) const {
99105 const MachineFrameInfo *MFI = MF.getFrameInfo();
100106 MachineBasicBlock::iterator MBBI = prior(MBB.end());
101 const AlphaRegisterInfo *RegInfo =
102 static_cast(MF.getTarget().getRegisterInfo());
103 const AlphaInstrInfo &TII =
104 *static_cast(MF.getTarget().getInstrInfo());
107 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
105108
106109 assert((MBBI->getOpcode() == Alpha::RETDAG ||
107110 MBBI->getOpcode() == Alpha::RETDAGp)
108111 && "Can only insert epilog into returning blocks");
109112 DebugLoc dl = MBBI->getDebugLoc();
110113
111 bool FP = RegInfo->hasFP(MF);
114 bool FP = hasFP(MF);
112115
113116 // Get the number of bytes allocated from the FrameInfo...
114117 long NumBytes = MFI->getStackSize();
3333 /// the function.
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36
37 bool hasFP(const MachineFunction &MF) const;
3638 };
3739
3840 } // End llvm namespace
7777 // Stack Frame Processing methods
7878 //===----------------------------------------------------------------------===//
7979
80 // hasFP - Return true if the specified function should have a dedicated frame
81 // pointer register. This is true if the function has variable sized allocas or
82 // if frame pointer elimination is disabled.
83 //
84 bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
85 const MachineFrameInfo *MFI = MF.getFrameInfo();
86 return MFI->hasVarSizedObjects();
87 }
88
8980 void AlphaRegisterInfo::
9081 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
9182 MachineBasicBlock::iterator I) const {
92 if (hasFP(MF)) {
83 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
84
85 if (TFI->hasFP(MF)) {
9386 // If we have a frame pointer, turn the adjcallstackup instruction into a
9487 // 'sub ESP, ' and the adjcallstackdown instruction into 'add ESP,
9588 // '
137130 MachineInstr &MI = *II;
138131 MachineBasicBlock &MBB = *MI.getParent();
139132 MachineFunction &MF = *MBB.getParent();
140 bool FP = hasFP(MF);
133 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
134
135 bool FP = TFI->hasFP(MF);
141136
142137 while (!MI.getOperand(i).isFI()) {
143138 ++i;
182177 }
183178
184179 unsigned AlphaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
185 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
180 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
181
182 return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30;
186183 }
187184
188185 unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
3131
3232 BitVector getReservedRegs(const MachineFunction &MF) const;
3333
34 bool hasFP(const MachineFunction &MF) const;
35
3634 void eliminateCallFramePseudoInstr(MachineFunction &MF,
3735 MachineBasicBlock &MBB,
3836 MachineBasicBlock::iterator I) const;
1515 #include "llvm/CodeGen/MachineFrameInfo.h"
1616 #include "llvm/CodeGen/MachineFunction.h"
1717 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/Target/TargetOptions.h"
1819
1920 using namespace llvm;
2021
22
23 // hasFP - Return true if the specified function should have a dedicated frame
24 // pointer register. This is true if the function has variable sized allocas or
25 // if frame pointer elimination is disabled.
26 bool BlackfinFrameInfo::hasFP(const MachineFunction &MF) const {
27 const MachineFrameInfo *MFI = MF.getFrameInfo();
28 return DisableFramePointerElim(MF) ||
29 MFI->adjustsStack() || MFI->hasVarSizedObjects();
30 }
2131
2232 // Emit a prologue that sets up a stack frame.
2333 // On function entry, R0-R2 and P0 may hold arguments.
3949 MFI->setStackSize(FrameSize);
4050 }
4151
42 if (!RegInfo->hasFP(MF)) {
52 if (!hasFP(MF)) {
4353 assert(!MFI->adjustsStack() &&
4454 "FP elimination on a non-leaf function is not supported");
4555 RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
8494 int FrameSize = MFI->getStackSize();
8595 assert(FrameSize%4 == 0 && "Misaligned frame size");
8696
87 if (!RegInfo->hasFP(MF)) {
97 if (!hasFP(MF)) {
8898 assert(!MFI->adjustsStack() &&
8999 "FP elimination on a non-leaf function is not supported");
90100 RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
3333 /// the function.
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36
37 bool hasFP(const MachineFunction &MF) const;
3638 };
3739
3840 } // End llvm namespace
4949
5050 BitVector
5151 BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
52 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
53
5254 using namespace BF;
5355 BitVector Reserved(getNumRegs());
5456 Reserved.set(AZ);
6971 Reserved.set(L3);
7072 Reserved.set(SP);
7173 Reserved.set(RETS);
72 if (hasFP(MF))
74 if (TFI->hasFP(MF))
7375 Reserved.set(FP);
7476 return Reserved;
75 }
76
77 // hasFP - Return true if the specified function should have a dedicated frame
78 // pointer register. This is true if the function has variable sized allocas or
79 // if frame pointer elimination is disabled.
80 bool BlackfinRegisterInfo::hasFP(const MachineFunction &MF) const {
81 const MachineFrameInfo *MFI = MF.getFrameInfo();
82 return DisableFramePointerElim(MF) ||
83 MFI->adjustsStack() || MFI->hasVarSizedObjects();
8477 }
8578
8679 bool BlackfinRegisterInfo::
160153 eliminateCallFramePseudoInstr(MachineFunction &MF,
161154 MachineBasicBlock &MBB,
162155 MachineBasicBlock::iterator I) const {
163 if (!hasReservedCallFrame(MF)) {
156 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
157
158 if (!TFI->hasReservedCallFrame(MF)) {
164159 int64_t Amount = I->getOperand(0).getImm();
165160 if (Amount != 0) {
166161 assert(Amount%4 == 0 && "Unaligned call frame size");
195190 MachineInstr &MI = *II;
196191 MachineBasicBlock &MBB = *MI.getParent();
197192 MachineFunction &MF = *MBB.getParent();
193 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
198194 DebugLoc DL = MI.getDebugLoc();
199195
200196 unsigned FIPos;
207203 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex)
208204 + MI.getOperand(FIPos+1).getImm();
209205 unsigned BaseReg = BF::FP;
210 if (hasFP(MF)) {
206 if (TFI->hasFP(MF)) {
211207 assert(SPAdj==0 && "Unexpected SP adjust in function with frame pointer");
212208 } else {
213209 BaseReg = BF::SP;
347343
348344 unsigned
349345 BlackfinRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
350 return hasFP(MF) ? BF::FP : BF::SP;
346 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
347
348 return TFI->hasFP(MF) ? BF::FP : BF::SP;
351349 }
352350
353351 unsigned BlackfinRegisterInfo::getEHExceptionRegister() const {
4040 return &BF::PRegClass;
4141 }
4242
43 bool hasFP(const MachineFunction &MF) const;
44
4543 // bool hasReservedCallFrame(MachineFunction &MF) const;
4644
4745 bool requiresRegisterScavenging(const MachineFunction &MF) const;
251251 PClass::iterator
252252 PClass::allocation_order_end(const MachineFunction &MF) const {
253253 const TargetMachine &TM = MF.getTarget();
254 const TargetRegisterInfo *RI = TM.getRegisterInfo();
255 return allocation_order_begin(MF)
256 + (RI->hasFP(MF) ? 7 : 6);
254 const TargetFrameInfo *TFI = TM.getFrameInfo();
255 return allocation_order_begin(MF)
256 + (TFI->hasFP(MF) ? 7 : 6);
257257 }
258258 }];
259259 }
274274 DPClass::iterator
275275 DPClass::allocation_order_end(const MachineFunction &MF) const {
276276 const TargetMachine &TM = MF.getTarget();
277 const TargetRegisterInfo *RI = TM.getRegisterInfo();
278 return allocation_order_begin(MF)
279 + (RI->hasFP(MF) ? 15 : 14);
277 const TargetFrameInfo *TFI = TM.getFrameInfo();
278 return allocation_order_begin(MF)
279 + (TFI->hasFP(MF) ? 15 : 14);
280280 }
281281 }];
282282 }
294294 GRClass::iterator
295295 GRClass::allocation_order_end(const MachineFunction &MF) const {
296296 const TargetMachine &TM = MF.getTarget();
297 const TargetRegisterInfo *RI = TM.getRegisterInfo();
298 return allocation_order_begin(MF)
299 + (RI->hasFP(MF) ? 31 : 30);
297 const TargetFrameInfo *TFI = TM.getFrameInfo();
298 return allocation_order_begin(MF)
299 + (TFI->hasFP(MF) ? 31 : 30);
300300 }
301301 }];
302302 }
317317 ALLClass::iterator
318318 ALLClass::allocation_order_end(const MachineFunction &MF) const {
319319 const TargetMachine &TM = MF.getTarget();
320 const TargetRegisterInfo *RI = TM.getRegisterInfo();
321 return allocation_order_begin(MF)
322 + (RI->hasFP(MF) ? 31 : 30);
320 const TargetFrameInfo *TFI = TM.getFrameInfo();
321 return allocation_order_begin(MF)
322 + (TFI->hasFP(MF) ? 31 : 30);
323323 }
324324 }];
325325 }
333333 PIClass::iterator
334334 PIClass::allocation_order_end(const MachineFunction &MF) const {
335335 const TargetMachine &TM = MF.getTarget();
336 const TargetRegisterInfo *RI = TM.getRegisterInfo();
337 return allocation_order_begin(MF)
338 + (RI->hasFP(MF) ? 11 : 10);
336 const TargetFrameInfo *TFI = TM.getFrameInfo();
337 return allocation_order_begin(MF)
338 + (TFI->hasFP(MF) ? 11 : 10);
339339 }
340340 }];
341341 }
3838 }
3939
4040
41 //--------------------------------------------------------------------------
42 // hasFP - Return true if the specified function actually has a dedicated frame
43 // pointer register. This is true if the function needs a frame pointer and has
44 // a non-zero stack size.
45 bool SPUFrameInfo::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47
48 return MFI->getStackSize() &&
49 (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects());
50 }
51
52
4153 /// determineFrameLayout - Determine the size of the frame and maximum call
4254 /// frame size.
4355 void SPUFrameInfo::determineFrameLayout(MachineFunction &MF) const {
3535 /// the function.
3636 void emitPrologue(MachineFunction &MF) const;
3737 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
38
39 //! Prediate: Target has dedicated frame pointer
40 bool hasFP(const MachineFunction &MF) const;
3841
3942 //! Return a function's saved spill slots
4043 /*!
239239 // Stack Frame Processing methods
240240 //===----------------------------------------------------------------------===//
241241
242 // needsFP - Return true if the specified function should have a dedicated frame
243 // pointer register. This is true if the function has variable sized allocas or
244 // if frame pointer elimination is disabled.
245 //
246 static bool needsFP(const MachineFunction &MF) {
247 const MachineFrameInfo *MFI = MF.getFrameInfo();
248 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
249 }
250
251 //--------------------------------------------------------------------------
252 // hasFP - Return true if the specified function actually has a dedicated frame
253 // pointer register. This is true if the function needs a frame pointer and has
254 // a non-zero stack size.
255 bool
256 SPURegisterInfo::hasFP(const MachineFunction &MF) const {
257 const MachineFrameInfo *MFI = MF.getFrameInfo();
258 return MFI->getStackSize() && needsFP(MF);
259 }
260
261242 //--------------------------------------------------------------------------
262243 void
263244 SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
5555 //! Return the reserved registers
5656 BitVector getReservedRegs(const MachineFunction &MF) const;
5757
58 //! Prediate: Target has dedicated frame pointer
59 bool hasFP(const MachineFunction &MF) const;
6058 //! Eliminate the call frame setup pseudo-instructions
6159 void eliminateCallFramePseudoInstr(MachineFunction &MF,
6260 MachineBasicBlock &MBB,
3939 //
4040 //===----------------------------------------------------------------------===//
4141
42 // hasFP - Return true if the specified function should have a dedicated frame
43 // pointer register. This is true if the function has variable sized allocas or
44 // if frame pointer elimination is disabled.
45 bool MBlazeFrameInfo::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
48 }
49
4250 void MBlazeFrameInfo::adjustMBlazeStackFrame(MachineFunction &MF) const {
4351 MachineFrameInfo *MFI = MF.getFrameInfo();
4452 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
45 const MBlazeRegisterInfo *RegInfo =
46 static_cast(MF.getTarget().getRegisterInfo());
4753
4854 // See the description at MicroBlazeMachineFunction.h
4955 int TopCPUSavedRegOff = -1;
6066 MBlazeFI->adjustLoadArgsFI(MFI);
6167 MBlazeFI->adjustStoreVarArgsFI(MFI);
6268
63 if (RegInfo->hasFP(MF)) {
69 if (hasFP(MF)) {
6470 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
6571 StackOffset);
6672 MBlazeFI->setFPStackOffset(StackOffset);
8995 void MBlazeFrameInfo::emitPrologue(MachineFunction &MF) const {
9096 MachineBasicBlock &MBB = MF.front();
9197 MachineFrameInfo *MFI = MF.getFrameInfo();
92 const MBlazeRegisterInfo *RegInfo =
93 static_cast(MF.getTarget().getRegisterInfo());
9498 const MBlazeInstrInfo &TII =
9599 *static_cast(MF.getTarget().getInstrInfo());
96100 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
123127
124128 // if framepointer enabled, save it and set it
125129 // to point to the stack pointer
126 if (RegInfo->hasFP(MF)) {
130 if (hasFP(MF)) {
127131 // swi R19, R1, stack_loc
128132 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
129133 .addReg(MBlaze::R19).addReg(MBlaze::R1).addImm(FPOffset);
138142 MachineBasicBlock &MBB) const {
139143 MachineBasicBlock::iterator MBBI = prior(MBB.end());
140144 MachineFrameInfo *MFI = MF.getFrameInfo();
141 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
142 const MBlazeRegisterInfo *RegInfo =
143 static_cast(MF.getTarget().getRegisterInfo());
145 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
144146 const MBlazeInstrInfo &TII =
145147 *static_cast(MF.getTarget().getInstrInfo());
146148
152154
153155 // if framepointer enabled, restore it and restore the
154156 // stack pointer
155 if (RegInfo->hasFP(MF)) {
157 if (hasFP(MF)) {
156158 // add R1, R19, R0
157159 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADD), MBlaze::R1)
158160 .addReg(MBlaze::R19).addReg(MBlaze::R0);
4040 /// the function.
4141 void emitPrologue(MachineFunction &MF) const;
4242 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
43
44 bool hasFP(const MachineFunction &MF) const;
4345 };
4446
4547 } // End llvm namespace
163163 return Reserved;
164164 }
165165
166 // hasFP - Return true if the specified function should have a dedicated frame
167 // pointer register. This is true if the function has variable sized allocas or
168 // if frame pointer elimination is disabled.
169 bool MBlazeRegisterInfo::hasFP(const MachineFunction &MF) const {
170 const MachineFrameInfo *MFI = MF.getFrameInfo();
171 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
172 }
173
174166 // This function eliminate ADJCALLSTACKDOWN,
175167 // ADJCALLSTACKUP pseudo instructions
176168 void MBlazeRegisterInfo::
234226 }
235227
236228 unsigned MBlazeRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
237 return hasFP(MF) ? MBlaze::R19 : MBlaze::R1;
229 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
230
231 return TFI->hasFP(MF) ? MBlaze::R19 : MBlaze::R1;
238232 }
239233
240234 unsigned MBlazeRegisterInfo::getEHExceptionRegister() const {
5555
5656 BitVector getReservedRegs(const MachineFunction &MF) const;
5757
58 bool hasFP(const MachineFunction &MF) const;
59
6058 void eliminateCallFramePseudoInstr(MachineFunction &MF,
6159 MachineBasicBlock &MBB,
6260 MachineBasicBlock::iterator I) const;
2525
2626 using namespace llvm;
2727
28 bool MSP430FrameInfo::hasFP(const MachineFunction &MF) const {
29 const MachineFrameInfo *MFI = MF.getFrameInfo();
30
31 return (DisableFramePointerElim(MF) ||
32 MF.getFrameInfo()->hasVarSizedObjects() ||
33 MFI->isFrameAddressTaken());
34 }
35
36 bool MSP430FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
37 return !MF.getFrameInfo()->hasVarSizedObjects();
38 }
39
2840 void MSP430FrameInfo::emitPrologue(MachineFunction &MF) const {
2941 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
3042 MachineFrameInfo *MFI = MF.getFrameInfo();
3143 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo();
32 const MSP430RegisterInfo *RegInfo =
33 static_cast(MF.getTarget().getRegisterInfo());
3444 const MSP430InstrInfo &TII =
3545 *static_cast(MF.getTarget().getInstrInfo());
3646
4151 uint64_t StackSize = MFI->getStackSize();
4252
4353 uint64_t NumBytes = 0;
44 if (RegInfo->hasFP(MF)) {
54 if (hasFP(MF)) {
4555 // Calculate required stack adjustment
4656 uint64_t FrameSize = StackSize - 2;
4757 NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
96106 MachineBasicBlock &MBB) const {
97107 const MachineFrameInfo *MFI = MF.getFrameInfo();
98108 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo();
99 const MSP430RegisterInfo *RegInfo =
100 static_cast(MF.getTarget().getRegisterInfo());
101109 const MSP430InstrInfo &TII =
102110 *static_cast(MF.getTarget().getInstrInfo());
103111
117125 unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
118126 uint64_t NumBytes = 0;
119127
120 if (RegInfo->hasFP(MF)) {
128 if (hasFP(MF)) {
121129 // Calculate required stack adjustment
122130 uint64_t FrameSize = StackSize - 2;
123131 NumBytes = FrameSize - CSSize;
3333 /// the function.
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36
37 bool hasFP(const MachineFunction &MF) const;
38 bool hasReservedCallFrame(const MachineFunction &MF) const;
3639 };
3740
3841 } // End llvm namespace
3737
3838 const unsigned*
3939 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
40 const TargetFrameInfo *TFI = MF->getTarget().getFrameInfo();
4041 const Function* F = MF->getFunction();
4142 static const unsigned CalleeSavedRegs[] = {
4243 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
6162 0
6263 };
6364
64 if (hasFP(*MF))
65 if (TFI->hasFP(*MF))
6566 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
6667 CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
6768 else
7273
7374 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
7475 BitVector Reserved(getNumRegs());
76 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
7577
7678 // Mark 4 special registers as reserved.
7779 Reserved.set(MSP430::PCW);
8082 Reserved.set(MSP430::CGW);
8183
8284 // Mark frame pointer as reserved if needed.
83 if (hasFP(MF))
85 if (TFI->hasFP(MF))
8486 Reserved.set(MSP430::FPW);
8587
8688 return Reserved;
9193 return &MSP430::GR16RegClass;
9294 }
9395
94
95 bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
96 const MachineFrameInfo *MFI = MF.getFrameInfo();
97
98 return (DisableFramePointerElim(MF) ||
99 MF.getFrameInfo()->hasVarSizedObjects() ||
100 MFI->isFrameAddressTaken());
101 }
102
103 bool MSP430RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
104 return !MF.getFrameInfo()->hasVarSizedObjects();
105 }
106
10796 void MSP430RegisterInfo::
10897 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
10998 MachineBasicBlock::iterator I) const {
110 if (!hasReservedCallFrame(MF)) {
99 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
100
101 if (!TFI->hasReservedCallFrame(MF)) {
111102 // If the stack pointer can be changed after prologue, turn the
112103 // adjcallstackup instruction into a 'sub SPW, ' and the
113104 // adjcallstackdown instruction into 'add SPW, '
171162 MachineInstr &MI = *II;
172163 MachineBasicBlock &MBB = *MI.getParent();
173164 MachineFunction &MF = *MBB.getParent();
165 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
174166 DebugLoc dl = MI.getDebugLoc();
175167 while (!MI.getOperand(i).isFI()) {
176168 ++i;
179171
180172 int FrameIndex = MI.getOperand(i).getIndex();
181173
182 unsigned BasePtr = (hasFP(MF) ? MSP430::FPW : MSP430::SPW);
174 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
183175 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
184176
185177 // Skip the saved PC
186178 Offset += 2;
187179
188 if (!hasFP(MF))
180 if (!TFI->hasFP(MF))
189181 Offset += MF.getFrameInfo()->getStackSize();
190182 else
191183 Offset += 2; // Skip the saved FPW
223215 void
224216 MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
225217 const {
218 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
219
226220 // Create a frame entry for the FPW register that must be saved.
227 if (hasFP(MF)) {
221 if (TFI->hasFP(MF)) {
228222 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true);
229223 (void)FrameIdx;
230224 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
237231 }
238232
239233 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
240 return hasFP(MF) ? MSP430::FPW : MSP430::SPW;
234 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
235
236 return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
241237 }
242238
243239 int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
3838 BitVector getReservedRegs(const MachineFunction &MF) const;
3939 const TargetRegisterClass* getPointerRegClass(unsigned Kind = 0) const;
4040
41 bool hasFP(const MachineFunction &MF) const;
42 bool hasReservedCallFrame(const MachineFunction &MF) const;
43
4441 void eliminateCallFramePseudoInstr(MachineFunction &MF,
4542 MachineBasicBlock &MBB,
4643 MachineBasicBlock::iterator I) const;
7878 GR8Class::iterator
7979 GR8Class::allocation_order_end(const MachineFunction &MF) const {
8080 const TargetMachine &TM = MF.getTarget();
81 const TargetRegisterInfo *RI = TM.getRegisterInfo();
81 const TargetFrameInfo *TFI = TM.getFrameInfo();
8282 // Depending on whether the function uses frame pointer or not, last 5 or 4
8383 // registers on the list above are reserved
84 if (RI->hasFP(MF))
84 if (TFI->hasFP(MF))
8585 return end()-5;
8686 else
8787 return end()-4;
105105 GR16Class::iterator
106106 GR16Class::allocation_order_end(const MachineFunction &MF) const {
107107 const TargetMachine &TM = MF.getTarget();
108 const TargetRegisterInfo *RI = TM.getRegisterInfo();
108 const TargetFrameInfo *TFI = TM.getFrameInfo();
109109 // Depending on whether the function uses frame pointer or not, last 5 or 4
110110 // registers on the list above are reserved
111 if (RI->hasFP(MF))
111 if (TFI->hasFP(MF))
112112 return end()-5;
113113 else
114114 return end()-4;
124124 // Create a bitmask with all callee saved registers for CPU or Floating Point
125125 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
126126 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
127 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
127 const TargetFrameInfo *TFI = TM.getFrameInfo();
128 const TargetRegisterInfo *RI = TM.getRegisterInfo();
128129 const MipsFunctionInfo *MipsFI = MF->getInfo();
129
130
130131 // CPU and FPU Saved Registers Bitmasks
131132 unsigned int CPUBitmask = 0;
132133 unsigned int FPUBitmask = 0;
144145 }
145146
146147 // Return Address and Frame registers must also be set in CPUBitmask.
147 if (RI.hasFP(*MF))
148 if (TFI->hasFP(*MF))
148149 CPUBitmask |= (1 << MipsRegisterInfo::
149 getRegisterNumbering(RI.getFrameRegister(*MF)));
150
151 if (MFI->adjustsStack())
150 getRegisterNumbering(RI->getFrameRegister(*MF)));
151
152 if (MFI->adjustsStack())
152153 CPUBitmask |= (1 << MipsRegisterInfo::
153 getRegisterNumbering(RI.getRARegister()));
154 getRegisterNumbering(RI->getRARegister()));
154155
155156 // Print CPUBitmask
156157 O << "\t.mask \t"; printHex32(CPUBitmask, O);
7878 //
7979 //===----------------------------------------------------------------------===//
8080
81 // hasFP - Return true if the specified function should have a dedicated frame
82 // pointer register. This is true if the function has variable sized allocas or
83 // if frame pointer elimination is disabled.
84 bool MipsFrameInfo::hasFP(const MachineFunction &MF) const {
85 const MachineFrameInfo *MFI = MF.getFrameInfo();
86 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
87 }
88
8189 void MipsFrameInfo::adjustMipsStackFrame(MachineFunction &MF) const {
8290 MachineFrameInfo *MFI = MF.getFrameInfo();
8391 MipsFunctionInfo *MipsFI = MF.getInfo();
84 const MipsRegisterInfo *RegInfo =
85 static_cast(MF.getTarget().getRegisterInfo());
8692 const std::vector &CSI = MFI->getCalleeSavedInfo();
8793 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
8894 unsigned RegSize = STI.isGP32bit() ? 4 : 8;
151157
152158 // Stack locations for FP and RA. If only one of them is used,
153159 // the space must be allocated for both, otherwise no space at all.
154 if (RegInfo->hasFP(MF) || MFI->adjustsStack()) {
160 if (hasFP(MF) || MFI->adjustsStack()) {
155161 // FP stack location
156162 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
157163 StackOffset);
241247
242248 // if framepointer enabled, save it and set it
243249 // to point to the stack pointer
244 if (RegInfo->hasFP(MF)) {
250 if (hasFP(MF)) {
245251 // sw $fp,stack_loc($sp)
246252 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
247253 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
262268 MachineBasicBlock::iterator MBBI = prior(MBB.end());
263269 MachineFrameInfo *MFI = MF.getFrameInfo();
264270 MipsFunctionInfo *MipsFI = MF.getInfo();
265 const MipsRegisterInfo *RegInfo =
266 static_cast(MF.getTarget().getRegisterInfo());
267271 const MipsInstrInfo &TII =
268272 *static_cast(MF.getTarget().getInstrInfo());
269273 DebugLoc dl = MBBI->getDebugLoc();
277281
278282 // if framepointer enabled, restore it and restore the
279283 // stack pointer
280 if (RegInfo->hasFP(MF)) {
284 if (hasFP(MF)) {
281285 // move $sp, $fp
282286 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
283287 .addReg(Mips::FP).addReg(Mips::ZERO);
3636 /// the function.
3737 void emitPrologue(MachineFunction &MF) const;
3838 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
39
40 bool hasFP(const MachineFunction &MF) const;
3941 };
4042
4143 } // End llvm namespace
116116 }
117117
118118 BitVector MipsRegisterInfo::
119 getReservedRegs(const MachineFunction &MF) const
120 {
119 getReservedRegs(const MachineFunction &MF) const {
121120 BitVector Reserved(getNumRegs());
122121 Reserved.set(Mips::ZERO);
123122 Reserved.set(Mips::AT);
136135 return Reserved;
137136 }
138137
139 // hasFP - Return true if the specified function should have a dedicated frame
140 // pointer register. This is true if the function has variable sized allocas or
141 // if frame pointer elimination is disabled.
142 bool MipsRegisterInfo::
143 hasFP(const MachineFunction &MF) const {
144 const MachineFrameInfo *MFI = MF.getFrameInfo();
145 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
146 }
147
148138 // This function eliminate ADJCALLSTACKDOWN,
149139 // ADJCALLSTACKUP pseudo instructions
150140 void MipsRegisterInfo::
208198
209199 unsigned MipsRegisterInfo::
210200 getFrameRegister(const MachineFunction &MF) const {
211 return hasFP(MF) ? Mips::FP : Mips::SP;
201 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
202
203 return TFI->hasFP(MF) ? Mips::FP : Mips::SP;
212204 }
213205
214206 unsigned MipsRegisterInfo::
4343
4444 BitVector getReservedRegs(const MachineFunction &MF) const;
4545
46 bool hasFP(const MachineFunction &MF) const;
47
4846 void eliminateCallFramePseudoInstr(MachineFunction &MF,
4947 MachineBasicBlock &MBB,
5048 MachineBasicBlock::iterator I) const;
3333 /// the function.
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36
37 bool hasFP(const MachineFunction &MF) const { return false; }
3638 };
3739
3840 } // End llvm namespace
3737 return Reserved; // reserve no regs
3838 }
3939
40 virtual bool hasFP(const MachineFunction &MF) const { return false; }
41
4240 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
4341 int SPAdj,
4442 RegScavenger *RS = NULL) const {
221221 MFI->setStackSize(FrameSize);
222222 }
223223
224 // hasFP - Return true if the specified function actually has a dedicated frame
225 // pointer register.
226 bool PPCFrameInfo::hasFP(const MachineFunction &MF) const {
227 const MachineFrameInfo *MFI = MF.getFrameInfo();
228
229 // Naked functions have no stack frame pushed, so we don't have a frame
230 // pointer.
231 if (MF.getFunction()->hasFnAttr(Attribute::Naked))
232 return false;
233
234 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() ||
235 (GuaranteedTailCallOpt && MF.getInfo()->hasFastCall());
236 }
237
238
224239 void PPCFrameInfo::emitPrologue(MachineFunction &MF) const {
225240 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
226241 MachineBasicBlock::iterator MBBI = MBB.begin();
227242 MachineFrameInfo *MFI = MF.getFrameInfo();
228 const PPCRegisterInfo *RegInfo =
229 static_cast(MF.getTarget().getRegisterInfo());
230243 const PPCInstrInfo &TII =
231244 *static_cast(MF.getTarget().getInstrInfo());
232245
265278 PPCFunctionInfo *FI = MF.getInfo();
266279 bool MustSaveLR = FI->mustSaveLR();
267280 // Do we have a frame pointer for this function?
268 bool HasFP = RegInfo->hasFP(MF) && FrameSize;
281 bool HasFP = hasFP(MF) && FrameSize;
269282
270283 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
271284
470483 void PPCFrameInfo::emitEpilogue(MachineFunction &MF,
471484 MachineBasicBlock &MBB) const {
472485 MachineBasicBlock::iterator MBBI = prior(MBB.end());
473 const PPCRegisterInfo *RegInfo =
474 static_cast(MF.getTarget().getRegisterInfo());
475486 const PPCInstrInfo &TII =
476487 *static_cast(MF.getTarget().getInstrInfo());
477488
478489 unsigned RetOpcode = MBBI->getOpcode();
479490 DebugLoc dl;
480491
481 assert( (RetOpcode == PPC::BLR ||
482 RetOpcode == PPC::TCRETURNri ||
483 RetOpcode == PPC::TCRETURNdi ||
484 RetOpcode == PPC::TCRETURNai ||
485 RetOpcode == PPC::TCRETURNri8 ||
486 RetOpcode == PPC::TCRETURNdi8 ||
487 RetOpcode == PPC::TCRETURNai8) &&
492 assert((RetOpcode == PPC::BLR ||
493 RetOpcode == PPC::TCRETURNri ||
494 RetOpcode == PPC::TCRETURNdi ||
495 RetOpcode == PPC::TCRETURNai ||
496 RetOpcode == PPC::TCRETURNri8 ||
497 RetOpcode == PPC::TCRETURNdi8 ||
498 RetOpcode == PPC::TCRETURNai8) &&
488499 "Can only insert epilog into returning blocks");
489500
490501 // Get alignment info so we know how to restore r1
503514 PPCFunctionInfo *FI = MF.getInfo();
504515 bool MustSaveLR = FI->mustSaveLR();
505516 // Do we have a frame pointer for this function?
506 bool HasFP = RegInfo->hasFP(MF) && FrameSize;
517 bool HasFP = hasFP(MF) && FrameSize;
507518
508519 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
509520
549560 // call which invalidates the stack pointer value in SP(0). So we use the
550561 // value of R31 in this case.
551562 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
552 assert(RegInfo->hasFP(MF) && "Expecting a valid the frame pointer.");
563 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
553564 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
554565 .addReg(PPC::R31).addImm(FrameSize);
555566 } else if(FI->hasFastCall()) {
573584 }
574585 } else {
575586 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
576 assert(RegInfo->hasFP(MF) && "Expecting a valid the frame pointer.");
587 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
577588 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
578589 .addReg(PPC::X31).addImm(FrameSize);
579590 } else if(FI->hasFastCall()) {
3535 /// the function.
3636 void emitPrologue(MachineFunction &MF) const;
3737 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
38
39 bool hasFP(const MachineFunction &MF) const;
3840
3941 /// targetHandlesStackFrameRounding - Returns true if the target is
4042 /// responsible for rounding up the stack frame (probably at emitPrologue
258258 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs;
259259 }
260260
261 // needsFP - Return true if the specified function should have a dedicated frame
262 // pointer register. This is true if the function has variable sized allocas or
263 // if frame pointer elimination is disabled.
264 //
265 static bool needsFP(const MachineFunction &MF) {
266 const MachineFrameInfo *MFI = MF.getFrameInfo();
267 // Naked functions have no stack frame pushed, so we don't have a frame pointer.
268 if (MF.getFunction()->hasFnAttr(Attribute::Naked))
269 return false;
270 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() ||
271 (GuaranteedTailCallOpt && MF.getInfo()->hasFastCall());
272 }
273
274261 static bool spillsCR(const MachineFunction &MF) {
275262 const PPCFunctionInfo *FuncInfo = MF.getInfo();
276263 return FuncInfo->isCRSpilled();
278265
279266 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
280267 BitVector Reserved(getNumRegs());
268 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
269
281270 Reserved.set(PPC::R0);
282271 Reserved.set(PPC::R1);
283272 Reserved.set(PPC::LR);
323312 }
324313 }
325314
326 if (needsFP(MF))
315 if (TFI->hasFP(MF))
327316 Reserved.set(PPC::R31);
328317
329318 return Reserved;
332321 //===----------------------------------------------------------------------===//
333322 // Stack Frame Processing methods
334323 //===----------------------------------------------------------------------===//
335
336 // hasFP - Return true if the specified function actually has a dedicated frame
337 // pointer register. This is true if the function needs a frame pointer and has
338 // a non-zero stack size.
339 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
340 const MachineFrameInfo *MFI = MF.getFrameInfo();
341 return MFI->getStackSize() && needsFP(MF);
342 }
343324
344325 /// MustSaveLR - Return true if this function requires that we save the LR
345326 /// register onto the stack in the prolog and restore it in the epilog of the
582563 MachineFunction &MF = *MBB.getParent();
583564 // Get the frame info.
584565 MachineFrameInfo *MFI = MF.getFrameInfo();
566 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
585567 DebugLoc dl = MI.getDebugLoc();
586568
587569 // Find out which operand is the frame index.
621603 }
622604
623605 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
624 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
606 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ?
607 PPC::R31 : PPC::R1,
625608 false);
626609
627610 // Figure out if the offset in the instruction is shifted right two bits. This
707690 void
708691 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
709692 RegScavenger *RS) const {
693 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
694
710695 // Save and clear the LR state.
711696 PPCFunctionInfo *FI = MF.getInfo();
712697 unsigned LR = getRARegister();
718703 bool isPPC64 = Subtarget.isPPC64();
719704 bool isDarwinABI = Subtarget.isDarwinABI();
720705 MachineFrameInfo *MFI = MF.getFrameInfo();
721
706
722707 // If the frame pointer save index hasn't been defined yet.
723 if (!FPSI && needsFP(MF)) {
708 if (!FPSI && TFI->hasFP(MF)) {
724709 // Find out what the fix offset of the frame pointer save area.
725710 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
726711 isDarwinABI);
735720 if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
736721 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
737722 }
738
723
739724 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
740725 // a large stack, which will require scavenging a register to materialize a
741726 // large offset.
744729 // r0 for now.
745730
746731 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
747 if (needsFP(MF) || spillsCR(MF)) {
732 if (TFI->hasFP(MF) || spillsCR(MF)) {
748733 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
749734 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
750735 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
765750 // Get callee saved register information.
766751 MachineFrameInfo *FFI = MF.getFrameInfo();
767752 const std::vector &CSI = FFI->getCalleeSavedInfo();
753 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
768754
769755 // Early exit if no callee saved registers are modified!
770 if (CSI.empty() && !needsFP(MF)) {
756 if (CSI.empty() && !TFI->hasFP(MF)) {
771757 return;
772758 }
773
759
774760 unsigned MinGPR = PPC::R31;
775761 unsigned MinG8R = PPC::X31;
776762 unsigned MinFPR = PPC::F31;
857843
858844 // Check whether the frame pointer register is allocated. If so, make sure it
859845 // is spilled to the correct offset.
860 if (needsFP(MF)) {
846 if (TFI->hasFP(MF)) {
861847 HasGPSaveArea = true;
862848
863849 int FI = PFI->getFramePointerSaveIndex();
948934 }
949935
950936 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
937 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
938
951939 if (!Subtarget.isPPC64())
952 return hasFP(MF) ? PPC::R31 : PPC::R1;
940 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
953941 else
954 return hasFP(MF) ? PPC::X31 : PPC::X1;
942 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
955943 }
956944
957945 void PPCRegisterInfo::getInitialFrameState(std::vector &Moves)
4747 /// FIXME (64-bit): Should be inlined.
4848 bool requiresRegisterScavenging(const MachineFunction &MF) const;
4949
50 bool hasFP(const MachineFunction &MF) const;
51
5250 void eliminateCallFramePseudoInstr(MachineFunction &MF,
5351 MachineBasicBlock &MBB,
5452 MachineBasicBlock::iterator I) const;
6361 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
6462 RegScavenger *RS = NULL) const;
6563 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
66
67 void emitPrologue(MachineFunction &MF) const;
68 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
6964
7065 // Debug information queries.
7166 unsigned getRARegister() const;
299299 // R31 when the FP is not needed.
300300 // When using the 32-bit SVR4 ABI, r13 is reserved for the Small Data Area
301301 // pointer.
302 const PPCSubtarget &Subtarget
303 = MF.getTarget().getSubtarget();
304
302 const PPCSubtarget &Subtarget = MF.getTarget().getSubtarget();
303 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
304
305305 if (Subtarget.isPPC64() || Subtarget.isSVR4ABI())
306306 return end()-5; // don't allocate R13, R31, R0, R1, LR
307307
308 if (needsFP(MF))
308 if (TFI->hasFP(MF))
309309 return end()-4; // don't allocate R31, R0, R1, LR
310310 else
311311 return end()-3; // don't allocate R0, R1, LR
330330 }
331331 G8RCClass::iterator
332332 G8RCClass::allocation_order_end(const MachineFunction &MF) const {
333 if (needsFP(MF))
333 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
334 if (TFI->hasFP(MF))
334335 return end()-5;
335336 else
336337 return end()-4;
3131 /// the function.
3232 void emitPrologue(MachineFunction &MF) const;
3333 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
34
35 bool hasFP(const MachineFunction &MF) const { return false; }
3436 };
3537
3638 } // End llvm namespace
4949 Reserved.set(SP::G6);
5050 Reserved.set(SP::G7);
5151 return Reserved;
52 }
53
54 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
55 return false;
5652 }
5753
5854 void SparcRegisterInfo::
3333
3434 BitVector getReservedRegs(const MachineFunction &MF) const;
3535
36 bool hasFP(const MachineFunction &MF) const;
37
3836 void eliminateCallFramePseudoInstr(MachineFunction &MF,
3937 MachineBasicBlock &MBB,
4038 MachineBasicBlock::iterator I) const;
2525 #include "llvm/Support/CommandLine.h"
2626
2727 using namespace llvm;
28
29
30 /// needsFP - Return true if the specified function should have a dedicated
31 /// frame pointer register. This is true if the function has variable sized
32 /// allocas or if frame pointer elimination is disabled.
33 bool SystemZFrameInfo::hasFP(const MachineFunction &MF) const {
34 const MachineFrameInfo *MFI = MF.getFrameInfo();
35 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
36 }
2837
2938 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
3039 /// stack pointer by a constant value.
6069 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
6170 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
6271 MachineFrameInfo *MFI = MF.getFrameInfo();
63 const SystemZRegisterInfo *RegInfo =
64 static_cast(MF.getTarget().getRegisterInfo());
6572 const SystemZInstrInfo &TII =
6673 *static_cast(MF.getTarget().getInstrInfo());
6774 SystemZMachineFunctionInfo *SystemZMFI =
93100 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, TII);
94101 }
95102
96 if (RegInfo->hasFP(MF)) {
103 if (hasFP(MF)) {
97104 // Update R11 with the new base value...
98105 BuildMI(MBB, MBBI, DL, TII.get(SystemZ::MOV64rr), SystemZ::R11D)
99106 .addReg(SystemZ::R15D);
3333 /// the function.
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36
37 bool hasReservedCallFrame(const MachineFunction &MF) const { return true; }
38 bool hasFP(const MachineFunction &MF) const;
3639 };
3740
3841 } // End llvm namespace
376376 const SmallVectorImpl &Ins,
377377 DebugLoc dl, SelectionDAG &DAG,
378378 SmallVectorImpl &InVals) const {
379
380379 MachineFunction &MF = DAG.getMachineFunction();
380 const TargetFrameInfo *TFI = TM.getFrameInfo();
381381
382382 // Offset to first argument stack slot.
383383 const unsigned FirstArgOffset = 160;
430430 if (StackPtr.getNode() == 0)
431431 StackPtr =
432432 DAG.getCopyFromReg(Chain, dl,
433 (RegInfo->hasFP(MF) ?
433 (TFI->hasFP(MF) ?
434434 SystemZ::R11D : SystemZ::R15D),
435435 getPointerTy());
436436
296296 if (MI != MBB.end()) DL = MI->getDebugLoc();
297297
298298 MachineFunction &MF = *MBB.getParent();
299 const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo();
299 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
300300 SystemZMachineFunctionInfo *MFI = MF.getInfo();
301301
302302 // Restore FP registers
322322 if (LowReg != HighReg)
323323 MIB.addReg(HighReg, RegState::Define);
324324
325 MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D));
325 MIB.addReg(TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
326326 MIB.addImm(StartOffset);
327327 if (LowReg == HighReg)
328328 MIB.addReg(0);
4848
4949 BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
5050 BitVector Reserved(getNumRegs());
51 if (hasFP(MF))
51 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
52
53 if (TFI->hasFP(MF))
5254 Reserved.set(SystemZ::R11D);
5355 Reserved.set(SystemZ::R14D);
5456 Reserved.set(SystemZ::R15D);
5557 return Reserved;
56 }
57
58 /// needsFP - Return true if the specified function should have a dedicated
59 /// frame pointer register. This is true if the function has variable sized
60 /// allocas or if frame pointer elimination is disabled.
61 bool SystemZRegisterInfo::hasFP(const MachineFunction &MF) const {
62 const MachineFrameInfo *MFI = MF.getFrameInfo();
63 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
6458 }
6559
6660 void SystemZRegisterInfo::
9993 unsigned i = 0;
10094 MachineInstr &MI = *II;
10195 MachineFunction &MF = *MI.getParent()->getParent();
96 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
97
10298 while (!MI.getOperand(i).isFI()) {
10399 ++i;
104100 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
106102
107103 int FrameIndex = MI.getOperand(i).getIndex();
108104
109 unsigned BasePtr = (hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
105 unsigned BasePtr = (TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
110106
111107 // This must be part of a rri or ri operand memory reference. Replace the
112108 // FrameIndex with base register with BasePtr. Add an offset to the
3333
3434 BitVector getReservedRegs(const MachineFunction &MF) const;
3535
36 bool hasReservedCallFrame(const MachineFunction &MF) const { return true; }
37 bool hasFP(const MachineFunction &MF) const;
38
3936 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
4037
4138 void eliminateCallFramePseudoInstr(MachineFunction &MF,
189189 GR32Class::iterator
190190 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
191191 const TargetMachine &TM = MF.getTarget();
192 const TargetRegisterInfo *RI = TM.getRegisterInfo();
193 if (RI->hasFP(MF))
192 const TargetFrameInfo *TFI = TM.getFrameInfo();
193 if (TFI->hasFP(MF))
194194 return SystemZ_REG32_nofp;
195195 else
196196 return SystemZ_REG32;
198198 GR32Class::iterator
199199 GR32Class::allocation_order_end(const MachineFunction &MF) const {
200200 const TargetMachine &TM = MF.getTarget();
201 const TargetRegisterInfo *RI = TM.getRegisterInfo();
202 if (RI->hasFP(MF))
201 const TargetFrameInfo *TFI = TM.getFrameInfo();
202 if (TFI->hasFP(MF))
203203 return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned));
204204 else
205205 return SystemZ_REG32 + (sizeof(SystemZ_REG32) / sizeof(unsigned));
236236 ADDR32Class::iterator
237237 ADDR32Class::allocation_order_begin(const MachineFunction &MF) const {
238238 const TargetMachine &TM = MF.getTarget();
239 const TargetRegisterInfo *RI = TM.getRegisterInfo();
240 if (RI->hasFP(MF))
239 const TargetFrameInfo *TFI = TM.getFrameInfo();
240 if (TFI->hasFP(MF))
241241 return SystemZ_ADDR32_nofp;
242242 else
243243 return SystemZ_ADDR32;
245245 ADDR32Class::iterator
246246 ADDR32Class::allocation_order_end(const MachineFunction &MF) const {
247247 const TargetMachine &TM = MF.getTarget();
248 const TargetRegisterInfo *RI = TM.getRegisterInfo();
249 if (RI->hasFP(MF))
248 const TargetFrameInfo *TFI = TM.getFrameInfo();
249 if (TFI->hasFP(MF))
250250 return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned));
251251 else
252252 return SystemZ_ADDR32 + (sizeof(SystemZ_ADDR32) / sizeof(unsigned));
283283 GR64Class::iterator
284284 GR64Class::allocation_order_begin(const MachineFunction &MF) const {
285285 const TargetMachine &TM = MF.getTarget();
286 const TargetRegisterInfo *RI = TM.getRegisterInfo();
287 if (RI->hasFP(MF))
286 const TargetFrameInfo *TFI = TM.getFrameInfo();
287 if (TFI->hasFP(MF))
288288 return SystemZ_REG64_nofp;
289289 else
290290 return SystemZ_REG64;
292292 GR64Class::iterator
293293 GR64Class::allocation_order_end(const MachineFunction &MF) const {
294294 const TargetMachine &TM = MF.getTarget();
295 const TargetRegisterInfo *RI = TM.getRegisterInfo();
296 if (RI->hasFP(MF))
295 const TargetFrameInfo *TFI = TM.getFrameInfo();
296 if (TFI->hasFP(MF))
297297 return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned));
298298 else
299299 return SystemZ_REG64 + (sizeof(SystemZ_REG64) / sizeof(unsigned));
330330 ADDR64Class::iterator
331331 ADDR64Class::allocation_order_begin(const MachineFunction &MF) const {
332332 const TargetMachine &TM = MF.getTarget();
333 const TargetRegisterInfo *RI = TM.getRegisterInfo();
334 if (RI->hasFP(MF))
333 const TargetFrameInfo *TFI = TM.getFrameInfo();
334 if (TFI->hasFP(MF))
335335 return SystemZ_ADDR64_nofp;
336336 else
337337 return SystemZ_ADDR64;
339339 ADDR64Class::iterator
340340 ADDR64Class::allocation_order_end(const MachineFunction &MF) const {
341341 const TargetMachine &TM = MF.getTarget();
342 const TargetRegisterInfo *RI = TM.getRegisterInfo();
343 if (RI->hasFP(MF))
342 const TargetFrameInfo *TFI = TM.getFrameInfo();
343 if (TFI->hasFP(MF))
344344 return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned));
345345 else
346346 return SystemZ_ADDR64 + (sizeof(SystemZ_ADDR64) / sizeof(unsigned));
367367 GR64PClass::iterator
368368 GR64PClass::allocation_order_begin(const MachineFunction &MF) const {
369369 const TargetMachine &TM = MF.getTarget();
370 const TargetRegisterInfo *RI = TM.getRegisterInfo();
371 if (RI->hasFP(MF))
370 const TargetFrameInfo *TFI = TM.getFrameInfo();
371 if (TFI->hasFP(MF))
372372 return SystemZ_REG64P_nofp;
373373 else
374374 return SystemZ_REG64P;
376376 GR64PClass::iterator
377377 GR64PClass::allocation_order_end(const MachineFunction &MF) const {
378378 const TargetMachine &TM = MF.getTarget();
379 const TargetRegisterInfo *RI = TM.getRegisterInfo();
380 if (RI->hasFP(MF))
379 const TargetFrameInfo *TFI = TM.getFrameInfo();
380 if (TFI->hasFP(MF))
381381 return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned));
382382 else
383383 return SystemZ_REG64P + (sizeof(SystemZ_REG64P) / sizeof(unsigned));
404404 GR128Class::iterator
405405 GR128Class::allocation_order_begin(const MachineFunction &MF) const {
406406 const TargetMachine &TM = MF.getTarget();
407 const TargetRegisterInfo *RI = TM.getRegisterInfo();
408 if (RI->hasFP(MF))
407 const TargetFrameInfo *TFI = TM.getFrameInfo();
408 if (TFI->hasFP(MF))
409409 return SystemZ_REG128_nofp;
410410 else
411411 return SystemZ_REG128;
413413 GR128Class::iterator
414414 GR128Class::allocation_order_end(const MachineFunction &MF) const {
415415 const TargetMachine &TM = MF.getTarget();
416 const TargetRegisterInfo *RI = TM.getRegisterInfo();
417 if (RI->hasFP(MF))
416 const TargetFrameInfo *TFI = TM.getFrameInfo();
417 if (TFI->hasFP(MF))
418418 return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned));
419419 else
420420 return SystemZ_REG128 + (sizeof(SystemZ_REG128) / sizeof(unsigned));
2828
2929 // FIXME: completely move here.
3030 extern cl::opt ForceStackAlign;
31
32 bool X86FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
33 return !MF.getFrameInfo()->hasVarSizedObjects();
34 }
35
36 /// hasFP - Return true if the specified function should have a dedicated frame
37 /// pointer register. This is true if the function has variable sized allocas
38 /// or if frame pointer elimination is disabled.
39 bool X86FrameInfo::hasFP(const MachineFunction &MF) const {
40 const MachineFrameInfo *MFI = MF.getFrameInfo();
41 const MachineModuleInfo &MMI = MF.getMMI();
42 const TargetRegisterInfo *RI = MF.getTarget().getRegisterInfo();
43
44 return (DisableFramePointerElim(MF) ||
45 RI->needsStackRealignment(MF) ||
46 MFI->hasVarSizedObjects() ||
47 MFI->isFrameAddressTaken() ||
48 MF.getInfo()->getForceFramePointer() ||
49 MMI.callsUnwindInit());
50 }
3151
3252 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
3353 if (is64Bit) {
183203 MCSymbol *Label,
184204 unsigned FramePtr) const {
185205 MachineFrameInfo *MFI = MF.getFrameInfo();
186 const X86RegisterInfo *RegInfo =
187 static_cast(MF.getTarget().getRegisterInfo());
188206 MachineModuleInfo &MMI = MF.getMMI();
189207
190208 // Add callee saved registers to move list.
193211
194212 std::vector &Moves = MMI.getFrameMoves();
195213 const TargetData *TD = MF.getTarget().getTargetData();
196 bool HasFP = RegInfo->hasFP(MF);
214 bool HasFP = hasFP(MF);
197215
198216 // Calculate amount of bytes used for return address storing.
199217 int stackGrowth =
268286 !Fn->doesNotThrow() || UnwindTablesMandatory;
269287 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
270288 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
271 bool HasFP = RegInfo->hasFP(MF);
289 bool HasFP = hasFP(MF);
272290 bool Is64Bit = STI.is64Bit();
273291 bool IsWin64 = STI.isTargetWin64();
274292 unsigned StackAlign = getStackAlignment();
595613 MaxAlign = MaxAlign ? MaxAlign : 4;
596614 }
597615
598 if (RegInfo->hasFP(MF)) {
616 if (hasFP(MF)) {
599617 // Calculate required stack adjustment.
600618 uint64_t FrameSize = StackSize - SlotSize;
601619 if (RegInfo->needsStackRealignment(MF))
3838 /// the function.
3939 void emitPrologue(MachineFunction &MF) const;
4040 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
41
42 bool hasFP(const MachineFunction &MF) const;
43 bool hasReservedCallFrame(const MachineFunction &MF) const;
44
4145 };
4246
4347 } // End llvm namespace
11711171 unsigned
11721172 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
11731173 MachineFunction &MF) const {
1174 unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0;
1174 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1175
1176 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
11751177 switch (RC->getID()) {
11761178 default:
11771179 return 0;
387387
388388 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
389389 BitVector Reserved(getNumRegs());
390 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
391
390392 // Set the stack-pointer register and its aliases as reserved.
391393 Reserved.set(X86::RSP);
392394 Reserved.set(X86::ESP);
399401 Reserved.set(X86::IP);
400402
401403 // Set the frame-pointer register and its aliases as reserved if needed.
402 if (hasFP(MF)) {
404 if (TFI->hasFP(MF)) {
403405 Reserved.set(X86::RBP);
404406 Reserved.set(X86::EBP);
405407 Reserved.set(X86::BP);
424426 // Stack Frame Processing methods
425427 //===----------------------------------------------------------------------===//
426428
427 /// hasFP - Return true if the specified function should have a dedicated frame
428 /// pointer register. This is true if the function has variable sized allocas
429 /// or if frame pointer elimination is disabled.
430 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
431 const MachineFrameInfo *MFI = MF.getFrameInfo();
432 const MachineModuleInfo &MMI = MF.getMMI();
433
434 return (DisableFramePointerElim(MF) ||
435 needsStackRealignment(MF) ||
436 MFI->hasVarSizedObjects() ||
437 MFI->isFrameAddressTaken() ||
438 MF.getInfo()->getForceFramePointer() ||
439 MMI.callsUnwindInit());
440 }
441
442429 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
443430 const MachineFrameInfo *MFI = MF.getFrameInfo();
444431 return (RealignStack &&
465452 return requiresRealignment && canRealignStack(MF);
466453 }
467454
468 bool X86RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
469 return !MF.getFrameInfo()->hasVarSizedObjects();
470 }
471
472455 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
473456 unsigned Reg, int &FrameIdx) const {
474 if (Reg == FramePtr && hasFP(MF)) {
457 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
458
459 if (Reg == FramePtr && TFI->hasFP(MF)) {
475460 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
476461 return true;
477462 }
480465
481466 int
482467 X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
483 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
468 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
484469 const MachineFrameInfo *MFI = MF.getFrameInfo();
485 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
470 int Offset = MFI->getObjectOffset(FI) - TFI->getOffsetOfLocalArea();
486471 uint64_t StackSize = MFI->getStackSize();
487472
488473 if (needsStackRealignment(MF)) {
497482 }
498483 // FIXME: Support tail calls
499484 } else {
500 if (!hasFP(MF))
485 if (!TFI->hasFP(MF))
501486 return Offset + StackSize;
502487
503488 // Skip the saved EBP.
540525 void X86RegisterInfo::
541526 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
542527 MachineBasicBlock::iterator I) const {
543 if (!hasReservedCallFrame(MF)) {
528 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
529
530 if (!TFI->hasReservedCallFrame(MF)) {
544531 // If the stack pointer can be changed after prologue, turn the
545532 // adjcallstackup instruction into a 'sub ESP, ' and the
546533 // adjcallstackdown instruction into 'add ESP, '
613600 unsigned i = 0;
614601 MachineInstr &MI = *II;
615602 MachineFunction &MF = *MI.getParent()->getParent();
603 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
616604
617605 while (!MI.getOperand(i).isFI()) {
618606 ++i;
629617 else if (AfterFPPop)
630618 BasePtr = StackPtr;
631619 else
632 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
620 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
633621
634622 // This must be part of a four operand memory reference. Replace the
635623 // FrameIndex with base register with EBP. Add an offset to the offset.
639627 int FIOffset;
640628 if (AfterFPPop) {
641629 // Tail call jmp happens after FP is popped.
642 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
643630 const MachineFrameInfo *MFI = MF.getFrameInfo();
644 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI.getOffsetOfLocalArea();
631 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
645632 } else
646633 FIOffset = getFrameIndexOffset(MF, FrameIndex);
647634
660647 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
661648 RegScavenger *RS) const {
662649 MachineFrameInfo *MFI = MF.getFrameInfo();
650 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
663651
664652 X86MachineFunctionInfo *X86FI = MF.getInfo();
665653 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
678666 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
679667 }
680668
681 if (hasFP(MF)) {
669 if (TFI->hasFP(MF)) {
682670 assert((TailCallReturnAddrDelta <= 0) &&
683671 "The Delta should always be zero or negative");
684672 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
701689 }
702690
703691 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
704 return hasFP(MF) ? FramePtr : StackPtr;
692 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
693 return TFI->hasFP(MF) ? FramePtr : StackPtr;
705694 }
706695
707696 void
110110 /// register scavenger to determine what registers are free.
111111 BitVector getReservedRegs(const MachineFunction &MF) const;
112112
113 bool hasFP(const MachineFunction &MF) const;
114
115113 bool canRealignStack(const MachineFunction &MF) const;
116114
117115 bool needsStackRealignment(const MachineFunction &MF) const;
118
119 bool hasReservedCallFrame(const MachineFunction &MF) const;
120116
121117 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
122118 int &FrameIdx) const;
298298 GR8Class::iterator
299299 GR8Class::allocation_order_end(const MachineFunction &MF) const {
300300 const TargetMachine &TM = MF.getTarget();
301 const TargetRegisterInfo *RI = TM.getRegisterInfo();
301 const TargetFrameInfo *TFI = TM.getFrameInfo();
302302 const X86Subtarget &Subtarget = TM.getSubtarget();
303303 const X86MachineFunctionInfo *MFI = MF.getInfo();
304304 // Does the function dedicate RBP / EBP to being a frame ptr?
305305 if (!Subtarget.is64Bit())
306306 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
307307 return begin() + 8;
308 else if (RI->hasFP(MF) || MFI->getReserveFP())
308 else if (TFI->hasFP(MF) || MFI->getReserveFP())
309309 // If so, don't allocate SPL or BPL.
310310 return array_endof(X86_GR8_AO_64) - 1;
311311 else
343343 GR16Class::iterator
344344 GR16Class::allocation_order_end(const MachineFunction &MF) const {
345345 const TargetMachine &TM = MF.getTarget();
346 const TargetRegisterInfo *RI = TM.getRegisterInfo();
346 const TargetFrameInfo *TFI = TM.getFrameInfo();
347347 const X86Subtarget &Subtarget = TM.getSubtarget();
348348 const X86MachineFunctionInfo *MFI = MF.getInfo();
349349 if (Subtarget.is64Bit()) {
350350 // Does the function dedicate RBP to being a frame ptr?
351 if (RI->hasFP(MF) || MFI->getReserveFP())
351 if (TFI->hasFP(MF) || MFI->getReserveFP())
352352 // If so, don't allocate SP or BP.
353353 return array_endof(X86_GR16_AO_64) - 1;
354354 else
356356 return array_endof(X86_GR16_AO_64);
357357 } else {
358358 // Does the function dedicate EBP to being a frame ptr?
359 if (RI->hasFP(MF) || MFI->getReserveFP())
359 if (TFI->hasFP(MF) || MFI->getReserveFP())
360360 // If so, don't allocate SP or BP.
361361 return begin() + 6;
362362 else
395395 GR32Class::iterator
396396 GR32Class::allocation_order_end(const MachineFunction &MF) const {
397397 const TargetMachine &TM = MF.getTarget();
398 const TargetRegisterInfo *RI = TM.getRegisterInfo();
398 const TargetFrameInfo *TFI = TM.getFrameInfo();
399399 const X86Subtarget &Subtarget = TM.getSubtarget();
400400 const X86MachineFunctionInfo *MFI = MF.getInfo();
401401 if (Subtarget.is64Bit()) {
402402 // Does the function dedicate RBP to being a frame ptr?
403 if (RI->hasFP(MF) || MFI->getReserveFP())
403 if (TFI->hasFP(MF) || MFI->getReserveFP())
404404 // If so, don't allocate ESP or EBP.
405405 return array_endof(X86_GR32_AO_64) - 1;
406406 else
408408 return array_endof(X86_GR32_AO_64);
409409 } else {
410410 // Does the function dedicate EBP to being a frame ptr?
411 if (RI->hasFP(MF) || MFI->getReserveFP())
411 if (TFI->hasFP(MF) || MFI->getReserveFP())
412412 // If so, don't allocate ESP or EBP.
413413 return begin() + 6;
414414 else
435435 GR64Class::iterator
436436 GR64Class::allocation_order_end(const MachineFunction &MF) const {
437437 const TargetMachine &TM = MF.getTarget();
438 const TargetRegisterInfo *RI = TM.getRegisterInfo();
438 const TargetFrameInfo *TFI = TM.getFrameInfo();
439439 const X86Subtarget &Subtarget = TM.getSubtarget();
440440 const X86MachineFunctionInfo *MFI = MF.getInfo();
441441 if (!Subtarget.is64Bit())
442442 return begin(); // None of these are allocatable in 32-bit.
443443 // Does the function dedicate RBP to being a frame ptr?
444 if (RI->hasFP(MF) || MFI->getReserveFP())
444 if (TFI->hasFP(MF) || MFI->getReserveFP())
445445 return end()-3; // If so, don't allocate RIP, RSP or RBP
446446 else
447447 return end()-2; // If not, just don't allocate RIP or RSP
540540 GR16_NOREXClass::iterator
541541 GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
542542 const TargetMachine &TM = MF.getTarget();
543 const TargetRegisterInfo *RI = TM.getRegisterInfo();
543 const TargetFrameInfo *TFI = TM.getFrameInfo();
544544 const X86MachineFunctionInfo *MFI = MF.getInfo();
545545 // Does the function dedicate RBP / EBP to being a frame ptr?
546 if (RI->hasFP(MF) || MFI->getReserveFP())
546 if (TFI->hasFP(MF) || MFI->getReserveFP())
547547 // If so, don't allocate SP or BP.
548548 return end() - 2;
549549 else
564564 GR32_NOREXClass::iterator
565565 GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
566566 const TargetMachine &TM = MF.getTarget();
567 const TargetRegisterInfo *RI = TM.getRegisterInfo();
567 const TargetFrameInfo *TFI = TM.getFrameInfo();
568568 const X86MachineFunctionInfo *MFI = MF.getInfo();
569569 // Does the function dedicate RBP / EBP to being a frame ptr?
570 if (RI->hasFP(MF) || MFI->getReserveFP())
570 if (TFI->hasFP(MF) || MFI->getReserveFP())
571571 // If so, don't allocate ESP or EBP.
572572 return end() - 2;
573573 else
589589 GR64_NOREXClass::iterator
590590 GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
591591 const TargetMachine &TM = MF.getTarget();
592 const TargetRegisterInfo *RI = TM.getRegisterInfo();
592 const TargetFrameInfo *TFI = TM.getFrameInfo();
593593 const X86MachineFunctionInfo *MFI = MF.getInfo();
594594 // Does the function dedicate RBP to being a frame ptr?
595 if (RI->hasFP(MF) || MFI->getReserveFP())
595 if (TFI->hasFP(MF) || MFI->getReserveFP())
596596 // If so, don't allocate RIP, RSP or RBP.
597597 return end() - 3;
598598 else
631631 GR32_NOSPClass::iterator
632632 GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
633633 const TargetMachine &TM = MF.getTarget();
634 const TargetRegisterInfo *RI = TM.getRegisterInfo();
634 const TargetFrameInfo *TFI = TM.getFrameInfo();
635635 const X86Subtarget &Subtarget = TM.getSubtarget();
636636 const X86MachineFunctionInfo *MFI = MF.getInfo();
637637 if (Subtarget.is64Bit()) {
638638 // Does the function dedicate RBP to being a frame ptr?
639 if (RI->hasFP(MF) || MFI->getReserveFP())
639 if (TFI->hasFP(MF) || MFI->getReserveFP())
640640 // If so, don't allocate EBP.
641641 return array_endof(X86_GR32_NOSP_AO_64) - 1;
642642 else
644644 return array_endof(X86_GR32_NOSP_AO_64);
645645 } else {
646646 // Does the function dedicate EBP to being a frame ptr?
647 if (RI->hasFP(MF) || MFI->getReserveFP())
647 if (TFI->hasFP(MF) || MFI->getReserveFP())
648648 // If so, don't allocate EBP.
649649 return begin() + 6;
650650 else
669669 GR64_NOSPClass::iterator
670670 GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
671671 const TargetMachine &TM = MF.getTarget();
672 const TargetRegisterInfo *RI = TM.getRegisterInfo();
672 const TargetFrameInfo *TFI = TM.getFrameInfo();
673673 const X86Subtarget &Subtarget = TM.getSubtarget();
674674 const X86MachineFunctionInfo *MFI = MF.getInfo();
675675 if (!Subtarget.is64Bit())
676676 return begin(); // None of these are allocatable in 32-bit.
677677 // Does the function dedicate RBP to being a frame ptr?
678 if (RI->hasFP(MF) || MFI->getReserveFP())
678 if (TFI->hasFP(MF) || MFI->getReserveFP())
679679 return end()-1; // If so, don't allocate RBP
680680 else
681681 return end(); // If not, any reg in this class is ok.
697697 GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const
698698 {
699699 const TargetMachine &TM = MF.getTarget();
700 const TargetRegisterInfo *RI = TM.getRegisterInfo();
700 const TargetFrameInfo *TFI = TM.getFrameInfo();
701701 const X86MachineFunctionInfo *MFI = MF.getInfo();
702702 // Does the function dedicate RBP to being a frame ptr?
703 if (RI->hasFP(MF) || MFI->getReserveFP())
703 if (TFI->hasFP(MF) || MFI->getReserveFP())
704704 // If so, don't allocate RBP.
705705 return end() - 1;
706706 else
8181 // Do nothing
8282 }
8383
84 bool XCoreFrameInfo::hasFP(const MachineFunction &MF) const {
85 return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects();
86 }
87
8488 void XCoreFrameInfo::emitPrologue(MachineFunction &MF) const {
8589 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
8690 MachineBasicBlock::iterator MBBI = MBB.begin();
9397 XCoreFunctionInfo *XFI = MF.getInfo();
9498 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
9599
96 bool FP = RegInfo->hasFP(MF);
100 bool FP = hasFP(MF);
97101
98102 // Work out frame sizes.
99103 int FrameSize = MFI->getStackSize();
203207 MachineBasicBlock &MBB) const {
204208 MachineFrameInfo *MFI = MF.getFrameInfo();
205209 MachineBasicBlock::iterator MBBI = prior(MBB.end());
206 const XCoreRegisterInfo *RegInfo =
207 static_cast(MF.getTarget().getRegisterInfo());
208210 const XCoreInstrInfo &TII =
209211 *static_cast(MF.getTarget().getInstrInfo());
210212 DebugLoc dl = MBBI->getDebugLoc();
211213
212 bool FP = RegInfo->hasFP(MF);
213
214 bool FP = hasFP(MF);
214215 if (FP) {
215216 // Restore the stack pointer.
216217 unsigned FramePtr = XCore::R10;
3030 void emitPrologue(MachineFunction &MF) const;
3131 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
3232
33 bool hasFP(const MachineFunction &MF) const;
34
3335 //! Stack slot size (4 bytes)
3436 static int stackSlotSize() {
3537 return 4;
8383
8484 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
8585 BitVector Reserved(getNumRegs());
86 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
87
8688 Reserved.set(XCore::CP);
8789 Reserved.set(XCore::DP);
8890 Reserved.set(XCore::SP);
8991 Reserved.set(XCore::LR);
90 if (hasFP(MF)) {
92 if (TFI->hasFP(MF)) {
9193 Reserved.set(XCore::R10);
9294 }
9395 return Reserved;
9597
9698 bool
9799 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
100 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
101
98102 // TODO can we estimate stack size?
99 return hasFP(MF);
100 }
101
102 bool XCoreRegisterInfo::hasFP(const MachineFunction &MF) const {
103 return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects();
103 return TFI->hasFP(MF);
104104 }
105105
106106 // This function eliminates ADJCALLSTACKDOWN,
108108 void XCoreRegisterInfo::
109109 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
110110 MachineBasicBlock::iterator I) const {
111 if (!hasReservedCallFrame(MF)) {
111 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
112
113 if (!TFI->hasReservedCallFrame(MF)) {
112114 // Turn the adjcallstackdown instruction into 'extsp ' and the
113115 // adjcallstackup instruction into 'ldaw sp, sp[]'
114116 MachineInstr *Old = I;
171173 int FrameIndex = FrameOp.getIndex();
172174
173175 MachineFunction &MF = *MI.getParent()->getParent();
176 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
174177 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
175178 int StackSize = MF.getFrameInfo()->getStackSize();
176179
196199
197200 Offset/=4;
198201
199 bool FP = hasFP(MF);
202 bool FP = TFI->hasFP(MF);
200203
201204 unsigned Reg = MI.getOperand(0).getReg();
202205 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
295298 XCoreRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
296299 RegScavenger *RS) const {
297300 MachineFrameInfo *MFI = MF.getFrameInfo();
301 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
298302 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
299303 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
300304 XCoreFunctionInfo *XFI = MF.getInfo();
319323 RC->getAlignment(),
320324 false));
321325 }
322 if (hasFP(MF)) {
326 if (TFI->hasFP(MF)) {
323327 // A callee save register is used to hold the FP.
324328 // This needs saving / restoring in the epilogue / prologue.
325329 XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
350354 }
351355
352356 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
353 bool FP = hasFP(MF);
354
355 return FP ? XCore::R10 : XCore::SP;
357 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
358
359 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
356360 }
357361
358362 unsigned XCoreRegisterInfo::getRARegister() const {
4747
4848 bool requiresRegisterScavenging(const MachineFunction &MF) const;
4949
50 bool hasFP(const MachineFunction &MF) const;
51
5250 void eliminateCallFramePseudoInstr(MachineFunction &MF,
5351 MachineBasicBlock &MBB,
5452 MachineBasicBlock::iterator I) const;
6060 GRRegsClass::iterator
6161 GRRegsClass::allocation_order_end(const MachineFunction &MF) const {
6262 const TargetMachine &TM = MF.getTarget();
63 const TargetRegisterInfo *RI = TM.getRegisterInfo();
64 if (RI->hasFP(MF))
63 const TargetFrameInfo *TFI = TM.getFrameInfo();
64 if (TFI->hasFP(MF))
6565 return end()-1; // don't allocate R10
6666 else
6767 return end();