llvm.org GIT mirror llvm / d0885af
[GlobalISel][X86] clang-format. NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298590 91177308-0d34-0410-b5e6-96231b3b80d8 Igor Breger 3 years ago
5 changed file(s) with 18 addition(s) and 21 deletion(s). Raw diff Collapse all Expand all
1313 //===----------------------------------------------------------------------===//
1414
1515 #include "X86CallLowering.h"
16 #include "X86CallingConv.h"
1617 #include "X86ISelLowering.h"
1718 #include "X86InstrInfo.h"
1819 #include "X86TargetMachine.h"
19 #include "X86CallingConv.h"
2020
2121 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
2223 #include "llvm/CodeGen/MachineValueType.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
2424 #include "llvm/Target/TargetSubtargetInfo.h"
2525
2626 using namespace llvm;
115115 });
116116
117117 FuncReturnHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
118 if(!handleAssignments(MIRBuilder, SplitArgs, Handler))
118 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
119119 return false;
120120 }
121121
136136 int FI = MFI.CreateFixedObject(Size, Offset, true);
137137 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
138138
139 unsigned AddrReg =
140 MRI.createGenericVirtualRegister(LLT::pointer(0,
141 DL.getPointerSizeInBits(0)));
139 unsigned AddrReg = MRI.createGenericVirtualRegister(
140 LLT::pointer(0, DL.getPointerSizeInBits(0)));
142141 MIRBuilder.buildFrameIndex(AddrReg, FI);
143142 return AddrReg;
144143 }
160159
161160 const DataLayout &DL;
162161 };
163 }
162 } // namespace
164163
165164 bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
166165 const Function &F,
168167 if (F.arg_empty())
169168 return true;
170169
171 //TODO: handle variadic function
170 // TODO: handle variadic function
172171 if (F.isVarArg())
173172 return false;
174173
202201
203202 MachineBasicBlock &MBB = MIRBuilder.getMBB();
204203 if (!MBB.empty())
205 MIRBuilder.setInstr(*MBB.begin());
204 MIRBuilder.setInstr(*MBB.begin());
206205
207206 FormalArgHandler Handler(MIRBuilder, MRI, CC_X86, DL);
208207 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
117117 // No need to constrain SrcReg. It will get constrained when
118118 // we hit another of its use or its defs.
119119 // Copies do not have constraints.
120 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
120 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
121121 if (!OldRC || !RC->hasSubClassEq(OldRC)) {
122122 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
123 DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
124 << " operand\n");
125 return false;
126 }
123 DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
124 << " operand\n");
125 return false;
126 }
127127 }
128128 I.setDesc(TII.get(X86::COPY));
129129 return true;
151151 assert(I.getNumOperands() == I.getNumExplicitOperands() &&
152152 "Generic instruction has unexpected implicit operands\n");
153153
154 // TODO: This should be implemented by tblgen, pattern with predicate not supported yet.
154 // TODO: This should be implemented by tblgen, pattern with predicate not
155 // supported yet.
155156 if (selectBinaryOp(I, MRI))
156157 return true;
157158
299300
300301 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
301302 }
302
8484 for (unsigned BinOp : {G_ADD, G_SUB})
8585 for (auto Ty : {v4s32})
8686 setAction({BinOp, Ty}, Legal);
87
8887 }
7171 unsigned NumOperands = MI.getNumOperands();
7272 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
7373
74 if (NumOperands != 3 ||
75 (Ty != MRI.getType(MI.getOperand(1).getReg())) ||
74 if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) ||
7675 (Ty != MRI.getType(MI.getOperand(2).getReg())))
7776 llvm_unreachable("Unsupported operand maping yet.");
7877
105104 ValMapIdx = VMI_3OpsFp64Idx;
106105 break;
107106 default:
108 llvm_unreachable("Unsupported register size.");
107 llvm_unreachable("Unsupported register size.");
109108 }
110109 }
111110 } else {
4949 InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
5050 };
5151
52 } // End llvm namespace.
52 } // namespace llvm
5353 #endif