llvm.org GIT mirror llvm / d05a658
AVX-512: optimized scalar compare patterns removed AVX512SI format, since it is similar to AVX512BI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199217 91177308-0d34-0410-b5e6-96231b3b80d8 Elena Demikhovsky 6 years ago
4 changed file(s) with 50 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
1023410234 if (!Invert) return Op0;
1023510235
1023610236 CCode = X86::GetOppositeBranchCondition(CCode);
10237 return DAG.getNode(X86ISD::SETCC, dl, VT,
10237 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
1023810238 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10239 if (VT == MVT::i1)
10240 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10241 return SetCC;
1023910242 }
1024010243 }
1024110244
1024610249
1024710250 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
1024810251 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10249 return DAG.getNode(X86ISD::SETCC, dl, VT,
10252 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
1025010253 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10254 if (VT == MVT::i1)
10255 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10256 return SetCC;
1025110257 }
1025210258
1025310259 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
1769517701 // See X86ATTInstPrinter.cpp:printSSECC().
1769617702 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
1769717703 if (Subtarget->hasAVX512()) {
17698 // SETCC type in AVX-512 is MVT::i1
17699 assert(N->getValueType(0) == MVT::i1 && "Unexpected AND node type");
17700 return DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00, CMP01,
17704 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00, CMP01,
1770117705 DAG.getConstant(x86cc, MVT::i8));
17706 if (N->getValueType(0) != MVT::i1)
17707 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0), FSetCC);
17708 return FSetCC;
1770217709 }
1770317710 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL, CMP00.getValueType(), CMP00, CMP01,
1770417711 DAG.getConstant(x86cc, MVT::i8));
13551355 }
13561356 // Move Int Doubleword to Packed Double Int
13571357 //
1358 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1358 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
13591359 "vmovd\t{$src, $dst|$dst, $src}",
13601360 [(set VR128X:$dst,
13611361 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
13621362 EVEX, VEX_LIG;
1363 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1363 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
13641364 "vmovd\t{$src, $dst|$dst, $src}",
13651365 [(set VR128X:$dst,
13661366 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
13671367 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1368 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1368 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
13691369 "vmovq\t{$src, $dst|$dst, $src}",
13701370 [(set VR128X:$dst,
13711371 (v2i64 (scalar_to_vector GR64:$src)))],
13721372 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
13731373 let isCodeGenOnly = 1 in {
1374 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1374 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
13751375 "vmovq\t{$src, $dst|$dst, $src}",
13761376 [(set FR64:$dst, (bitconvert GR64:$src))],
13771377 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1378 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1378 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
13791379 "vmovq\t{$src, $dst|$dst, $src}",
13801380 [(set GR64:$dst, (bitconvert FR64:$src))],
13811381 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
13821382 }
1383 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1383 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
13841384 "vmovq\t{$src, $dst|$dst, $src}",
13851385 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
13861386 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
13891389 // Move Int Doubleword to Single Scalar
13901390 //
13911391 let isCodeGenOnly = 1 in {
1392 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1392 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
13931393 "vmovd\t{$src, $dst|$dst, $src}",
13941394 [(set FR32X:$dst, (bitconvert GR32:$src))],
13951395 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
13961396
1397 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1397 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
13981398 "vmovd\t{$src, $dst|$dst, $src}",
13991399 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
14001400 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
14011401 }
14021402
1403 // Move Packed Doubleword Int to Packed Double Int
1403 // Move doubleword from xmm register to r/m32
14041404 //
1405 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1405 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
14061406 "vmovd\t{$src, $dst|$dst, $src}",
14071407 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
14081408 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
14091409 EVEX, VEX_LIG;
1410 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1410 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
14111411 (ins i32mem:$dst, VR128X:$src),
14121412 "vmovd\t{$src, $dst|$dst, $src}",
14131413 [(store (i32 (vector_extract (v4i32 VR128X:$src),
14141414 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
14151415 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
14161416
1417 // Move Packed Doubleword Int first element to Doubleword Int
1417 // Move quadword from xmm1 register to r/m64
14181418 //
14191419 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
14201420 "vmovq\t{$src, $dst|$dst, $src}",
14341434 // Move Scalar Single to Double Int
14351435 //
14361436 let isCodeGenOnly = 1 in {
1437 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1437 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
14381438 (ins FR32X:$src),
14391439 "vmovd\t{$src, $dst|$dst, $src}",
14401440 [(set GR32:$dst, (bitconvert FR32X:$src))],
14411441 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1442 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1442 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
14431443 (ins i32mem:$dst, FR32X:$src),
14441444 "vmovd\t{$src, $dst|$dst, $src}",
14451445 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
14481448
14491449 // Move Quadword Int to Packed Quadword Int
14501450 //
1451 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1451 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
14521452 (ins i64mem:$src),
14531453 "vmovq\t{$src, $dst|$dst, $src}",
14541454 [(set VR128X:$dst,
643643 list pattern, InstrItinClass itin = NoItinerary>
644644 : Ii8, PD,
645645 Requires<[HasAVX512]>;
646 class AVX512SI o, Format F, dag outs, dag ins, string asm,
647 list pattern, InstrItinClass itin = NoItinerary>
648 : I, PD,
649 Requires<[HasAVX512]>;
650646 class AVX512AIi8 o, Format F, dag outs, dag ins, string asm,
651647 list pattern, InstrItinClass itin = NoItinerary>
652648 : Ii8, TAPD,
7272 return: ; preds = %if.end, %entry
7373 %retval.0 = phi float [ %cond, %if.end ], [ %p, %entry ]
7474 ret float %retval.0
75 }
75 }
76
77 ; CHECK-LABEL: test6
78 ; CHECK: cmpl
79 ; CHECK-NOT: kmov
80 ; CHECK: ret
81 define i32 @test6(i32 %a, i32 %b) {
82 %cmp = icmp eq i32 %a, %b
83 %res = zext i1 %cmp to i32
84 ret i32 %res
85 }
86
87 ; CHECK-LABEL: test7
88 ; CHECK: vucomisd
89 ; CHECK-NOT: kmov
90 ; CHECK: ret
91 define i32 @test7(double %x, double %y) #2 {
92 entry:
93 %0 = fcmp one double %x, %y
94 %or = zext i1 %0 to i32
95 ret i32 %or
96 }
97