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[mips] Guard indirect and tailcall pseudo instructions correctly. Previously these pseudo instructions were not guarded by ISA, so their select was dependant on the ordering of the entries in the DAG matcher. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39723 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317681 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Dardis 1 year, 11 months ago
5 changed file(s) with 98 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
18821882 }
18831883
18841884 def TAILCALL_MMR6 : TailCall, ISA_MICROMIPS32R6;
1885
1886 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1887 (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1888
1889 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1890 (TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1891
10611061 (LW_MM addr:$addr)>;
10621062 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
10631063 (SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
1064
1065 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1066 (TAILCALL_MM tglobaladdr:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
1067 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1068 (TAILCALL_MM texternalsym:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
1069 }
1064 }
1065
1066 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1067 (TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1068 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1069 (TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
10701070
10711071 let AddedComplexity = 40 in {
10721072 def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
211211 AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
212212 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
213213 AssemblerPredicate<"FeatureMips16">;
214 def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">,
215 AssemblerPredicate<"!FeatureMips16">;
214216 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
215217 AssemblerPredicate<"FeatureCnMips">;
216218 def NotCnMips : Predicate<"!Subtarget->hasCnMips()">,
15431545 PseudoInstExpansion<(JumpInst Opnd:$target)>;
15441546
15451547 class TailCallReg :
1546 MipsPseudo<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
1548 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
15471549 }
15481550
15491551 class BAL_BR_Pseudo :
20862088 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
20872089 def BAL_BR : BAL_BR_Pseudo;
20882090
2089 let Predicates = [NotInMicroMips] in {
2091 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in {
20902092 def TAILCALL : TailCall;
20912093 }
20922094
21032105 let isBranch = 1;
21042106 let isIndirectBranch = 1;
21052107 bit isCTI = 1;
2108 let Predicates = [NotInMips16Mode];
21062109 }
21072110
21082111 def PseudoIndirectBranch : PseudoIndirectBranchBase;
27762779 // (JALR GPR32:$dst)>;
27772780
27782781 // Tail call
2779 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
2780 (TAILCALL tglobaladdr:$dst)>;
2781 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
2782 (TAILCALL texternalsym:$dst)>;
2782 let AdditionalPredicates = [NotInMicroMips] in {
2783 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
2784 (TAILCALL tglobaladdr:$dst)>;
2785 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
2786 (TAILCALL texternalsym:$dst)>;
2787 }
27832788 // hi/lo relocs
27842789 multiclass MipsHiLoRelocs
27852790 Register ZeroReg, RegisterOperand GPROpnd> {
0 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
1 ; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC %s
2 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
3 ; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC %s
4 ; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \
5 ; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC64 %s
6 ; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \
7 ; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC64 %s
8 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
9 ; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s
10 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
11 ; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s
12 ; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
13 ; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s
14 ; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
15 ; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s
16 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
17 ; RUN: -relocation-model=pic -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s
18 ; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
19 ; RUN: -relocation-model=static -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s
20
21 ; REQUIRES: asserts
22
23 ; Test that the correct pseudo instructions are generated for indirect
24 ; branches and tail calls. Previously, the order of the DAG matcher table
25 ; determined if the correct instruction was selected for mips16.
26
27 declare protected void @a()
28
29 define void @test1(i32 %a) {
30 entry:
31 %0 = trunc i32 %a to i1
32 %1 = select i1 %0,
33 i8* blockaddress(@test1, %bb),
34 i8* blockaddress(@test1, %bb6)
35 indirectbr i8* %1, [label %bb, label %bb6]
36
37 ; STATIC: PseudoIndirectBranch
38 ; STATIC-MM: PseudoIndirectBranch
39 ; STATIC-NOT: PseudoIndirectBranch64
40 ; STATIC64: PseudoIndirectBranch64
41 ; PIC: PseudoIndirectBranch
42 ; PIC-NOT: PseudoIndirectBranch64
43 ; PIC64: PseudoIndirectBranch64
44 ; MIPS16: JrcRx16
45 bb:
46 ret void
47
48 bb6:
49 tail call void @a()
50
51 ; STATIC: TAILCALL
52 ; STATIC-NOT: TAILCALL_MM
53 ; STATIC-MM: TAILCALL_MM
54 ; PIC: TAILCALLREG
55 ; PIC-NOT: TAILCALLREG64
56 ; PIC64: TAILCALLREG64
57 ; MIPS16: RetRA16
58 ret void
59 }
2626 ; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \
2727 ; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
2828 ; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
29 ; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
29 ; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6
3030 ; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \
3131 ; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM
3232 ; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \
5050 ; PIC32MM: jalr $25
5151 ; PIC32R6: jalr $25
5252 ; STATIC32: jal
53 ; STATIC32MMR6: jal
5354 ; N64: jalr $25
5455 ; N64R6: jalr $25
5556 ; PIC16: jalrc
6768 ; PIC32MM: jalr $25
6869 ; PIC32R6: jalr $25
6970 ; STATIC32: jal
71 ; STATIC32MMR6: jal
7072 ; N64: jalr $25
7173 ; N64R6: jalr $25
7274 ; PIC16: jalrc
8486 ; PIC32R6: jalr $25
8587 ; PIC32MM: jalr $25
8688 ; STATIC32: jal
89 ; STATIC32MMR6: jal
8790 ; N64: jalr $25
8891 ; N64R6: jalr $25
8992 ; PIC16: jalrc
101104 ; PIC32R6: jalr $25
102105 ; PIC32MM: jalr $25
103106 ; STATIC32: jal
107 ; SATATIC32MMR6: jal
104108 ; PIC64: jalr $25
105109 ; STATIC64: jal
106110 ; N64R6: jalr $25
119123 ; PIC32R6: jr $25
120124 ; PIC32MM: jr
121125 ; STATIC32: j
126 ; STATIC32MMR6: bc
122127 ; PIC64: jr $25
123128 ; STATIC64: j
124129 ; PIC16: jalrc
160165 ; PIC32R6: jrc $25
161166 ; PIC32MM: jrc
162167 ; STATIC32: j
168 ; STATIC32MMR6: bc
163169 ; PIC64: jr $25
164170 ; PIC64R6: jrc $25
165171 ; PIC64R6MM: jr $25
177183 ; PIC32R6: jalr $25
178184 ; PIC32MM: jalr $25
179185 ; STATIC32: jal
186 ; STATIC32MMR6: jal
180187 ; PIC64: jalr $25
181188 ; STATIC64: jal
182189 ; PIC16: jalrc
198205 ; PIC32R6: jrc $25
199206 ; PIC32MM: jrc
200207 ; STATIC32: j
208 ; STATIC32MMR6: bc
201209 ; PIC64: jr $25
202210 ; STATIC64: j
203211 ; PIC64R6: jrc $25
213221 ; PIC32R6: jalrc $25
214222 ; PIC32MM: jalr $25
215223 ; STATIC32: jal
224 ; STATIC32MMR6: jal
216225 ; STATIC64: jal
217226 ; PIC64: jalr $25
218227 ; PIC64R6: jalrc $25
231240 ; PIC32R6: jalr $25
232241 ; PIC32MM: jalr $25
233242 ; STATIC32: jal
243 ; STATIC32MMR6: jal
234244 ; STATIC64: jal
235245 ; PIC64: jalr $25
236246 ; PIC64R6: jalr $25
249259 ; PIC32R6: jalrc $25
250260 ; PIC32MM: jalr $25
251261 ; STATIC32: jal
262 ; STATIC32MMR6: jal
252263 ; STATIC64: jal
253264 ; PIC64: jalr $25
254265 ; PIC64R6: jalrc $25
269280 ; PIC32R6: jalrc $25
270281 ; PIC32MM: jalr $25
271282 ; STATIC32: jal
283 ; STATIC32MMR6: jal
272284 ; STATIC64: jal
273285 ; PIC64: jalr $25
274286 ; PIC64R6: jalrc $25
289301 ; PIC32R6: jalr $25
290302 ; PIC32MM: jalr $25
291303 ; STATIC32: jal
304 ; STATIC32MMR6: jal
292305 ; STATIC64: jal
293306 ; PIC64R6: jalr $25
294307 ; PIC64: jalr $25