llvm.org GIT mirror llvm / cfff317
AVX-512: select operation for i1 vectors like: select i1 %cond, <16 x i1> %a, <16 x i1> %b. I added pseudo-CMOV patterns to resolve the "select". Added tests for KNL and SKX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237106 91177308-0d34-0410-b5e6-96231b3b80d8 Elena Demikhovsky 5 years ago
3 changed file(s) with 100 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
13641364 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
13651365 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
13661366 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1367 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1368 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
13671369
13681370 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
13691371 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
14661468 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
14671469 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
14681470 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1471 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
14691473
14701474 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
14711475 const MVT VT = (MVT::SimpleValueType)i;
14931497 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
14941498 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
14951499 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1500 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1501 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
14961502
14971503 setOperationAction(ISD::AND, MVT::v8i32, Legal);
14981504 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1360613612 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
1360713613 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
1360813614 }
13615 }
13616
13617 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13618 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13619 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13620 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13621 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13622 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13623 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13624 Cond, Op1, Op2);
13625 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
1360913626 }
1361013627
1361113628 if (Cond.getOpcode() == ISD::SETCC) {
1948019497 case X86::CMOV_RFP32:
1948119498 case X86::CMOV_RFP64:
1948219499 case X86::CMOV_RFP80:
19500 case X86::CMOV_V8I1:
19501 case X86::CMOV_V16I1:
19502 case X86::CMOV_V32I1:
19503 case X86::CMOV_V64I1:
1948319504 return EmitLoweredSelect(MI, BB);
1948419505
1948519506 case X86::FP32_TO_INT16_IN_MEM:
517517 defm _V8I64 : CMOVrr_PSEUDO;
518518 defm _V8F64 : CMOVrr_PSEUDO;
519519 defm _V16F32 : CMOVrr_PSEUDO;
520 defm _V8I1 : CMOVrr_PSEUDO;
521 defm _V16I1 : CMOVrr_PSEUDO;
522 defm _V32I1 : CMOVrr_PSEUDO;
523 defm _V64I1 : CMOVrr_PSEUDO;
520524 } // usesCustomInserter = 1, Uses = [EFLAGS]
521525
522526 //===----------------------------------------------------------------------===//
206206 false:
207207 ret void
208208 }
209
210 ; KNL-LABEL: test8
211 ; KNL: vpxord %zmm2, %zmm2, %zmm2
212 ; KNL: jg
213 ; KNL: vpcmpltud %zmm2, %zmm1, %k1
214 ; KNL: jmp
215 ; KNL: vpcmpgtd %zmm2, %zmm0, %k1
216
217 ; SKX-LABEL: test8
218 ; SKX: jg
219 ; SKX: vpcmpltud {{.*}}, %k0
220 ; SKX: vpmovm2b
221 ; SKX: vpcmpgtd {{.*}}, %k0
222 ; SKX: vpmovm2b
223
224 define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) {
225 %cond = icmp sgt i32 %a1, %b1
226 %cmp1 = icmp sgt <16 x i32> %a, zeroinitializer
227 %cmp2 = icmp ult <16 x i32> %b, zeroinitializer
228 %mix = select i1 %cond, <16 x i1> %cmp1, <16 x i1> %cmp2
229 %res = sext <16 x i1> %mix to <16 x i8>
230 ret <16 x i8> %res
231 }
232
233 ; KNL-LABEL: test9
234 ; KNL: jg
235 ; KNL: vpmovsxbd %xmm1, %zmm0
236 ; KNL: jmp
237 ; KNL: vpmovsxbd %xmm0, %zmm0
238
239 ; SKX-LABEL: test9
240 ; SKX: vpmovb2m %xmm1, %k0
241 ; SKX: vpmovm2b %k0, %xmm0
242 ; SKX: retq
243 ; SKX: vpmovb2m %xmm0, %k0
244 ; SKX: vpmovm2b %k0, %xmm0
245
246 define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) {
247 %mask = icmp sgt i32 %a1, %b1
248 %c = select i1 %mask, <16 x i1>%a, <16 x i1>%b
249 ret <16 x i1>%c
250 }
251
252 ; KNL-LABEL: test10
253 ; KNL: jg
254 ; KNL: vpmovsxwq %xmm1, %zmm0
255 ; KNL: jmp
256 ; KNL: vpmovsxwq %xmm0, %zmm0
257
258 ; SKX-LABEL: test10
259 ; SKX: jg
260 ; SKX: vpmovw2m %xmm1, %k0
261 ; SKX: vpmovm2w %k0, %xmm0
262 ; SKX: retq
263 ; SKX: vpmovw2m %xmm0, %k0
264 ; SKX: vpmovm2w %k0, %xmm0
265 define <8 x i1> @test10(<8 x i1>%a, <8 x i1>%b, i32 %a1, i32 %b1) {
266 %mask = icmp sgt i32 %a1, %b1
267 %c = select i1 %mask, <8 x i1>%a, <8 x i1>%b
268 ret <8 x i1>%c
269 }
270
271 ; SKX-LABEL: test11
272 ; SKX: jg
273 ; SKX: vpmovd2m %xmm1, %k0
274 ; SKX: vpmovm2d %k0, %xmm0
275 ; SKX: retq
276 ; SKX: vpmovd2m %xmm0, %k0
277 ; SKX: vpmovm2d %k0, %xmm0
278 define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) {
279 %mask = icmp sgt i32 %a1, %b1
280 %c = select i1 %mask, <4 x i1>%a, <4 x i1>%b
281 ret <4 x i1>%c
282 }
283